WO2004031964A3 - Method and apparatus for reducing overhead in a data processing system with a cache - Google Patents

Method and apparatus for reducing overhead in a data processing system with a cache Download PDF

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Publication number
WO2004031964A3
WO2004031964A3 PCT/US2003/028934 US0328934W WO2004031964A3 WO 2004031964 A3 WO2004031964 A3 WO 2004031964A3 US 0328934 W US0328934 W US 0328934W WO 2004031964 A3 WO2004031964 A3 WO 2004031964A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
cache
allocates
cache line
data processing
Prior art date
Application number
PCT/US2003/028934
Other languages
French (fr)
Other versions
WO2004031964A2 (en
Inventor
Patrick Conway
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to JP2004541549A priority Critical patent/JP4559861B2/en
Priority to EP03749675A priority patent/EP1546887A2/en
Priority to AU2003267204A priority patent/AU2003267204A1/en
Publication of WO2004031964A2 publication Critical patent/WO2004031964A2/en
Publication of WO2004031964A3 publication Critical patent/WO2004031964A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

A data processor (120) recognizes a special data processing operation in which data will be stored in a cache (124) for one use only. The data processor (120) allocates a memory location to at least one cache line of the cache (124). A data producer such as a data communication driver program running on a central processing unit (122) then writes a data element to the allocated memory location. A data consumer (160) reads the data element by sending a READ ONCE request to a host bridge (130). The host bridge (130) provides the READ ONCE request to a memory controller (126), which reads the data from the cache (124) and de-allocates the at least one cache line without performing a writeback from the cache to a main memory (170). In one form the memory controller (126) de-allocates the at least one cache line by issuing a probe marking the next state of the associated cache line as invalid.
PCT/US2003/028934 2002-09-30 2003-09-18 Method and apparatus for reducing overhead in a data processing system with a cache WO2004031964A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004541549A JP4559861B2 (en) 2002-09-30 2003-09-18 Method and apparatus for reducing overhead of a data processing system with a cache
EP03749675A EP1546887A2 (en) 2002-09-30 2003-09-18 Method and apparatus for reducing overhead in a data processing system with a cache
AU2003267204A AU2003267204A1 (en) 2002-09-30 2003-09-18 Method and apparatus for reducing overhead in a data processing system with a cache

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/261,642 US7062610B2 (en) 2002-09-30 2002-09-30 Method and apparatus for reducing overhead in a data processing system with a cache
US10/261,642 2002-09-30

Publications (2)

Publication Number Publication Date
WO2004031964A2 WO2004031964A2 (en) 2004-04-15
WO2004031964A3 true WO2004031964A3 (en) 2004-10-28

Family

ID=32030034

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/028934 WO2004031964A2 (en) 2002-09-30 2003-09-18 Method and apparatus for reducing overhead in a data processing system with a cache

Country Status (8)

Country Link
US (1) US7062610B2 (en)
EP (1) EP1546887A2 (en)
JP (1) JP4559861B2 (en)
KR (1) KR101069931B1 (en)
CN (1) CN100357915C (en)
AU (1) AU2003267204A1 (en)
TW (1) TWI322944B (en)
WO (1) WO2004031964A2 (en)

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US7571286B2 (en) * 2006-08-24 2009-08-04 International Business Machines Corporation Reduced memory traffic via detection and tracking of temporally silent stores
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JP2009157608A (en) * 2007-12-26 2009-07-16 Nec Corp Cache memory system and cache memory control method
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US8185695B2 (en) * 2008-06-30 2012-05-22 Advanced Micro Devices, Inc. Snoop filtering mechanism
US8627017B2 (en) * 2008-12-30 2014-01-07 Intel Corporation Read and write monitoring attributes in transactional memory (TM) systems
US9785462B2 (en) 2008-12-30 2017-10-10 Intel Corporation Registering a user-handler in hardware for transactional memory event handling
DE102009026961A1 (en) * 2009-06-16 2010-12-23 Robert Bosch Gmbh Method for transmitting data between subscriber stations of a bus system
US8751714B2 (en) * 2010-09-24 2014-06-10 Intel Corporation Implementing quickpath interconnect protocol over a PCIe interface
US8683135B2 (en) * 2010-10-31 2014-03-25 Apple Inc. Prefetch instruction that ignores a cache hit
KR102118309B1 (en) 2012-09-19 2020-06-03 돌비 레버러토리즈 라이쎈싱 코오포레이션 Quantum dot/remote phosphor display system improvements
TWI526966B (en) 2013-11-25 2016-03-21 財團法人資訊工業策進會 A data processor and a data processing method
US9792210B2 (en) 2015-12-22 2017-10-17 Advanced Micro Devices, Inc. Region probe filter for distributed memory system
US10042762B2 (en) 2016-09-14 2018-08-07 Advanced Micro Devices, Inc. Light-weight cache coherence for data processors with limited data sharing
US10235302B2 (en) * 2016-12-12 2019-03-19 Intel Corporation Invalidating reads for cache utilization in processors
US10402349B2 (en) * 2017-02-08 2019-09-03 Arm Limited Memory controller having data access hint message for specifying the given range of one or more memory addresses
US11036658B2 (en) 2019-01-16 2021-06-15 Advanced Micro Devices, Inc. Light-weight memory expansion in a coherent memory system

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US20020087796A1 (en) * 2000-12-29 2002-07-04 Fanning Blaise B. Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device

Also Published As

Publication number Publication date
AU2003267204A8 (en) 2004-04-23
WO2004031964A2 (en) 2004-04-15
EP1546887A2 (en) 2005-06-29
TW200407709A (en) 2004-05-16
JP2006501568A (en) 2006-01-12
KR20050046814A (en) 2005-05-18
KR101069931B1 (en) 2011-10-05
US20040064651A1 (en) 2004-04-01
JP4559861B2 (en) 2010-10-13
AU2003267204A1 (en) 2004-04-23
CN1685321A (en) 2005-10-19
TWI322944B (en) 2010-04-01
CN100357915C (en) 2007-12-26
US7062610B2 (en) 2006-06-13

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