WO2004034290A2 - Method of using clock cycle-time in determining loop schedules during circuit design - Google Patents

Method of using clock cycle-time in determining loop schedules during circuit design Download PDF

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Publication number
WO2004034290A2
WO2004034290A2 PCT/US2003/031618 US0331618W WO2004034290A2 WO 2004034290 A2 WO2004034290 A2 WO 2004034290A2 US 0331618 W US0331618 W US 0331618W WO 2004034290 A2 WO2004034290 A2 WO 2004034290A2
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WO
WIPO (PCT)
Prior art keywords
clock cycle
boundaries
cycle
dependence graph
recurrence
Prior art date
Application number
PCT/US2003/031618
Other languages
French (fr)
Other versions
WO2004034290A3 (en
WO2004034290A9 (en
Inventor
Mukund Sivaraman
Shail A. Gupta
Original Assignee
Hewlett-Packard Development Company L. P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company L. P. filed Critical Hewlett-Packard Development Company L. P.
Priority to JP2004543398A priority Critical patent/JP2006502501A/en
Priority to EP03774592A priority patent/EP1550058A2/en
Priority to AU2003282707A priority patent/AU2003282707A1/en
Publication of WO2004034290A2 publication Critical patent/WO2004034290A2/en
Publication of WO2004034290A3 publication Critical patent/WO2004034290A3/en
Publication of WO2004034290A9 publication Critical patent/WO2004034290A9/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Abstract

A method for determining validity of a proposed loop iteration schedule comprising the steps of receiving a dependence graph including operations and edges between said operations (201); receiving a performance specification; receiving an assignment of latencies to operations of said dependence graph; and determing existence of a placement clock cycle-boundaries in said dependence graph such that all dependence and timing constraints are satisfied for the performance specification (206, 207).

Claims

CLAIMS What is claimed is:
1. A method for determining validity of a proposed loop iteration schedule comprising: receiving a dependence graph including operations and edges between said operations (201); receiving a performance specification; receiving an assignment of latencies to operations of said dependence graph; and determining existence of a placement of clock cycle-boundaries in said dependence graph such that all dependence and timing constraints are satisfied for said performance specification (206, 207).
2. The method of claim 1 further including: receiving a macrocell library; and assigning latencies to operations of said dependence graph.
3. The method of claim 1 further including: receiving a proposed loop iteration scheduling vector; and calculating omegas for edges included in said dependence graph.
4. The method of claim 3 wherein the existence of a placement of clock cycle-boundaries in said dependence graph is done such that: for every recurrence cycle in said dependence graph, the total number of clock cycle-boundaries so placed equals the said proposed initiation interval multiplied by the sum of the omegas for the edges belonging to said recurrence cycle, and the maximum delay between successive clock cycle-boundaries so placed is no greater than the said proposed clock cycle-time.
5. The method of claim 4 wherein said existence is determined by: enumerating all recurrence cycles in said dependence graph; for each such recurrence cycle, determining a placement of clock cycle- boundaries along said recurrence cycle such that: the total number of clock cycle-boundaries so placed equals the said proposed initiation interval multiplied by the sum of the omegas for the edges belonging to said recurrence cycle; the maximum delay between successive clock cycle-boundaries so placed is no greater than the said proposed clock cycle-time; and deriving said existence to be existence of a placement of clock cycle- boundaries along each said recurrence cycle.
6. An apparatus for validating a proposed loop iteration schedule comprising: means for assigning latency to dependence graph operations; means for calculating omegas for each of edge associated with said dependence graph operations; means for determining existence of placement of clock cycle boundaries in said dependence graph; and means for determining a validity of proposed iteration schedule vectors.
7. The apparatus of claim 6 further including: means for determining said placement of said clock cycle boundaries.
8. The apparatus of claim 6 further including means for determining a comparative cost of said proposed loop iteration schedule as a function of said placement of said clock cycle boundaries in said dependence graph.
9. The apparatus of claim 6 wherein said means for determining existence of said placement of clock cycle-boundaries includes: for every recurrence cycle in said dependence graph, the total number of clock cycle-boundaries so placed equals a proposed initiation interval multiplied by a sum of the omegas for the edges belonging to the associated recurrence cycle of said dependence graph; and the maximum delay between successive clock cycle-boundaries so placed is no greater than a proposed clock cycle-time.
10. The apparatus of claim 9 wherein said means for determining existence includes: enumerating all recurrence cycles in said dependence graph; for each such recurrence cycle, determining a placement of clock cycle- boundaries along said recurrence cycle such that: the total number of clock cycle-boundaries so placed equals the said proposed initiation interval multiplied by the sum of the omegas for the edges belonging to said recurrence cycle; the maximum delay between successive clock cycle-boundaries so placed is no greater than the said proposed clock cycle-time; and deriving said existence to be existence of a placement of clock cycle- boundaries along each said recurrence cycle.
PCT/US2003/031618 2002-10-07 2003-10-03 Method of using clock cycle-time in determining loop schedules during circuit design WO2004034290A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004543398A JP2006502501A (en) 2002-10-07 2003-10-03 How to use clock cycle time when determining loop schedule during circuit design
EP03774592A EP1550058A2 (en) 2002-10-07 2003-10-03 Method of using clock cycle-time in determining loop schedules during circuit design
AU2003282707A AU2003282707A1 (en) 2002-10-07 2003-10-03 Method of using clock cycle-time in determining loop schedules during circuit design

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/266,826 US7096438B2 (en) 2002-10-07 2002-10-07 Method of using clock cycle-time in determining loop schedules during circuit design
US10/266,826 2002-10-07

Publications (3)

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WO2004034290A2 true WO2004034290A2 (en) 2004-04-22
WO2004034290A3 WO2004034290A3 (en) 2004-12-02
WO2004034290A9 WO2004034290A9 (en) 2005-08-25

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US (1) US7096438B2 (en)
EP (1) EP1550058A2 (en)
JP (1) JP2006502501A (en)
AU (1) AU2003282707A1 (en)
WO (1) WO2004034290A2 (en)

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Publication number Priority date Publication date Assignee Title
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KR102161055B1 (en) 2013-10-07 2020-09-29 삼성전자주식회사 Method and Apparatus for instruction scheduling using software pipelining

Also Published As

Publication number Publication date
US7096438B2 (en) 2006-08-22
AU2003282707A1 (en) 2004-05-04
US20040068708A1 (en) 2004-04-08
EP1550058A2 (en) 2005-07-06
WO2004034290A3 (en) 2004-12-02
JP2006502501A (en) 2006-01-19
WO2004034290A9 (en) 2005-08-25

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