WO2004038798A2 - Stacked electronic structures including offset substrates - Google Patents

Stacked electronic structures including offset substrates Download PDF

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Publication number
WO2004038798A2
WO2004038798A2 PCT/US2003/033211 US0333211W WO2004038798A2 WO 2004038798 A2 WO2004038798 A2 WO 2004038798A2 US 0333211 W US0333211 W US 0333211W WO 2004038798 A2 WO2004038798 A2 WO 2004038798A2
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WO
WIPO (PCT)
Prior art keywords
electronic
substrate
substrates
electrical
electronic substrate
Prior art date
Application number
PCT/US2003/033211
Other languages
French (fr)
Other versions
WO2004038798A3 (en
Inventor
Glenn A. Rinne
Original Assignee
Unitive International Limited
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Filing date
Publication date
Application filed by Unitive International Limited filed Critical Unitive International Limited
Priority to AU2003301632A priority Critical patent/AU2003301632A1/en
Publication of WO2004038798A2 publication Critical patent/WO2004038798A2/en
Publication of WO2004038798A3 publication Critical patent/WO2004038798A3/en

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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Definitions

  • the present invention relates to the field of electronics, and more particularly to stacked electronic structures.
  • the integrated circuit chips are generally mounted parallel to and facing the printed circuit board such that faces of the integrated circuit chips are adjacent a face' of the circuit board.
  • This packaging technology allows a large number of input/output connections between the integrated circuit chips and the printed circuit board, especially when solder bump technology is used over the entire face of the integrated circuit chips.
  • this technology may limit a packaging density because the large faces of the integrated circuit chips are mounted adjacent the face of the printed circuit board.
  • an electronic device may include first, second, and third electronic substrates wherein the second electronic substrate may be provided between the first and third electronic substrates. More particularly, a first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates.
  • the second electronic substrate may be offset relative to the first and third electronic substrates so that a first end of the second electronic substrate extends beyond the first and third electronic substrates and so that the first and third electronic substrates extend beyond a second end of the second electronic substrate.
  • the first electrical and mechanical connection may thus be between portions of the first and third electronic substrates extending beyond the second end of the second electronic substrate.
  • a conductive trace may be provided on a surface of the third electronic substrate, with the conductive trace providing an electrical coupling between the first and second electrical and mechanical connections.
  • the electronic device may also include a third electrical and mechanical connection between the first and second electronic substrates, and a conductive trace on a surface of the first electronic substrate. More particularly, the conductive trace may provide an electrical coupling between the first and third electrical and mechanical connections.
  • the first electrical and mechanical connection may include a first conductive bump between the first and third electronic substrates
  • the second electrical and mechanical connection may include a second conductive bump between the second and third electronic substrates.
  • the first and second conductive bumps may be solder bumps, and/or the first conductive bump may have a greater volume than the second conductive bump.
  • Each of the first and third electronic substrates may include a device side having electronic circuits (such as transistors, diodes, resistors, capacitors, inductors, etc.) thereon and a backside free of electronic circuits.
  • a backside of the first electronic substrate may be adjacent the second electronic substrate
  • a device side of the third electronic substrate may be adjacent the second electronic substrate.
  • both of the first and third electronic substrates may be memory devices, and both of the first and second electrical and mechanical connections can be electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
  • the second electronic substrate may also be a memory device, and both of the first and second electrical and mechanical connections can also be electrically coupled to a data input, a data output, and/or an address input of the second electronic substrate, and to a data input, a data output, and/or an address input of the first electronic substrate.
  • the first, second, and third substrates can also have a same electrical layout such as a same integrated circuit memory layout.
  • the electronic device may also include a printed circuit board, with the first and third electronic substrates being integrated circuit device substrates having devices sides facing the printed circuit board and having backsides facing away from the printed circuit board.
  • a third electrical and mechanical connection may be provided between the first electronic substrate and the printed circuit board
  • a fourth electrical and mechanical connection may be provided ' between the second electronic substrate and the printed circuit board
  • a fifth electrical and mechanical connection may be provided between the second electronic substrate and the first electronic substrate.
  • the printed circuit board may include a first conductive pad to which the third electrical and mechanical connection is bonded and a second conductive pad to which the fourth electrical and mechanical connection is bonded, and the first conductive pad may have a greater surface area than the second conductive pad.
  • a first conductive trace may be provided on the printed circuit board providing electrical coupling between the third and fourth electrical and mechanical connections
  • a second conductive trace may be provided on the second electronic substrate providing electrical coupling between the fourth and fifth electrical and mechanical connections
  • a third conductive trace may be provided on the first electronic substrate providing electrical coupling between the fifth and first electrical and mechanical connections.
  • first and third electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the first electronic substrate, and the first and third electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
  • the electronic device may also include a fourth electronic substrate on the third electronic substrate so that the third electronic substrate is between the second and fourth electronic substrates, and a fifth electronic substrate on the fourth electronic substrate so that the fourth electronic substrate is between the third and fifth electronic substrates.
  • a third electrical and mechanical connection may be provided between the second and fourth electronic substrates
  • a fourth electrical and mechanical connection may be provided between the fourth and third electronic substrates
  • a fifth electrical and mechanical connection may be provided between the third and fifth electronic substrates.
  • the first, second, third, fourth and fifth electrical and mechanical connections may provide portions of a signal path, with an electrical coupling being provided between the signal path and an electronic circuit of the fifth electronic substrate.
  • the signal path may be free of electrical coupling with an electronic circuit of the third electronic substrate. Unique signal paths may thus be provided for particular electronic substrates in the device.
  • the electronic device may also include a heat dissipating layer between the first and second electronic substrates, and the heat dissipating layer may include a material that is thermally conductive and electrically insulating.
  • heat dissipating layers may be provided between each adjacent electronic substrate in the device, and the plurality of heat dissipating layers may be coupled to a heat sink adjacent edges of the electronic substrates.
  • an electronic device may include a printed circuit board, and first, second, and third electronic substrates.
  • the first electronic substrate may be on the printed circuit board
  • the second electronic substrate may be on the first electronic substrate with the first electronic substrate being between the printed circuit board and the second electronic substrate.
  • the third electronic substrate may be on the second electronic substrate with the second electronic substrate being between the first and third electronic substrates.
  • the second electronic substrate may be offset relative to the first and third electronic substrates so that a first end of the second electronic substrate extends beyond the first and third electronic substrates and so that the first and third electronic substrates extend beyond a second end of the second electronic substrate.
  • a first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates. More particularly, the first electrical and mechanical connection may be between portions of the first and third electronic substrates extending beyond the second end of the second electronic substrate.
  • a conductive trace may also be provided on a surface of the third electronic substrate, and the conductive trace may provide an electrical coupling between the first and second electrical and mechanical connections.
  • a third electrical and mechanical connection may be provided between the first and second electronic substrates, and a conductive trace on a surface of the first electronic substrate may provide an electrical coupling between the first and third electrical and mechanical connections.
  • the first electrical and mechanical connection may include a first conductive bump between the first and third electronic substrates
  • the second electrical and mechanical connection may include a second conductive bump between the second and third electronic substrates.
  • the first conductive bump may have a greater volume than the second conductive bump, and/or the first and second conductive bumps may be solder bumps.
  • Each of the first and third electronic substrates may include a device side having electronic circuits (such as transistors, diodes, resistors, capacitors, and/or inductors) thereon and a backside free of electronic circuits, wherein a backside of the first electronic substrate is adjacent the second electronic substrate and wherein a device side of the third electronic substrate is adjacent the second electronic substrate.
  • Both of the first and third electronic substrates may be memory devices.
  • a first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical coupling may be provided between the second and third electronic substrates.
  • both of the first and second electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
  • the second electronic substrate may also be a memory device, and both of the first and second electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the second electronic substrate, and to a data input, a data output, and/or an address input of the first electronic substrate.
  • the first, second, and third electronic substrates may have a same integrated circuit memory device layout.
  • the first and third electronic substrates may be integrated circuit device substrates having devices sides facing the printed circuit board and backsides facing away from the printed circuit board.
  • a first electrical and mechanical connection may be provided between the first and third electronic substrates, a second electrical and mechanical connection between the second and third electronic substrates, and a third electrical and mechanical connection between the first electronic substrate and the printed circuit board.
  • a fourth electrical and mechanical connection may also be provided between the second electromc substrate and the printed circuit board, and a fifth electrical and mechanical connection may be provided between the second electronic substrate and the first electronic substrate.
  • the printed circuit board may include a first conductive pad to which the third electrical and mechanical connection is bonded and a second conductive pad to which the fourth electrical and mechanical connection is bonded, and the first conductive pad may have a greater surface area than the second conductive pad.
  • a first conductive trace may be provided on the printed circuit board providing electrical coupling between the third and fourth electrical and mechanical connections
  • a second conductive trace may be provided on the second electronic substrate providing electrical coupling between the fourth and fifth electrical and mechanical connections.
  • a third conductive trace may also be provided on the first electronic substrate providing electrical coupling between the fifth and first electrical and mechanical connections.
  • the first and third electrical and mechanical connections may also be electrically coupled to a data input, a data output, and/or an address input of the first electronic substrate, and the first and third electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
  • a fourth electronic substrate may be provided on the third electronic substrate with the third electronic substrate between the second and fourth electronic substrates, and a fifth electronic substrate may be provided on the fourth electronic substrate with the fourth electronic substrate between the third and fifth electronic substrates.
  • the fourth electronic substrate may be offset relative to the first, third, and fifth electronic substrates so that a first end of the second electronic substrate extends beyond the first, third, and fifth electronic substrates, and so that the first, third, and fifth electronic substrates extend beyond a second end of the fourth electronic substrate.
  • a heat dissipating layer may be provided between the first and second electronic substrates wherein the heat dissipating layer includes a material that is thermally conductive and electrically insulating.
  • an electronic device may include first, second, and third electronic substrates, with the second electronic substrate being between the first and third electronic substrates and with each electronic substrate having opposing first and second sides.
  • a signal path may extend along the first surface of the second electronic substrate, to the second surface of the first electronic substrate, along the second surface of the first electronic substrate, to the first surface of the third electronic substrate, along the first surface of the third electronic substrate, and to the second surface of the second electronic substrate.
  • the signal path may include a first conductive trace on the first surface of the second electronic substrate, a first electrical and mechanical connection between the first surface of the second electronic substrate and the second surface of the first electronic substrate, and a second conductive trace on the second surface of the first electronic substrate.
  • the signal path may also include a second electrical and mechanical connection between the second surface of the first electronic substrate and the first surface of the third electronic substrate, a third conductive trace of the first surface of the third electronic substrate, and a third electrical and mechanical connection between the first surface of the third electronic substrate and the second surface of the second electronic substrate. More particularly, the first, second, and third electrical and mechanical connections may be respective conductive bumps.
  • the first and third electronic substrates may be integrated circuit devices, the first side of the first and third electronic substrates may be a device side, and the second side of the first and third electronic substrates may be a backside.
  • the signal path may be electrically coupled to an electronic circuit of the third 5 electronic substrate.
  • the second electronic substrate may also be an integrated circuit device, the first side of the second electronic substrate may be a device side, and the second side of the second electronic substrate may be a backside.
  • the signal path may be electrically coupled to an electronic circuit of the second electronic substrate and to an electronic circuit of the third electronic substrate.
  • first, second, and third electronic substrates may be respective memory devices.
  • the electronic device may also include a fourth electronic substrate on the third electronic substrate wherein the third electronic substrate is between the second and fourth electronic substrates.
  • the signal path may thus further extend
  • the signal path may also be electrically coupled with electronic circuits of the second and fourth substrates.
  • the signal path can be electrically coupled with an electronic circuit of the fourth electronic substrate, and the signal path may be free of electrical coupling with an electronic
  • a unique signal path may ' be provided for a particular electronic substrate of the device.
  • a heat dissipating layer may be provided between the first and second electronic substrates, and the heat dissipating layer may include a material that is thermally conductive and electrically insulating.
  • an electroinic device may include a substrate having opposing first and second surfaces, a first array of interconnection structures on the first surface of the substrate, and a second array of interconnection structures on the second surface of the substrate.
  • the first array of interconnection structures can be arranged in a first
  • the second array of interconnection structures can be arranged in a second pattern. More particularly, the second pattern can be mirror image of the first pattern.
  • the first array of interconnection structures may include an array of interconnection bumps
  • the second array of interconnection structures may include an array of conductive pads free of interconnection bumps. More particularly, the interconnection bumps may be solder bumps, and the conductive pads may be solder wettable pads.
  • a third array of interconnection structures may be provided on the first face of the substrate arranged in a third pattern, and a fourth array of interconnection structures may be provided on the second face of the substrate arranged in a fourth pattern.
  • the third array of interconnection structures may be spaced apart from the first array of interconnection structures, and the fourth array of interconnections structures may be spaced apart from the second array of interconnection structures.
  • the fourth pattern may be a mirror image of the third pattern.
  • a first plurality of conductive traces on the first surface of the substrate may provide interconnection between at least some of the interconnection structures of the first and second arrays on a one to one basis.
  • the substrate may be an integrated circuit substrate such that the ' first surface is a device side of the substrate having electronic circuits (such as transistors, diodes, resistors, capacitors, and/or inductors) thereon and the second surface is a backside of the substrate.
  • the integrated circuit device may be an integrated circuit memory device.
  • an electronic device may include first, second, and third integrated circuit substrates with the second integrated circuit substrate being between the first and second integrated circuit substrates.
  • At least one large bump may provide electrical and mechanical connection between the first and third integrated circuit substrates, and at least one small bump may provide electrical and mechanical connection between the second and third integrated circuit substrates wherein the at least one large bump has a greater volume than the at least one small bump.
  • Figure 1 is a top perspective view of an electronic device including stacked electronic substrates according to embodiments of the present invention.
  • Figures 2a and 2b are respective views of a device side and a backside of an electronic substrate from the stack of Figure 1 according to embodiments of the present invention.
  • Figure 3 is an exploded view of the electronic substrates of Figure 1 according to embodiments of the present invention.
  • Figure 4 is a bottom perspective view of the electronic device of Figure 1 according to embodiments of the present invention.
  • Figure 5 is a cross sectional view of an electronic device including stacked electronic substrates according to embodiments of the present invention.
  • Figure 6 illustrates examples of traces providing direct and shifted electrical connection between conductive pads and/or bumps according to embodiments of the present invention.
  • Figures 7a and 7b are device side and backside views of an electronic substrate according to alternate embodiments of the present invention.
  • Figure 8 illustrates examples of traces providing crossed electrical connection between conductive pads and/or bumps according to embodiments of the present invention.
  • Multilayer substrate (such as integrated circuit die) stacking structures may provide ease of fabrication, testing, and assembly. In addition, rework of a completed stack of substrates may be accomplished by allowing removal and replacement of one or more substrates in the stack.
  • Figure 1 is a perspective view of a stack of nine substrates lOa-i according to embodiments of the present invention.
  • Figure 2a is a top view of a device side 20 of one of the substrates 10 of Figure 1
  • Figure 2b is a top view of a backside 120 of one of the substrates 10 of Figure 1.
  • each substrate 10 may be slightly offset from adjacent substrates to allow room for inter-level vertical interconnections.
  • the vertical interconnections can be formed of solder bumps of at least two different vertical dimensions.
  • a first smaller dimension of interconnection bump may be used for adjacent substrate connections (such as between substrates 10a and 10b, between substrates 10b and 10c, between substrates 10c and lOd, between substrates lOd and lOe, between substrates lOe and lOf, between substrates lOf and lOg, between substrates lOg and lOh, and/or between substrates lOh and lOi).
  • a second larger dimension of interconnection may be used to traverse more than one layer (such as between substrates 10a and 10c, between substrates 10b and lOd, between substrates 10c and lOe, between substrates lOd and lOf, between substrateslOe and lOg, between substrates lOf and lOh, and/or between substrates lOg and lOi).
  • the interconnections may be provided using conductive bumps such as solder bumps.
  • the smaller bumps can be on the order of 50 microns in height while the larger bumps can be on the order of 250 microns in height.
  • the substrates lOa-i (such as silicon substrates) may be thinned to less than the height of the large bump minus the joined height of the small bumps (for example, approximately 200 microns to 225 microns).
  • Conductive traces 30 and 130 may be formed of patterned metal layers on the device side 20 and on the backside 120 of the substrates lOa-i to thereby provide horizontal/lateral interconnections.
  • the conductive traces 30 and 130 can interconnect linear arrays of conductive pads 40 and/or 50 and/or solder bumps 140 and/or 150 in a one-to-one relationship. While not visible in Figures 2a-b, conductive pads may also be provided on the device side 20 of the substrate 10 between the solder bumps 140 and/or 150 and the substrate 10.
  • a device side 20 of a substrate 10 (such as an integrated circuit die) is illustrated in Figure 2a, and a backside 120 of the substrate 10 is illustrated in Figure 2b.
  • the device side 20 may include electronic circuits (such as transistors, diodes, capacitors resistors, and/or capacitors) thereon, and the backside 120 may be free of electronic devices.
  • an insulating layer(s) may be provided on the device side 20 and/or the backside 120 to isolate the bumps 40 and/or 50, the conductive pads 140 and or 150, and or the conductive traces 30 and/or 130 from the substrate and/or electronic circuits thereon.
  • each of the substrates 10 may be an integrated circuit device such as a solid state memory device (i.e. static random access memory, dynamic random assess memory, non-volatile memory, etc.).
  • the electronic circuits on the device side 20 of the substrate 10 may provide memory, device circuitry such as memory cells, input/output buffers, address decoders, amplifiers, etc.
  • an insulating layer (such as an oxide layer, nitride layer, etc.) may provide isolation between the electronic circuits of the memory device and the bumps 40 and/or 50 and/or the traces 30.- Moreover, one or more vias in the insulating layer may provide contact between particular electronic circuits (such as input/output circuits) of the memory device and respective bumps 40 and or 50 and/or traces 30.
  • the substrate 10 may also include an insulating layer (such as an oxide or nitride layer) on the backside 120 between a semiconductor portion of the substrate 10 and the conductive pads 140 and/or 150 and/or the traces 130.
  • an insulating layer such as an oxide or nitride layer
  • conductive traces 30 can be provided between large solder bumps 50 and smaller solder bumps 40.
  • the conductive traces 30 may also be connected to active circuit(s) through vias (not shown), and the conductive traces 30 may be short relative to a long dimension of the substrate 10.
  • the conductive traces 30 may be defined to include conductive pads between the solder bumps 40 and 50 and the substrate 10.
  • conductive traces 130 may be provided to electrically connect large pads 150 to small pads 140.
  • the conductive traces 130 can have a length that is comparable to a length of the long dimension of the substrate 10. While relatively short traces 30 on the device side 20 and relatively long traces 130 on the backside 120 are illustrated in Figures 1 and 2a-b, it will be understood that the relative lengths of the traces on the device side 20 and backside 120 may be reversed, or the traces on the device side 20 and backside 120 may each extend approximately half a lengthwise dimension of the. substrate 10.
  • solder bumps may be placed on the contact pads 140 and/or 150 of the backside 120 and contact pads of the device side 20 may be free of solder bumps until bonded with another substrate.
  • active electronic circuits on the device side 20b of the second substrate 10b may be adjacent the backside 120a of the first substrate 10a and the small solder bumps 40b of the second substrate 10b may be joined to the matching small pads 140a of the first substrate 10a.
  • the position of the small pads 140a may be such that the large solder bumps 50b of the second substrate extend past the edge of the first substrate 10a and enable connection to a substrate and/or printed circuit board below the first substrate 10a.
  • a third substrate 10c can then be placed on the second substrate 10b such that the small solder bumps 40c of the third substrate 10c join to the small pads 140b of the second substrate 10b and the large solder bumps 50c of the third substrate 10c join to the large pads 150a of the first substrate 10a.
  • An exploded view of such a stack is shown in Figure 3, and a perspective bottom view of the completed stack is shown in Figure 4.
  • the solder bumps can be heated above a melting temperature of the solder and cooled to provide electrical and mechanical connections between substrates. More particularly, contact pads 140 and 150 may provide wettable surfaces to which the solder bumps can bond.
  • the large bumps 50 may provide the trans-layer interconnection between substrates separated by one or more other substrates, and the small bumps 40 may provide adjacent-layer interconnection between adjacent substrates.
  • the conductive traces 30 and 130 may tie the trans-layer and adjacent- layer interconnections together.
  • a stack of substrates lOa-c may be mounted on a substrate 210 (sucji as a printed circuit board PCB) on which conductors have been provided corresponding to the small solder bumps 40, the conductive traces 30, and the large solder bumps 50.
  • a signal path 60 may be provided from the substrate 210 through large bump 50a into conductive trace 30a along the device side of the substrate 10a to small bump 40a, and then down to a small pad 240 on the substrate 210 below, then across the face of the substrate 210 and up through the large bump 50b of the second substrate 50b.
  • the signal may then traverse the device side (active face) of the second substrate 10b through conductive trace 30b and down through small bump 40b into the small pad 140a on the backside (inactive face) of the first substrate 10a, and then through conductive trace 130a to the large pad 150a and up through the large bump 50c of the third substrate 10c.
  • This zig-zag interconnection topology may continues up through a stack of any number of substrates 10.
  • the signal path 60 is discussed above as following from the substrate 210 through the bump 50a, through the conductive trace 30a, through the bump 40a, and across the substrate 210 to the bump 50b. It will be understood, however, that the signal may be separately provided from the substrate 210 to the bump 50b and to either the bump 40a and/or the bump 50a. As shown in Figure 5, large bump 50a may be connected between the substrate 10a and the substrate 210, and large bump 50b may be connected between the substrate 10b and the substrate 210. The substrate 10a, however, is closer to the substrate 210 than the substrate 10b.
  • sizes of solder wettable conductive pads on the substrate 210 can be varied to provide a relatively parallel orientation of the substrates lOa-c relative to the substrate 210. More particularly, a pad on the substrate 210 used to bond to the bump 50a may be larger than a pad on the substrate 210 used to bond to the bump 50b.
  • Parallel traces 30 and 130 may allow for all signals to be routed to every substrate.
  • the substrates 10 may be integrated circuit memory devices, and parallel traces 30 and 130 may provide a signal bus(es) providing one or more of data input, data output, and/or address input. Accordingly, a plurality of signal paths may be provided with each signal path being electrically coupled with an input and/or output of each stacked memory device.
  • Parallel traces are illustrated in Figures 1, 2a-b, 3, and 4.
  • the traces on the device side 20 and/or on the backside 120 may cross so that integrated circuit substrates 10 of identical layout can be stacked with adjacent substrates rotated in opposing directions (and facing a same direction) and so that a signal path is electrically coupled to a same input/output on each stacked substrate.
  • conductive traces 130' on backsides of substrates may cross as illustrated in Figure 8. As shown, the conductive traces 130' may provide electrical connection between respective small conductive pads 140' and large conductive pads 150'.
  • a unique signal path(s) may be provided for a particular substrate(s).
  • a unique signal path(s) may be provided for a data input/output(s) and or a chip select input(s) for each memory device in the stack.
  • certain of the conductive traces 30' on the device side of each substrate can be shifted one position laterally as shown in Figure 6.
  • the signal paths including conductive traces SOi between small bumps 40 1 . 6 ' and large bumps 50 ⁇ ' may continue through out a stack of substrates with interconnection to an input/output of each substrate in the stack.
  • signal paths including conductive traces 30 ⁇ ' may provide a bus(es) for distribution of data input/output and/or address input to . each of substrates in a stack.
  • signal paths including conductive traces 0 8 -u may shift one position over at each substrate in a stack, and the bump 50 ⁇ 2 ' for each substrate may terminate the unique signal path for that substrate.
  • Signal paths through traces 30i may thus continue throughout the stack whereas signal paths through traces 30 8 -i 2 ' may terminate one signal at each level.
  • signal paths including conductive traces 30 ⁇ 2 ' may provide a unique signal path for each substrate for distribution of a unique data input/output and or chip select signal for each substrate.
  • the bump 50 ⁇ ' may be coupled to a data input/output or chip select input for the substrate- to receive the unique signal for the substrate.
  • the bumps 40 7 _ 12 ' and 50 7 _ ⁇ ' and the traces 30s-i 2 ' are electrically isolated from inputs/outputs of the substrate and merely provide coupling of unique signal paths to other substrates in the stack further from the printed circuit board.
  • a first substrate in a stack may receive a first unique signal from a printed circuit board through a bump 50 12 ' thereon connected to the printed circuit board.
  • a second unique data signal for a second substrate can be received through a bump 50 ⁇ ' of the first substrate
  • a third unique data signal for a third substrate can be received through bump 50 10 ' of the first substrate
  • a fourth unique data signal for a fourth substrate can be received through a bump 50 9 ' of the first substrate
  • a fifth unique data signal for a fifth substrate can be received through bump 50s' of the first substrate
  • a sixth unique data signal for a sixth substrate can be received through bump 50 ' of the first substrate.
  • the second substrate may receive the second unique data signal through bump 50 ⁇ ' thereon.
  • the third through sixth unique data. signals may be received and transmitted through bumps 50 8 - ⁇ ' and 40 9 . 12 t and traces 30 9 .i 2 ' of the second substrate without coupling to inputs/outputs of the second substrate.
  • the third substrate (including a same arrangement of small and large bumps) may receive the third unique data signal through bump 50i 2 ' thereon.
  • the fourth through sixth unique data signals may be received and transmitted through bumps 509- ⁇ ' and 4O10-12' and traces 30 10 -i2' of the third substrate without coupling to inputs/outputs of the third substrate.
  • the fourth substrate may receive the fourth unique data signal through bump 5O 1 2' thereon.
  • the fifth and sixth unique data signals may be received and transmitted through bumps SOio- ⁇ ' and 4O 1 2 ' and traces 30n-i 2 ' of the fourth substrate without coupling to inputs/outputs of the fourth substrate.
  • the fifth substrate (including a same arrangement of small and large bumps) may receive the fifth unique data signal through bump 50 ⁇ ' thereon.
  • the sixth unique data signal may be received and transmitted through bumps 50 ⁇ ' and 40 12 ' and trace 30i 2 * of the fifth substrate without coupling to inputs/outputs of the third substrate.
  • some traces may be unused (redundant) in substrates of the stack.
  • bumps 40 _s' and 50 ' and trace 30s' may be unused in the second substrate
  • bumps 40 . 9 ' and 50 . 8 ' and traces 30 8 - 9 ' may be unused in the • third substrate
  • bumps 40 . 1 o' and 50 .g' and traces 30$. ⁇ may be unused in the fourth substrate
  • bumps 4Q 8 _ ⁇ ' and 50 -io' and traces 30s-n may be unused in the fifth substrate
  • bumps 40 7 may be unused (redundant) in substrates of the stack.
  • bumps 40 _s' and 50 ' and trace 30s' may be unused in the second substrate
  • bumps 40 . 9 ' and 50 . 8 ' and traces 30 8 - 9 ' may be unused in the • third substrate
  • bumps 40 . 1 o' and 50 .g' and traces 30$. ⁇
  • traces 12 ' and 50 7 _ ⁇ ' and traces 30 8 - ⁇ ' may be unused in the sixth substrate. Accordingly, a same pattern of traces, pads, and bumps can be provided on stacked substrates (such as memory devices) having a same layout to provide a signal path(s) for data signals common to all substrates in the stack and to provide a signal path(s) unique for each of the. substrates in the stack.
  • stacked substrates may include both shifting traces (such as traces 30 8 - 12 ' illustrated in Figure 6) and crossing traces (such as traces 130' illustrated in Figure 8).
  • shifting traces and crossing traces a same input/output layout may be provided for all memory devices in a stack, with a first input/output location of each memory device being coupled to a same signal path and with a second input/output location of each memory device being coupled to a signal path unique to that memory device.
  • traces may shift and cross on the same or different sides of the substrates.
  • a same layout of input/output locations, traces, contact pads, and bumps may be provided for each substrate in a stacked structure according to embodiments of the present invention wherein alternating substrates (such as memory devices) face a same direction (device sides toward a printed circuit board) with adjacent substrates being rotated 180 degrees relative to one another.
  • solder bumps 50 may be provided on backsides 120" of substrates 10
  • solder bumps 40 may be provided on device sides 20" of the substrates.
  • Conductive traces 30" on device sides 20" of substrates 10" may thus connect bumps 40" and conductive pads 150
  • conductive traces 130" on backsides 120" may connect bumps 50" and conductive pads 140". Accordingly, conductive pads 140" on a first substrate may be bonded to small solder bumps 40" on a second substrate, and conductive pads 150" on the first substrate may be bonded to large solder bumps 50" of a third substrate.
  • all of the solder bumps could be provided on the backsides of the substrates prior to stacking and bonding substrates.
  • the small bumps could be placed on the backsides of substrates and the large bumps could be placed on the device sides of the substrates prior to stacking and bonding substrates.
  • small bumps and/or la ge bumps can be placed on both device sides and backsides of substrates prior to stacking and bonding.
  • placement of long and short conductive traces could be reversed with respect to the device sides and backsides.
  • conductive traces and/or pads may be formed on substrates by blanket deposition of metal followed by patterning, such as photolithographic patterning.
  • solder bumps may be formed by plating, such as electroplating.
  • conductive traces, conductive pads, and/or bumps for the device sides and/or backsides of substrates may be separately formed on thin flexible substrates, and the thin flexible substrates can be bonded to the electronic substrates later.
  • Conductive bumps used for interconnection can be solder, solid metal, conductive organic material, or other known connection material.
  • the conductive pads can be pins, posts, pillars, beams, springs, receptacles, sockets, and/or other mating structures for the conductive bumps.
  • the large and small bumps may be defined to include a solder bump in combination with a conductive pad (such as an under bump metallurgy layer).
  • the description of this structure showed the electronic substrates as collinear relative to the long dimensions thereof, the stacked substrate structures according to embodiments of the present invention could be provided with substrates overlapping at other angles such as 30 degrees, 45 degrees, 60 degrees, or 90 degrees. Structures including stacked substrates according to embodiments of the present invention could also be combined with other stacking and/or interconnection structures to provide additional connectivity, unique signals to certain levels, and/or other features afforded by different interconnection structures.
  • a stacked structure of integrated circuit (IC) devices may be tested prior to bonding on a printed circuit board. If it is determined that a defective IC device in the stack should be replaced, a portion of the stack on one side of the defective IC device can be clamped with a first clamp, and the remainder of the stack can be clamped with a second clamp. The stack of IC devices can then be heated above a melting temperature of the solder bumps and the clamps separated to divide the stack. The defective IC device can then be replaced and the stack re- soldered.
  • IC integrated circuit
  • thermal conductivity layers having low electrical conductivity
  • thin, high thermal conductivity layers having low electrical conductivity
  • DLC films and/or carbon fiber laminates of approximately 25 microns thickness can be provided between substrates of the stacks of Figures 1 and 4.
  • Such materials may provide relatively low electrical conductivity and relatively high lateral thermal conductivity to improve dissipation of thermal energy.
  • the thermal conductivity layers may be connected to one or more heat sinks adjacent the stack. While the thermally conductive layers may desirably be electrically insulating, the property of being electrically insulating is not required.
  • an electrically - conductive layer(s) may be used provided that it does not electrically sJhort pads, bumps, and/or traces.
  • the thermally conductive layer(s) may be electrically conductive with an electrically insulating layer thereon.
  • an electronic device may include at least first, second, and third electronic substrates, such as substrates lOb-d illustrated in Figures 1, 2a-b, 3, and 4.
  • the second electronic substrate 10c may be between the first electronic substrate 10b and the second electronic substrate lOd.
  • a first electrical and mechanical connection(s), such as solder bum ⁇ (s) 50d may be provided between the first electronic substrate 10b and the third electronic substrate lOd.
  • a second electrical and mechanical connection(s), such as solder bump(s) 40d may be provided between the second electronic substrate 10c and the third electronic substrate lOd.
  • the second electronic substrate 10c may be offset relative to the first electronic substrate 10b and third electronic substrate lOd so that a first end of the second electronic substrate 10c extends beyond the first and third electronic substrates.
  • the first electronic substrate 10b and third electronic substrate lOd may extend beyond a second end of the second electronic substrate 10c.
  • the first electronic substrate 10b may be stacked on additional substrates (such as electronic substrate 10a), and additional substrates (such as electronic substrate lOe) may be stacked on the third electronic substrate lOd.
  • Each of the first and third electronic substrates 10b and lOd may include a device side 20 having electronic circuits (such as transistors, resistors, capacitors, inductors, and/or diodes) thereon and a backside 120 free of electronic circuits thereon.
  • the first and third electronic substrates may be integrated circuit devices such as integrated circuit memory devices.
  • the second electronic substrate may also be an integrated circuit device such as an integrated circuit memory device.
  • device sides of the electronic substrates may face in a common direction.
  • one or more of the electronic substrates may be provided for interconnection only without providing electronic circuits therein.
  • even ones of the substrates of Figures 1 and 4 may be integrated circuit memory devices, and odd ones of the substrates of Figures 1 and 4 may be provided for interconnection only without providing memory functionality.
  • stack of electronic substrates of Figures 1 and 4 may be bonded to a printed circuit board.
  • stacked IC memory devices according to embodiments of the present invention may be used to increase memory capacity on a printed circuit board (PCB) without significantly increasing PCB real estate consumed by memory devices.
  • Stacked electronic substrates according to embodiments of the present invention may thus be particularly suited for use in portable electronic devices such as personal digital assistants (PDAs), pocket computers, mobile radiotelephones, etc. While stacks of substrates of a same size are discussed above, substrates of different sizes may be stacked and bonded according to embodiments of the present invention.
  • substrates may be stacked with odd substrates in the stack having a first orientation and with even substrates in the stack having a second orientation (i.e. rotated 180 degrees relative to the first substrate). More particularly, substrates in the first orientation may have a first ' redistribution of inputs/outputs to traces, pads, and/or bumps, and substrates in the second orientation may have a second redistribution of inputs/outputs to traces, pads, and/or bumps.
  • the redistribution may be reversed for substrates in the second orientation relative to substrates in the first orientation. Accordingly, a same data path may be connected to a same input/output of each substrate in the stack without crossing traces as discussed above with respect to Figure 8. Moreover, substrates may be stacked without rotating according to still more embodiments of the present invention.

Abstract

An electronic device may include first, second, and third substrates wherein the second electronic substrate is between the first and second electronic substrates. A first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates. In addition or in an alternative, an electronic device may include a printed circuit board, a first electronic substrate on the printed circuit board, a second electronic substrate on the first electronic substrate, and a third electronic substrate on the second electronic substrate. More particularly, the first electronic substrate may be between the printed circuit board and the second electronic substrate, and the second electronic substrate may be between the first and third electronic substrates. In addition, the second electronic substrate may be offset relative to the first and third electronic substrates so that a first end of the second electronic substrate extends beyond the first and third electronic substrates and so that the first and third electronic substrates extend beyond a second end of the second electronic substrate.

Description

STACKED ELECTRONIC STRUCTURES INCLUDING OFFSET
SUBSTRATES Related Application
This application claims priority from U.S. Provisional Patent Application No. 60/420,422 filed on October 22, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety. Field Of The Invention
The present invention relates to the field of electronics, and more particularly to stacked electronic structures.
Background
In packaging microelectronic devices, such as packaging integrated circuit chips on printed circuit boards, the integrated circuit chips are generally mounted parallel to and facing the printed circuit board such that faces of the integrated circuit chips are adjacent a face' of the circuit board. This packaging technology allows a large number of input/output connections between the integrated circuit chips and the printed circuit board, especially when solder bump technology is used over the entire face of the integrated circuit chips. However, this technology may limit a packaging density because the large faces of the integrated circuit chips are mounted adjacent the face of the printed circuit board.
Summary Of The Invention According to embodiments of the present invention, an electronic device may include first, second, and third electronic substrates wherein the second electronic substrate may be provided between the first and third electronic substrates. More particularly, a first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates.
In addition, the second electronic substrate may be offset relative to the first and third electronic substrates so that a first end of the second electronic substrate extends beyond the first and third electronic substrates and so that the first and third electronic substrates extend beyond a second end of the second electronic substrate. The first electrical and mechanical connection may thus be between portions of the first and third electronic substrates extending beyond the second end of the second electronic substrate. Moreover, a conductive trace may be provided on a surface of the third electronic substrate, with the conductive trace providing an electrical coupling between the first and second electrical and mechanical connections.
The electronic device may also include a third electrical and mechanical connection between the first and second electronic substrates, and a conductive trace on a surface of the first electronic substrate. More particularly, the conductive trace may provide an electrical coupling between the first and third electrical and mechanical connections.
The first electrical and mechanical connection may include a first conductive bump between the first and third electronic substrates, and the second electrical and mechanical connection may include a second conductive bump between the second and third electronic substrates. More particularly, the first and second conductive bumps may be solder bumps, and/or the first conductive bump may have a greater volume than the second conductive bump. Each of the first and third electronic substrates may include a device side having electronic circuits (such as transistors, diodes, resistors, capacitors, inductors, etc.) thereon and a backside free of electronic circuits. Moreover, a backside of the first electronic substrate may be adjacent the second electronic substrate, and a device side of the third electronic substrate may be adjacent the second electronic substrate. More particularly, both of the first and third electronic substrates may be memory devices, and both of the first and second electrical and mechanical connections can be electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate. The second electronic substrate may also be a memory device, and both of the first and second electrical and mechanical connections can also be electrically coupled to a data input, a data output, and/or an address input of the second electronic substrate, and to a data input, a data output, and/or an address input of the first electronic substrate. The first, second, and third substrates can also have a same electrical layout such as a same integrated circuit memory layout.
The electronic device may also include a printed circuit board, with the first and third electronic substrates being integrated circuit device substrates having devices sides facing the printed circuit board and having backsides facing away from the printed circuit board. In addition, a third electrical and mechanical connection may be provided between the first electronic substrate and the printed circuit board, a fourth electrical and mechanical connection may be provided ' between the second electronic substrate and the printed circuit board, and a fifth electrical and mechanical connection may be provided between the second electronic substrate and the first electronic substrate.
The printed circuit board may include a first conductive pad to which the third electrical and mechanical connection is bonded and a second conductive pad to which the fourth electrical and mechanical connection is bonded, and the first conductive pad may have a greater surface area than the second conductive pad. In addition, a first conductive trace may be provided on the printed circuit board providing electrical coupling between the third and fourth electrical and mechanical connections, a second conductive trace may be provided on the second electronic substrate providing electrical coupling between the fourth and fifth electrical and mechanical connections, and a third conductive trace may be provided on the first electronic substrate providing electrical coupling between the fifth and first electrical and mechanical connections. Moreover, the first and third electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the first electronic substrate, and the first and third electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
The electronic device may also include a fourth electronic substrate on the third electronic substrate so that the third electronic substrate is between the second and fourth electronic substrates, and a fifth electronic substrate on the fourth electronic substrate so that the fourth electronic substrate is between the third and fifth electronic substrates. In addition, a third electrical and mechanical connection may be provided between the second and fourth electronic substrates, a fourth electrical and mechanical connection may be provided between the fourth and third electronic substrates, and a fifth electrical and mechanical connection may be provided between the third and fifth electronic substrates. Moreover, the first, second, third, fourth and fifth electrical and mechanical connections may provide portions of a signal path, with an electrical coupling being provided between the signal path and an electronic circuit of the fifth electronic substrate. In addition, the signal path may be free of electrical coupling with an electronic circuit of the third electronic substrate. Unique signal paths may thus be provided for particular electronic substrates in the device.
The electronic device may also include a heat dissipating layer between the first and second electronic substrates, and the heat dissipating layer may include a material that is thermally conductive and electrically insulating. Moreover, heat dissipating layers may be provided between each adjacent electronic substrate in the device, and the plurality of heat dissipating layers may be coupled to a heat sink adjacent edges of the electronic substrates.
According to additional embodiments of the present invention, an electronic device may include a printed circuit board, and first, second, and third electronic substrates. The first electronic substrate may be on the printed circuit board, and the second electronic substrate may be on the first electronic substrate with the first electronic substrate being between the printed circuit board and the second electronic substrate. The third electronic substrate may be on the second electronic substrate with the second electronic substrate being between the first and third electronic substrates. In addition, the second electronic substrate may be offset relative to the first and third electronic substrates so that a first end of the second electronic substrate extends beyond the first and third electronic substrates and so that the first and third electronic substrates extend beyond a second end of the second electronic substrate. In addition, a first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates. More particularly, the first electrical and mechanical connection may be between portions of the first and third electronic substrates extending beyond the second end of the second electronic substrate. A conductive trace may also be provided on a surface of the third electronic substrate, and the conductive trace may provide an electrical coupling between the first and second electrical and mechanical connections. A third electrical and mechanical connection may be provided between the first and second electronic substrates, and a conductive trace on a surface of the first electronic substrate may provide an electrical coupling between the first and third electrical and mechanical connections.
The first electrical and mechanical connection may include a first conductive bump between the first and third electronic substrates, and the second electrical and mechanical connection may include a second conductive bump between the second and third electronic substrates. Moreover, the first conductive bump may have a greater volume than the second conductive bump, and/or the first and second conductive bumps may be solder bumps.
Each of the first and third electronic substrates may include a device side having electronic circuits (such as transistors, diodes, resistors, capacitors, and/or inductors) thereon and a backside free of electronic circuits, wherein a backside of the first electronic substrate is adjacent the second electronic substrate and wherein a device side of the third electronic substrate is adjacent the second electronic substrate. Both of the first and third electronic substrates may be memory devices. In addition, a first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical coupling may be provided between the second and third electronic substrates.
Moreover, both of the first and second electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate. The second electronic substrate may also be a memory device, and both of the first and second electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the second electronic substrate, and to a data input, a data output, and/or an address input of the first electronic substrate. More particularly, the first, second, and third electronic substrates may have a same integrated circuit memory device layout.
The first and third electronic substrates may be integrated circuit device substrates having devices sides facing the printed circuit board and backsides facing away from the printed circuit board. In addition, a first electrical and mechanical connection may be provided between the first and third electronic substrates, a second electrical and mechanical connection between the second and third electronic substrates, and a third electrical and mechanical connection between the first electronic substrate and the printed circuit board. A fourth electrical and mechanical connection may also be provided between the second electromc substrate and the printed circuit board, and a fifth electrical and mechanical connection may be provided between the second electronic substrate and the first electronic substrate.
The printed circuit board may include a first conductive pad to which the third electrical and mechanical connection is bonded and a second conductive pad to which the fourth electrical and mechanical connection is bonded, and the first conductive pad may have a greater surface area than the second conductive pad. In addition, a first conductive trace may be provided on the printed circuit board providing electrical coupling between the third and fourth electrical and mechanical connections, and a second conductive trace may be provided on the second electronic substrate providing electrical coupling between the fourth and fifth electrical and mechanical connections. A third conductive trace may also be provided on the first electronic substrate providing electrical coupling between the fifth and first electrical and mechanical connections. The first and third electrical and mechanical connections may also be electrically coupled to a data input, a data output, and/or an address input of the first electronic substrate, and the first and third electrical and mechanical connections may be electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
A fourth electronic substrate may be provided on the third electronic substrate with the third electronic substrate between the second and fourth electronic substrates, and a fifth electronic substrate may be provided on the fourth electronic substrate with the fourth electronic substrate between the third and fifth electronic substrates. In addition, the fourth electronic substrate may be offset relative to the first, third, and fifth electronic substrates so that a first end of the second electronic substrate extends beyond the first, third, and fifth electronic substrates, and so that the first, third, and fifth electronic substrates extend beyond a second end of the fourth electronic substrate. In addition, a heat dissipating layer may be provided between the first and second electronic substrates wherein the heat dissipating layer includes a material that is thermally conductive and electrically insulating. According to still additional embodiments of the present invention, an electronic device may include first, second, and third electronic substrates, with the second electronic substrate being between the first and third electronic substrates and with each electronic substrate having opposing first and second sides. In addition, a signal path may extend along the first surface of the second electronic substrate, to the second surface of the first electronic substrate, along the second surface of the first electronic substrate, to the first surface of the third electronic substrate, along the first surface of the third electronic substrate, and to the second surface of the second electronic substrate.
The signal path may include a first conductive trace on the first surface of the second electronic substrate, a first electrical and mechanical connection between the first surface of the second electronic substrate and the second surface of the first electronic substrate, and a second conductive trace on the second surface of the first electronic substrate. The signal path may also include a second electrical and mechanical connection between the second surface of the first electronic substrate and the first surface of the third electronic substrate, a third conductive trace of the first surface of the third electronic substrate, and a third electrical and mechanical connection between the first surface of the third electronic substrate and the second surface of the second electronic substrate. More particularly, the first, second, and third electrical and mechanical connections may be respective conductive bumps. The first and third electronic substrates may be integrated circuit devices, the first side of the first and third electronic substrates may be a device side, and the second side of the first and third electronic substrates may be a backside. The signal path may be electrically coupled to an electronic circuit of the third 5 electronic substrate. The second electronic substrate may also be an integrated circuit device, the first side of the second electronic substrate may be a device side, and the second side of the second electronic substrate may be a backside. The signal path may be electrically coupled to an electronic circuit of the second electronic substrate and to an electronic circuit of the third electronic substrate.
10 Moreover, the first, second, and third electronic substrates may be respective memory devices.
The electronic device may also include a fourth electronic substrate on the third electronic substrate wherein the third electronic substrate is between the second and fourth electronic substrates. The signal path may thus further extend
15 along the second surface of the second electronic substrate, and to a first surface of the fourth electronic substrate. The signal path may also be electrically coupled with electronic circuits of the second and fourth substrates. In addition, the signal path can be electrically coupled with an electronic circuit of the fourth electronic substrate, and the signal path may be free of electrical coupling with an electronic
20. circuit of the second electronic substrate. Accordingly, a unique signal path may ' be provided for a particular electronic substrate of the device. In addition, a heat dissipating layer may be provided between the first and second electronic substrates, and the heat dissipating layer may include a material that is thermally conductive and electrically insulating.
25 According to yet additional embodiments of the present invention, an electroinic device may include a substrate having opposing first and second surfaces, a first array of interconnection structures on the first surface of the substrate, and a second array of interconnection structures on the second surface of the substrate. The first array of interconnection structures can be arranged in a first
30 pattern, and the second array of interconnection structures can be arranged in a second pattern. More particularly, the second pattern can be mirror image of the first pattern.
The first array of interconnection structures may include an array of interconnection bumps, and the second array of interconnection structures may include an array of conductive pads free of interconnection bumps. More particularly, the interconnection bumps may be solder bumps, and the conductive pads may be solder wettable pads.
In addition, a third array of interconnection structures may be provided on the first face of the substrate arranged in a third pattern, and a fourth array of interconnection structures may be provided on the second face of the substrate arranged in a fourth pattern. Moreover, the third array of interconnection structures may be spaced apart from the first array of interconnection structures, and the fourth array of interconnections structures may be spaced apart from the second array of interconnection structures. In addition, the fourth pattern may be a mirror image of the third pattern. In addition, a first plurality of conductive traces on the first surface of the substrate may provide interconnection between at least some of the interconnection structures of the first and second arrays on a one to one basis.
Moreover, the substrate may be an integrated circuit substrate such that the ' first surface is a device side of the substrate having electronic circuits (such as transistors, diodes, resistors, capacitors, and/or inductors) thereon and the second surface is a backside of the substrate. More particularly, the integrated circuit device may be an integrated circuit memory device.
According to still more embodiments of the present invention, an electronic device may include first, second, and third integrated circuit substrates with the second integrated circuit substrate being between the first and second integrated circuit substrates. At least one large bump may provide electrical and mechanical connection between the first and third integrated circuit substrates, and at least one small bump may provide electrical and mechanical connection between the second and third integrated circuit substrates wherein the at least one large bump has a greater volume than the at least one small bump.
Brief Description Of The Drawings
Figure 1 is a top perspective view of an electronic device including stacked electronic substrates according to embodiments of the present invention.
Figures 2a and 2b are respective views of a device side and a backside of an electronic substrate from the stack of Figure 1 according to embodiments of the present invention.
Figure 3 is an exploded view of the electronic substrates of Figure 1 according to embodiments of the present invention.
Figure 4 is a bottom perspective view of the electronic device of Figure 1 according to embodiments of the present invention.
Figure 5 is a cross sectional view of an electronic device including stacked electronic substrates according to embodiments of the present invention. Figure 6 illustrates examples of traces providing direct and shifted electrical connection between conductive pads and/or bumps according to embodiments of the present invention.
Figures 7a and 7b are device side and backside views of an electronic substrate according to alternate embodiments of the present invention. Figure 8 illustrates examples of traces providing crossed electrical connection between conductive pads and/or bumps according to embodiments of the present invention.
Detailed Description The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers or substrates may also be present. It will also be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element, or intervening elements may also be present. Like numbers refer to like elements throughout.
Multilayer substrate (such as integrated circuit die) stacking structures according to embodiments of the present invention may provide ease of fabrication, testing, and assembly. In addition, rework of a completed stack of substrates may be accomplished by allowing removal and replacement of one or more substrates in the stack. Figure 1 is a perspective view of a stack of nine substrates lOa-i according to embodiments of the present invention. Figure 2a is a top view of a device side 20 of one of the substrates 10 of Figure 1, and Figure 2b is a top view of a backside 120 of one of the substrates 10 of Figure 1. As shown in Figure 1 , each substrate 10 may be slightly offset from adjacent substrates to allow room for inter-level vertical interconnections. The vertical interconnections can be formed of solder bumps of at least two different vertical dimensions. A first smaller dimension of interconnection bump may be used for adjacent substrate connections (such as between substrates 10a and 10b, between substrates 10b and 10c, between substrates 10c and lOd, between substrates lOd and lOe, between substrates lOe and lOf, between substrates lOf and lOg, between substrates lOg and lOh, and/or between substrates lOh and lOi). A second larger dimension of interconnection may be used to traverse more than one layer (such as between substrates 10a and 10c, between substrates 10b and lOd, between substrates 10c and lOe, between substrates lOd and lOf, between substrateslOe and lOg, between substrates lOf and lOh, and/or between substrates lOg and lOi). Moreover, the interconnections may be provided using conductive bumps such as solder bumps. In the structure illustrated in Figure 1, the smaller bumps can be on the order of 50 microns in height while the larger bumps can be on the order of 250 microns in height. The substrates lOa-i (such as silicon substrates) may be thinned to less than the height of the large bump minus the joined height of the small bumps (for example, approximately 200 microns to 225 microns).
Conductive traces 30 and 130 may be formed of patterned metal layers on the device side 20 and on the backside 120 of the substrates lOa-i to thereby provide horizontal/lateral interconnections. The conductive traces 30 and 130 can interconnect linear arrays of conductive pads 40 and/or 50 and/or solder bumps 140 and/or 150 in a one-to-one relationship. While not visible in Figures 2a-b, conductive pads may also be provided on the device side 20 of the substrate 10 between the solder bumps 140 and/or 150 and the substrate 10. A device side 20 of a substrate 10 (such as an integrated circuit die) is illustrated in Figure 2a, and a backside 120 of the substrate 10 is illustrated in Figure 2b. In particular, the device side 20 may include electronic circuits (such as transistors, diodes, capacitors resistors, and/or capacitors) thereon, and the backside 120 may be free of electronic devices. Moreover, an insulating layer(s) may be provided on the device side 20 and/or the backside 120 to isolate the bumps 40 and/or 50, the conductive pads 140 and or 150, and or the conductive traces 30 and/or 130 from the substrate and/or electronic circuits thereon.
According to a particular example, each of the substrates 10 may be an integrated circuit device such as a solid state memory device (i.e. static random access memory, dynamic random assess memory, non-volatile memory, etc.). Accordingly, the electronic circuits on the device side 20 of the substrate 10 may provide memory, device circuitry such as memory cells, input/output buffers, address decoders, amplifiers, etc. Moreover, an insulating layer (such as an oxide layer, nitride layer, etc.) may provide isolation between the electronic circuits of the memory device and the bumps 40 and/or 50 and/or the traces 30.- Moreover, one or more vias in the insulating layer may provide contact between particular electronic circuits (such as input/output circuits) of the memory device and respective bumps 40 and or 50 and/or traces 30.
The substrate 10 may also include an insulating layer (such as an oxide or nitride layer) on the backside 120 between a semiconductor portion of the substrate 10 and the conductive pads 140 and/or 150 and/or the traces 130. On the device side 20, conductive traces 30 (such as metal conductor lines) can be provided between large solder bumps 50 and smaller solder bumps 40. The conductive traces 30 may also be connected to active circuit(s) through vias (not shown), and the conductive traces 30 may be short relative to a long dimension of the substrate 10. In addition, the conductive traces 30 may be defined to include conductive pads between the solder bumps 40 and 50 and the substrate 10.
On the backside 120 of the substrate 10, conductive traces 130 (such as metal conductive lines) may be provided to electrically connect large pads 150 to small pads 140. In the illustrated example, the conductive traces 130 can have a length that is comparable to a length of the long dimension of the substrate 10. While relatively short traces 30 on the device side 20 and relatively long traces 130 on the backside 120 are illustrated in Figures 1 and 2a-b, it will be understood that the relative lengths of the traces on the device side 20 and backside 120 may be reversed, or the traces on the device side 20 and backside 120 may each extend approximately half a lengthwise dimension of the. substrate 10. Moreover, solder bumps may be placed on the contact pads 140 and/or 150 of the backside 120 and contact pads of the device side 20 may be free of solder bumps until bonded with another substrate. When two substrates 10a and 10b are bonded together, active electronic circuits on the device side 20b of the second substrate 10b may be adjacent the backside 120a of the first substrate 10a and the small solder bumps 40b of the second substrate 10b may be joined to the matching small pads 140a of the first substrate 10a. The position of the small pads 140a may be such that the large solder bumps 50b of the second substrate extend past the edge of the first substrate 10a and enable connection to a substrate and/or printed circuit board below the first substrate 10a. A third substrate 10c can then be placed on the second substrate 10b such that the small solder bumps 40c of the third substrate 10c join to the small pads 140b of the second substrate 10b and the large solder bumps 50c of the third substrate 10c join to the large pads 150a of the first substrate 10a. An exploded view of such a stack is shown in Figure 3, and a perspective bottom view of the completed stack is shown in Figure 4.
Once the substrates lOa-i are aligned, the solder bumps can be heated above a melting temperature of the solder and cooled to provide electrical and mechanical connections between substrates. More particularly, contact pads 140 and 150 may provide wettable surfaces to which the solder bumps can bond.
Accordingly, the large bumps 50 may provide the trans-layer interconnection between substrates separated by one or more other substrates, and the small bumps 40 may provide adjacent-layer interconnection between adjacent substrates. The conductive traces 30 and 130 may tie the trans-layer and adjacent- layer interconnections together.
As shown in the cross section of Figure 5, a stack of substrates lOa-c may be mounted on a substrate 210 (sucji as a printed circuit board PCB) on which conductors have been provided corresponding to the small solder bumps 40, the conductive traces 30, and the large solder bumps 50. A signal path 60, for example, may be provided from the substrate 210 through large bump 50a into conductive trace 30a along the device side of the substrate 10a to small bump 40a, and then down to a small pad 240 on the substrate 210 below, then across the face of the substrate 210 and up through the large bump 50b of the second substrate 50b. The signal may then traverse the device side (active face) of the second substrate 10b through conductive trace 30b and down through small bump 40b into the small pad 140a on the backside (inactive face) of the first substrate 10a, and then through conductive trace 130a to the large pad 150a and up through the large bump 50c of the third substrate 10c. This zig-zag interconnection topology may continues up through a stack of any number of substrates 10.
The signal path 60 is discussed above as following from the substrate 210 through the bump 50a, through the conductive trace 30a, through the bump 40a, and across the substrate 210 to the bump 50b. It will be understood, however, that the signal may be separately provided from the substrate 210 to the bump 50b and to either the bump 40a and/or the bump 50a. As shown in Figure 5, large bump 50a may be connected between the substrate 10a and the substrate 210, and large bump 50b may be connected between the substrate 10b and the substrate 210. The substrate 10a, however, is closer to the substrate 210 than the substrate 10b. If bumps 50a and 50b of uniform size are placed on the respective substrates 10a and 10b prior to bonding with the substrate 210, a tilting of the stack of substrates 10a-cmay result. According to embodiments of the present invention, sizes of solder wettable conductive pads on the substrate 210 can be varied to provide a relatively parallel orientation of the substrates lOa-c relative to the substrate 210. More particularly, a pad on the substrate 210 used to bond to the bump 50a may be larger than a pad on the substrate 210 used to bond to the bump 50b.
Parallel traces 30 and 130 may allow for all signals to be routed to every substrate. For example, the substrates 10 may be integrated circuit memory devices, and parallel traces 30 and 130 may provide a signal bus(es) providing one or more of data input, data output, and/or address input. Accordingly, a plurality of signal paths may be provided with each signal path being electrically coupled with an input and/or output of each stacked memory device. Parallel traces are illustrated in Figures 1, 2a-b, 3, and 4.
In an alternative, the traces on the device side 20 and/or on the backside 120 may cross so that integrated circuit substrates 10 of identical layout can be stacked with adjacent substrates rotated in opposing directions (and facing a same direction) and so that a signal path is electrically coupled to a same input/output on each stacked substrate. For example, conductive traces 130' on backsides of substrates may cross as illustrated in Figure 8. As shown, the conductive traces 130' may provide electrical connection between respective small conductive pads 140' and large conductive pads 150'. By reversing connections of traces 130' between large contact pads 150' and small contact pads 140', identical layouts of inputs/outputs and traces of substrates in the stack of Figures 1, 3, and 4 can be used with a particular signal path being electrically coupled to the same input/output of each substrate. While Figure 8 shows that traces may cross on backsides of the substrates, traces may instead cross on devices sides of the substrates.
In some designs it may be desirable to have a unique signal path(s) provided for a particular substrate(s). In some structures including a stack of integrated circuit memory devices, a unique signal path(s) may be provided for a data input/output(s) and or a chip select input(s) for each memory device in the stack.
In such a case, certain of the conductive traces 30' on the device side of each substrate (such as conductive traces 303-12') can be shifted one position laterally as shown in Figure 6. In Figure 6, the signal paths including conductive traces SOi between small bumps 401.6' and large bumps 50^' may continue through out a stack of substrates with interconnection to an input/output of each substrate in the stack. Accordingly, signal paths including conductive traces 30^' may provide a bus(es) for distribution of data input/output and/or address input to . each of substrates in a stack.
In contrast, signal paths including conductive traces 08-u may shift one position over at each substrate in a stack, and the bump 50ι2' for each substrate may terminate the unique signal path for that substrate. Signal paths through traces 30i may thus continue throughout the stack whereas signal paths through traces 308-i2' may terminate one signal at each level. Accordingly, signal paths including conductive traces 30^2' may provide a unique signal path for each substrate for distribution of a unique data input/output and or chip select signal for each substrate. In the example of Figure 6, the bump 50^' may be coupled to a data input/output or chip select input for the substrate- to receive the unique signal for the substrate. In the example of Figure 6, the bumps 407_12' and 507_π' and the traces 30s-i2' are electrically isolated from inputs/outputs of the substrate and merely provide coupling of unique signal paths to other substrates in the stack further from the printed circuit board.
By way of example, a first substrate in a stack may receive a first unique signal from a printed circuit board through a bump 5012' thereon connected to the printed circuit board. A second unique data signal for a second substrate can be received through a bump 50π' of the first substrate, a third unique data signal for a third substrate can be received through bump 5010' of the first substrate, a fourth unique data signal for a fourth substrate can be received through a bump 509' of the first substrate, a fifth unique data signal for a fifth substrate can be received through bump 50s' of the first substrate, and a sixth unique data signal for a sixth substrate can be received through bump 50 ' of the first substrate. The second substrate (including a same arrangement of small and large bumps) may receive the second unique data signal through bump 50^' thereon. The third through sixth unique data. signals may be received and transmitted through bumps 508-π' and 409.12 t and traces 309.i2' of the second substrate without coupling to inputs/outputs of the second substrate. The third substrate (including a same arrangement of small and large bumps) may receive the third unique data signal through bump 50i2' thereon. The fourth through sixth unique data signals may be received and transmitted through bumps 509-π' and 4O10-12' and traces 3010-i2' of the third substrate without coupling to inputs/outputs of the third substrate. The fourth substrate (including a same arrangement of small and large bumps) may receive the fourth unique data signal through bump 5O12' thereon. The fifth and sixth unique data signals may be received and transmitted through bumps SOio-π' and 4O1 2' and traces 30n-i2' of the fourth substrate without coupling to inputs/outputs of the fourth substrate. The fifth substrate (including a same arrangement of small and large bumps) may receive the fifth unique data signal through bump 50^' thereon. The sixth unique data signal may be received and transmitted through bumps 50π' and 4012' and trace 30i2* of the fifth substrate without coupling to inputs/outputs of the third substrate.
In the example of a stacked structure discussed above with respect to the shifting traces of Figure 6, some traces may be unused (redundant) in substrates of the stack. In particular, bumps 40 _s' and 50 ' and trace 30s' may be unused in the second substrate, bumps 40 .9' and 50 .8' and traces 308-9' may be unused in the • third substrate, bumps 40 .1o' and 50 .g' and traces 30$.^ may be unused in the fourth substrate, bumps 4Q8_π' and 50 -io' and traces 30s-n may be unused in the fifth substrate, and bumps 407.12' and 507_π' and traces 308-π' may be unused in the sixth substrate. Accordingly, a same pattern of traces, pads, and bumps can be provided on stacked substrates (such as memory devices) having a same layout to provide a signal path(s) for data signals common to all substrates in the stack and to provide a signal path(s) unique for each of the. substrates in the stack.
While the shifting of traces is discussed above with respect to traces on device sides of substrates in a stack, traces may alternately be shifted on backsides of substrates. Moreover, stacked substrates according to embodiments of the present invention may include both shifting traces (such as traces 308-12' illustrated in Figure 6) and crossing traces (such as traces 130' illustrated in Figure 8). By combining shifting traces and crossing traces, a same input/output layout may be provided for all memory devices in a stack, with a first input/output location of each memory device being coupled to a same signal path and with a second input/output location of each memory device being coupled to a signal path unique to that memory device. In addition, traces may shift and cross on the same or different sides of the substrates. In either case, a same layout of input/output locations, traces, contact pads, and bumps may be provided for each substrate in a stacked structure according to embodiments of the present invention wherein alternating substrates (such as memory devices) face a same direction (device sides toward a printed circuit board) with adjacent substrates being rotated 180 degrees relative to one another.
As discussed above with regard to Figures 1, 2a-b, 3, and 4, all bumps 40 and 50 may be provided on device sides 120 of the substrates 10 prior to stacking and bonding, and solder wettable conductive pads 140 and 150 may be provided on backsides of the substrates 10 for bonding to solder bumps of other substrates in the stack. In an alternative illustrated in Figures 7a and 7b, solder bumps 50" may be provided on backsides 120" of substrates 10", and solder bumps 40" may be provided on device sides 20" of the substrates. Conductive traces 30" on device sides 20" of substrates 10" may thus connect bumps 40" and conductive pads 150", and conductive traces 130" on backsides 120" may connect bumps 50" and conductive pads 140". Accordingly, conductive pads 140" on a first substrate may be bonded to small solder bumps 40" on a second substrate, and conductive pads 150" on the first substrate may be bonded to large solder bumps 50" of a third substrate.
In another alternative, all of the solder bumps could be provided on the backsides of the substrates prior to stacking and bonding substrates. In yet another alternative, the small bumps could be placed on the backsides of substrates and the large bumps could be placed on the device sides of the substrates prior to stacking and bonding substrates. In still other embodiments, small bumps and/or la ge bumps can be placed on both device sides and backsides of substrates prior to stacking and bonding. Moreover, placement of long and short conductive traces could be reversed with respect to the device sides and backsides.
According to some embodiments of the present invention, conductive traces and/or pads may be formed on substrates by blanket deposition of metal followed by patterning, such as photolithographic patterning. Moreover, solder bumps may be formed by plating, such as electroplating. In an alternative, conductive traces, conductive pads, and/or bumps for the device sides and/or backsides of substrates may be separately formed on thin flexible substrates, and the thin flexible substrates can be bonded to the electronic substrates later.
Conductive bumps used for interconnection can be solder, solid metal, conductive organic material, or other known connection material. Likewise the conductive pads can be pins, posts, pillars, beams, springs, receptacles, sockets, and/or other mating structures for the conductive bumps. In addition, the large and small bumps may be defined to include a solder bump in combination with a conductive pad (such as an under bump metallurgy layer). Although the description of this structure showed the electronic substrates as collinear relative to the long dimensions thereof, the stacked substrate structures according to embodiments of the present invention could be provided with substrates overlapping at other angles such as 30 degrees, 45 degrees, 60 degrees, or 90 degrees. Structures including stacked substrates according to embodiments of the present invention could also be combined with other stacking and/or interconnection structures to provide additional connectivity, unique signals to certain levels, and/or other features afforded by different interconnection structures.
According to embodiments of the present invention, a stacked structure of integrated circuit (IC) devices (such as illustrated in Figures 1 and 4) may be tested prior to bonding on a printed circuit board. If it is determined that a defective IC device in the stack should be replaced, a portion of the stack on one side of the defective IC device can be clamped with a first clamp, and the remainder of the stack can be clamped with a second clamp. The stack of IC devices can then be heated above a melting temperature of the solder bumps and the clamps separated to divide the stack. The defective IC device can then be replaced and the stack re- soldered.
For thermal management, thin, high thermal conductivity layers (having low electrical conductivity) can be provided between the substrates during the lay- up of the stack. For example, diamond-like composite (DLC) films and/or carbon fiber laminates of approximately 25 microns thickness can be provided between substrates of the stacks of Figures 1 and 4. Such materials may provide relatively low electrical conductivity and relatively high lateral thermal conductivity to improve dissipation of thermal energy. Moreover, the thermal conductivity layers may be connected to one or more heat sinks adjacent the stack. While the thermally conductive layers may desirably be electrically insulating, the property of being electrically insulating is not required. For example, an electrically - conductive layer(s) may be used provided that it does not electrically sJhort pads, bumps, and/or traces. In another alternative, the thermally conductive layer(s) may be electrically conductive with an electrically insulating layer thereon.
According to additional embodiments of the present invention, an electronic device may include at least first, second, and third electronic substrates, such as substrates lOb-d illustrated in Figures 1, 2a-b, 3, and 4. As shown, the second electronic substrate 10c may be between the first electronic substrate 10b and the second electronic substrate lOd. In addition, a first electrical and mechanical connection(s), such as solder bumρ(s) 50d, may be provided between the first electronic substrate 10b and the third electronic substrate lOd. Moreover, a second electrical and mechanical connection(s), such as solder bump(s) 40d, may be provided between the second electronic substrate 10c and the third electronic substrate lOd. As shown in Figures 1 and 4, the second electronic substrate 10c may be offset relative to the first electronic substrate 10b and third electronic substrate lOd so that a first end of the second electronic substrate 10c extends beyond the first and third electronic substrates. In addition, the first electronic substrate 10b and third electronic substrate lOd may extend beyond a second end of the second electronic substrate 10c. As further shown in Figures 1 and 4, the first electronic substrate 10b may be stacked on additional substrates (such as electronic substrate 10a), and additional substrates (such as electronic substrate lOe) may be stacked on the third electronic substrate lOd.
Each of the first and third electronic substrates 10b and lOd may include a device side 20 having electronic circuits (such as transistors, resistors, capacitors, inductors, and/or diodes) thereon and a backside 120 free of electronic circuits thereon. Accordingly, the first and third electronic substrates may be integrated circuit devices such as integrated circuit memory devices. In addition, the second electronic substrate may also be an integrated circuit device such as an integrated circuit memory device. Moreover, device sides of the electronic substrates may face in a common direction.
In an alternative, one or more of the electronic substrates may be provided for interconnection only without providing electronic circuits therein. By way of example, even ones of the substrates of Figures 1 and 4 may be integrated circuit memory devices, and odd ones of the substrates of Figures 1 and 4 may be provided for interconnection only without providing memory functionality.
In addition, the stack of electronic substrates of Figures 1 and 4 may be bonded to a printed circuit board. Accordingly, stacked IC memory devices according to embodiments of the present invention may be used to increase memory capacity on a printed circuit board (PCB) without significantly increasing PCB real estate consumed by memory devices. Stacked electronic substrates according to embodiments of the present invention may thus be particularly suited for use in portable electronic devices such as personal digital assistants (PDAs), pocket computers, mobile radiotelephones, etc. While stacks of substrates of a same size are discussed above, substrates of different sizes may be stacked and bonded according to embodiments of the present invention. Moreover, different redistributions of inputs/outputs to traces, pads, and/or bumps can be provided for different substrates in a stack according to embodiments of the present invention. For example, substrates may be stacked with odd substrates in the stack having a first orientation and with even substrates in the stack having a second orientation (i.e. rotated 180 degrees relative to the first substrate). More particularly, substrates in the first orientation may have a first ' redistribution of inputs/outputs to traces, pads, and/or bumps, and substrates in the second orientation may have a second redistribution of inputs/outputs to traces, pads, and/or bumps. More particularly, the redistribution may be reversed for substrates in the second orientation relative to substrates in the first orientation. Accordingly, a same data path may be connected to a same input/output of each substrate in the stack without crossing traces as discussed above with respect to Figure 8. Moreover, substrates may be stacked without rotating according to still more embodiments of the present invention.
While this invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

Claims

That which is claimed is:
1. An electronic device comprising: a first electronic substrate; a second electronic substrate on the first electronic substrate; a third electronic substrate on the second electronic substrate wherein the second electronic substrate is between the first and third electronic substrates; a first electrical and mechanical connection between the first and third electronic substrates wherein the first electrical and mechanical connection bypasses the second substrate; and a second electrical and mechanical connection between the second and third electronic substrates.
2. An electronic device according to Claim 1 wherein the second electronic substrate is offset relative to the first and third electronic substrates so that the first and third electronic substrates extend beyond an end of the second electronic substrate.
3. An electronic device according to Claim 2 wherein the first electrical and mechanical connection is between portions of the first and third electronic substrates extending beyond the end of the second electronic substrate.
4. An electronic device according to Claim 3 further comprising: a conductive trace on a surface of the third electronic substrate, the conductive trace providing an electrical coupling between the first and second electrical and mechanical connections.
5. An electronic device according to Claim 1 further comprising: a third electrical and mechanical connection between the first and second elecfronic substrates.
6. An elecfronic device according to Claim 5 further comprising: a conductive trace on a surface of the first electronic substrate, the conductive trace providing an electrical coupling between the first and third electrical and mechanical connections.
7. An electronic device according to Claim 1 wherein the first electrical and mechanical connection comprises a first conductive bump between the first and third electronic substrates and wherein the second electrical and mechanical connection comprises a second conductive bump between the second and third electronic substrates.
8. An electronic device according to Claim 7 wherein the first conductive bump has a greater volume than the second conductive bump.
9. An electronic device according to Claim 1 wherein each of the first and third electronic substrates includes a device side having electronic circuits thereon and a backside, wherein a backside of the first electronic substrate is adjacent the second electronic substrate and wherein a device side of the third electronic substrate is adjacent the second electronic substrate.
10. An electromc device according to Claim 9 wherein both of the first and third electronic substrates are memory devices.
11. An electronic device according to Claim 10 wherein both of the first and second electrical and mechanical connections are electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
12. An electronic device according to Claim 11 wherein the second electronic substrate comprises a memory device.
13. An electronic device according to Claim 12 wherein both of the first and second electrical and mechanical connections are electrically coupled to a data input, a data output, and/or an address input of the second electronic substrate, and to a data input, a data output, and/or an address input of the first electronic substrate.
14. An electronic device according to Claim 10 wherein the first and third electronic substrates comprise memory devices having a same layout.
15. An electronic device according to Claim 1 further comprising: a printed circuit board, wherein the first and third electronic substrates comprises integrated circuit device substrates having devices sides facing the printed circuit board and backsides facing away from the printed circuit board; a third electrical and mechanical connection between the first elecfronic substrate and the printed circuit board; a fourth electrical and mechanical connection between the second electronic substrate and the printed circuit board; and a fifth electrical and mechanical connection between the second electronic substrate and the first electronic substrate.
16. An electronic device according to Claim 15 wherein the printed circuit board includes a first conductive pad to which the third electrical and mechanical connection is bonded and a second conductive pad to which the fourth electrical and mechanical connection is bonded, wherein the first conductive pad has a greater surface area than the second conductive pad.
17. An electronic device according to Claim 15 further comprising: a first conductive trace on the printed circuit board providing electrical coupling between the third and fourth electrical and mechanical connections; a second conductive trace on the second electronic substrate providing electrical coupling between the fourth and fifth electrical and mechanical connections; and a third conductive trace on the first electronic substrate providing electrical coupling between the fifth and first electrical and mechanical connections.
18. An electronic device according to Claim 17 wherein the first and third electrical and mechanical connections are electrically coupled to a data input, a data output, and/or an address input of the first electronic substrate, and wherein the first and third electrical and mechanical connections are elecfrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
19. An electronic device according to Claim 1 further comprising: a fourth electronic substrate on the third electronic substrate so that the third electronic substrate is between the second and fourth electronic substrates; a fifth electronic substrate on the fourth electromc substrate so that the fourth electronic substrate is between the third and fifth electronic substrates; a third electrical and mechanical connection between the second and fourth electronic substrates; a fourth electrical and mechanical connection between the fourth and third electronic substrates; and a fifth elecfrical and mechanical connection between the third and fifth electronic substrates; wherein the first, second, third, fourth and fifth electrical and mechanical connections comprise portions of a signal path, wherein an electrical coupling is provided between the signal path and an electronic circuit of the fifth electronic substrate, and wherein the signal path is free of electrical coupling with an electronic circuit of the third electronic substrate.
20. An electronic device according to Claim 1 further comprising: a heat dissipating layer between the first and second electronic substrates, wherein the heat dissipating layer includes a material that is thermally conductive.
21. An electronic device comprising: a printed circuit board; a first electronic substrate on the printed circuit board; a second electronic substrate on the first electronic substrate wherein the first electronic substrate is between the printed circuit board and the second electronic substrate; and a third electronic substrate on the second electronic substrate wherein the second electronic substrate is between the first and third electronic substrates, wherein the second electronic substrate is offset relative to the first and third electronic substrates so that the first and third electronic substrates extend beyond an end of the second electronic substrate.
22. An electronic device according to Claim 21 further comprising: a first electrical and mechanical connection between the first and third electronic substrates; and a second electrical and mechanical connection between the second and third electronic substrates.
23. An electronic device according to Claim 22 wherein the first electrical and mechanical connection is between portions of the first and third electronic substrates extending beyond the end of the second electronic substrate.
24. An electronic device according to Claim 22 further comprising: a conductive trace on a surface of the third electronic substrate, the conductive trace providing an electrical coupling between the first and second electrical and mechanical connections.
25. An electronic device according to Claim 22 further comprising: a third electrical and mechanical connection between the first and second electronic substrates.
26. An electronic device according to Claim 25 further comprising: a conductive trace on a surface of the first electronic substrate, the conductive trace providing an electrical coupling between the first and third elecfrical and mechanical connections.
27. An electronic device according to Claim 21 wherein the first electrical and mechamcal connection comprises a first conductive bump between the first and third electronic substrates and wherein the second electrical and mechanical connection comprises a second conductive bump between the second and third electronic substrates.
28. An electronic device according to Claim 27 wherein the first conductive bump has a greater volume than the second conductive bump.
29. An electronic device according to Claim 21 wherein each of the first and third electronic substrates includes a device side having electronic circuits thereon and a backside, wherein a backside of the first electronic substrate is adjacent the second electronic substrate and wherein a device side of the third electronic subsfrate is adjacent the second electronic substrate.
30. An electronic device according to Claim 29 wherein both of the first and third electronic substrates are memory devices.
31. An electronic device according to Claim 30 further comprising: a first electrical and mechanical connection between the first and third electronic substrates; and a second electrical and mechanical connection between the second and third electronic substrates, wherein both of the first and second electrical and mechanical connections are electrically coupled to a data input, a data output, and/or an address input of the third elecfronic subsfrate.
32. An electronic device according to Claim 31 wherein the second ■ electronic substrate comprises a memory device.
• 33. An electronic device according to Claim 32 wherein both of the first and second electrical and mechanical connections are electrically coupled to a data input, a data output, and/or an address input of the second electronic substrate, and to a data input, a data output, and/or an address input of the first electronic substrate.
34. An electronic device according to Claim 30 wherein the first and third elecfronic substrates comprise memory devices having a same layout.
35. An electronic device according to Claim 21 wherein a second end of the second electronic substrate extends beyond the first and third electronic substrates.
36. An electronic device according to Claim 35 wherein the first and third electronic substrates comprises integrated circuit device substrates having devices sides facing the printed circuit board and backsides facing away from the printed circuit board, the electronic device further comprising: a first electrical and mechanical connection between the first and third electronic substrates; a second electrical and mechanical connection between the second and third electronic substrates; a third electrical and mechanical connection between the first electronic substrate and the printed circuit board; a fourth electrical and mechanical connection between the second electronic substrate and the printed circuit board; and a fifth elecfrical and mechanical connection between the second electronic subsfrate and the first electronic substrate.
37. An electronic device according to Claim 36 wherein the printed circuit board includes a first conductive pad to which the third electrical and mechanical connection is bonded and a second conductive pad to which the fourth electrical and mechanical connection is bonded, wherein the first conductive pad has a greater surface area than the second conductive pad.
38. An electronic device according to Claim 36 further comprising: a first conductive trace on the printed circuit board providing electrical coupling between the third and fourth electrical and mechanical connections; a second conductive trace on the second electronic substrate providing electrical coupling between the fourth and fifth electrical and mechanical connections; and a third conductive trace on the first electronic substrate providing elecfrical coupling between the fifth and first electrical and mechanical connections.
39. An electronic device according to Claim 38 wherein the first and third electrical and mechanical connections are electrically coupled to a data input, a data output, and/or an address input of the first elecfronic substrate, and wherein the first and third electrical and mechanical connections are electrically coupled to a data input, a data output, and/or an address input of the third electronic substrate.
40. An electronic device according to Claim 35 further comprising: a fourth electronic substrate on the third electronic substrate wherein the third electronic substrate is between the second and fourth electronic substrates; a fifth electronic substrate on the fourth electronic substrate wherein the fourth electronic substrate is between the third and fifth electronic subsfrates, wherein the fourth elecfronic subsfrate is offset relative to the first, third, and fifth electronic substrates so that the second end of the second electronic substrate extends beyond the first, third, and fifth electronic subsfrates, and so that the first, third, and fifth electronic subsfrates extend beyond the fourth electronic substrate.
41. An electronic device according to Claim 21 further comprising: a heat dissipating layer between the first and second elecfronic subsfrates wherein the heat dissipating layer includes a material that is thermally conductive.
42. An electronic device comprising: a first electronic subsfrate having opposing first and second surfaces; a second electronic substrate on the first elecfronic subsfrate, the second electronic substrate having opposing first and second surfaces; a third elecfronic substrate on the second electronic substrate, the third electronic substrate having opposing first and second surfaces, wherein the second elecfronic substrate is between the first and third electronic substrates; and a signal path extending along the first surface of the second electronic substrate, to the second surface of the first electronic subsfrate, along the second surface of the first electronic substrate, to the first surface of the third elecfronic substrate, along the first surface of the third electronic substrate, and to the second surface of the second elecfronic subsfrate.
43. An electronic device according to Claim 42 wherein the signal path comprises a first conductive trace on the first surface of the second elecfronic substrate, a first electrical and mechanical connection between the first surface of the second electronic substrate and the second surface of the. first electronic substrate, a second conductive trace on the second surface of the first electronic substrate, a second electrical and mechanical connection between the second surface of the first electronic substrate and the first surface of the third electronic subsfrate, a third conductive trace of the first surface of the third elecfronic substrate, and a third elecfrical and mechanical connection between the first surface of the third elecfronic substrate and the second surface of the second electronic substrate.
44. An electronic device according to Claim 43 wherein the first, second, and third electrical and mechanical connections comprise respective conductive bumps.
45. An electronic device according to Claim 42 wherein the first and third electronic substrates comprise integrated circuit devices, wherein the first side of the first and third electronic substrates comprises a device side and wherein the second side of the first and third electronic subsfrates comprises a backside.
46. An electronic device according to Claim 45 wherein the signal path is electrically coupled to an electronic circuit of the third electronic substrate.
47. An electronic device according to Claim 45 wherein the second electronic substrate comprises an integrated circuit device, wherein the first side of the second electronic substrate comprises a device side and wherein the second side of the second electronic substrate comprises a backside.
48. An electronic device according to Claim 47 wherein the signal path is electrically coupled to an electronic circuit of the second electronic substrate and to an elecfronic circuit of the third elecfronic substrate.
49. An electronic device according to Claim 47 wherein the first, second, and third electronic subsfrates comprise respective memory devices.
50. An electronic device according to Claim 42 further comprising: a fourth electronic substrate on the third electronic substrate wherein the third electronic substrate is between the second and fourth electronic subsfrates; and wherein the signal path further extends along the second surface of the second electronic substrate, and to a first surface of the fourth electronic substrate.
51. An electronic device according to Claim 50 wherein the signal path is elecfrically coupled with electronic circuits of the second and fourth substrates.
52. An elecfronic device according to Claim 50 wherein the signal path is electrically coupled with an electronic circuit of the fourth electronic substrate, and wherein the signal path is free of electrical coupling with an electronic circuit of the second elecfronic substrate.
53. An elecfronic device according to Claim 42 further comprising: a heat dissipating layer between the first and second electronic substrates, the heat dissipating layer comprising a material that is thermally conductive.
54. An electronic device comprising: a substrate having opposing first and second surfaces; a first array of interconnection structures on the first surface of the substrate wherein the first array of interconnection structures are arranged in a first pattern; a second array of interconnection structures on the second surface of the substrate wherein the second array of interconnection structures are arranged in a second pattern and wherein the second pattern is a mirror image of the first pattern.
55. An elecfronic device according to Claim 54 wherein the first array of interconnection structures comprises an array of interconnection bumps and wherein the second array of interconnection structures comprises an array of conductive pads free of interconnection bumps.
56. An electronic device according to Claim 55 wherein the interconnection bumps comprise solder bumps and wherein the conductive pads comprise solder wettable pads.
57. An electronic device according to Claim 54 further comprising: a third array of interconnection structures on the first surface of the subsfrate spaced apart from the first array of interconnection structures wherein the third array of interconnection structures are arranged in a third pattern; a fourth array of interconnection structures on the second surface of the substrate spaced apart from the second array of interconnection structures wherein the fourth array of interconnection structures are arranged in a fourth pattern, wherein the fourth pattern is a mirror image of the third pattern.
58. An electronic device according to Claim 57 further comprising: a first plurality of conductive traces on the first surface of the substrate wherein the first plurality of conductive traces provide interconnection between at least some of the interconnection structures of the first and second arrays on a one to one basis.
59. An electronic device according to Claim 54 wherein the substrate comprises an integrated circuit subsfrate such that the first surface is a device side of the substrate having electronic circuits thereon and the second surface is a backside of the subsfrate.
60. An electronic device according to Claim 59 wherein the integrated circuit device comprises an integrated circuit memory device.
61. An electronic device comprising: a first integrated circuit subsfrate; a second integrated circuit subsfrate mounted on the first integrated circuit substrate; a third integrated circuit substrate mounted on the second integrated circuit subsfrate such that the second integrated circuit substrate is between the first and second integrated circuit substrates; at least one large bump providing electrical and mechanical connection between the first and third integrated circuit substrates; and at least one small bump providing elecfrical and mechanical connection between the second and third integrated circuit substrates wherein the at least one large bump has a greater volume than the at least one small bump.
PCT/US2003/033211 2002-10-22 2003-10-21 Stacked electronic structures including offset substrates WO2004038798A2 (en)

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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4110992B2 (en) * 2003-02-07 2008-07-02 セイコーエプソン株式会社 Semiconductor device, electronic device, electronic apparatus, semiconductor device manufacturing method, and electronic device manufacturing method
EP1471778A1 (en) * 2003-04-24 2004-10-27 Infineon Technologies AG Memory module having space-saving arrangement of memory chips and memory chip therefor
TW200511531A (en) * 2003-09-08 2005-03-16 Advanced Semiconductor Eng Package stack module
KR100832845B1 (en) * 2006-10-03 2008-05-28 삼성전자주식회사 Semiconductor Package Structure And Method Of Fabricating The Same
US7691668B2 (en) * 2006-12-19 2010-04-06 Spansion Llc Method and apparatus for multi-chip packaging
KR100874926B1 (en) * 2007-06-07 2008-12-19 삼성전자주식회사 Stack modules, cards containing them and systems containing them
KR100876889B1 (en) * 2007-06-26 2009-01-07 주식회사 하이닉스반도체 Semiconductor package, and multi-chip semiconductor package using the semiconductor package
JP2009054970A (en) * 2007-08-29 2009-03-12 Shinko Electric Ind Co Ltd Semiconductor device
US8399973B2 (en) * 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
US8110440B2 (en) 2009-05-18 2012-02-07 Stats Chippac, Ltd. Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
US8476749B2 (en) * 2009-07-22 2013-07-02 Oracle America, Inc. High-bandwidth ramp-stack chip package
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8338963B2 (en) 2011-04-21 2012-12-25 Tessera, Inc. Multiple die face-down stacking for two or more die
US8304881B1 (en) 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
KR101774938B1 (en) 2011-08-31 2017-09-06 삼성전자 주식회사 Semiconductor package having supporting plate and method of forming the same
US9082632B2 (en) 2012-05-10 2015-07-14 Oracle International Corporation Ramp-stack chip package with variable chip spacing
WO2014066153A1 (en) * 2012-10-23 2014-05-01 Tessera, Inc. Multiple die stacking for two or more die
US8933540B2 (en) 2013-02-28 2015-01-13 International Business Machines Corporation Thermal via for 3D integrated circuits structures
TWI608564B (en) * 2013-12-10 2017-12-11 艾馬克科技公司 Semiconductor device
US9559040B2 (en) 2013-12-30 2017-01-31 International Business Machines Corporation Double-sided segmented line architecture in 3D integration
KR102307490B1 (en) * 2014-10-27 2021-10-05 삼성전자주식회사 Semiconductor package
US10297541B2 (en) * 2016-11-18 2019-05-21 Intel Corporation Multiple-component substrate for a microelectronic device
US10741532B2 (en) 2018-03-12 2020-08-11 International Business Machines Corporation Multi-chip modules

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892230A (en) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp Semiconductor device
US20020005577A1 (en) * 2000-07-14 2002-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6388333B1 (en) * 1999-11-30 2002-05-14 Fujitsu Limited Semiconductor device having protruding electrodes higher than a sealed portion
EP1248295A2 (en) * 2001-04-06 2002-10-09 Shinko Electric Industries Co. Ltd. Semiconductor element, connection structure thereof, semiconductor device using a plurality of such elements and processes for making the same

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3105869A (en) 1962-03-23 1963-10-01 Hughes Aircraft Co Electrical connection of microminiature circuit wafers
DE1614928A1 (en) 1966-07-19 1970-12-23 Solitron Devices Method for contacting semiconductor components
NL159822B (en) 1969-01-02 1979-03-15 Philips Nv SEMICONDUCTOR DEVICE.
US3871014A (en) 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform solder wettable areas on the substrate
US3663184A (en) 1970-01-23 1972-05-16 Fairchild Camera Instr Co Solder bump metallization system using a titanium-nickel barrier layer
DE2044494B2 (en) 1970-09-08 1972-01-13 Siemens AG, 1000 Berlin u 8000 München CONNECTING AREAS FOR SOLDERING SEMI-CONDUCTOR COMPONENTS IN FLIP CHIP TECHNOLOGY
US3760238A (en) 1972-02-28 1973-09-18 Microsystems Int Ltd Fabrication of beam leads
US4113578A (en) 1973-05-31 1978-09-12 Honeywell Inc. Microcircuit device metallization
US3897871A (en) 1973-07-26 1975-08-05 Lilly Co Eli Print album storage case insert
US4074342A (en) 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
JPS55111127A (en) 1979-02-19 1980-08-27 Fuji Electric Co Ltd Method for forming solder bump
JPS5773952A (en) 1980-10-27 1982-05-08 Hitachi Ltd Chip for face down bonding and production thereof
US4473263A (en) 1981-01-21 1984-09-25 Sunstein Drew E Circuit board mounting device and associated components
US4382517A (en) 1981-02-20 1983-05-10 Metropolitan Wire Corporation Panels for holding printed circuit boards
JPS57197838A (en) 1981-05-29 1982-12-04 Oki Electric Ind Co Ltd Semiconductor flip chip element
JPS59154041A (en) 1983-02-22 1984-09-03 Fuji Electric Corp Res & Dev Ltd Formation of electrode of semiconductor device
US4532576A (en) 1983-08-29 1985-07-30 Gte Automatic Electric Incorporated Printed wiring board file and method of utilizing the same
JPS6116552A (en) 1985-06-21 1986-01-24 Hitachi Ltd Integrated circuit device
US4657146A (en) 1985-11-06 1987-04-14 Richard Walters Adjustable printed circuit board rack for supporting printed circuit boards in a horizontal or a vertical position
JPS63222245A (en) 1987-03-11 1988-09-16 Shokuhin Sangyo Onrain Sensor Gijutsu Kenkyu Kumiai Defect inspector for mouth of bottle
JPH0793304B2 (en) 1987-03-11 1995-10-09 富士通株式会社 Method of forming bump electrode
JPS6461934A (en) 1987-09-02 1989-03-08 Nippon Denso Co Semiconductor device and manufacture thereof
US4855809A (en) 1987-11-24 1989-08-08 Texas Instruments Incorporated Orthogonal chip mount system module and method
WO1989008926A1 (en) 1988-03-16 1989-09-21 Plessey Overseas Limited Vernier structure for flip chip bonded devices
US4950623A (en) 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US4962058A (en) 1989-04-14 1990-10-09 International Business Machines Corporation Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit
FR2663784B1 (en) 1990-06-26 1997-01-31 Commissariat Energie Atomique PROCESS FOR PRODUCING A STAGE OF AN INTEGRATED CIRCUIT.
JPH04150033A (en) 1990-10-12 1992-05-22 Sharp Corp Bump on electronic circuit board; formation method of bump on electronic circuit board and of circuit pattern
US5113314A (en) 1991-01-24 1992-05-12 Hewlett-Packard Company High-speed, high-density chip mounting
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
FR2678773B1 (en) 1991-07-05 1997-03-14 Thomson Csf WIRING PROCESS BETWEEN HOUSING OUTLETS AND HYBRID ELEMENTS.
US5160409A (en) 1991-08-05 1992-11-03 Motorola, Inc. Solder plate reflow method for forming a solder bump on a circuit trace intersection
US5194137A (en) 1991-08-05 1993-03-16 Motorola Inc. Solder plate reflow method for forming solder-bumped terminals
CA2050174A1 (en) 1991-08-28 1993-03-01 Dwight Chizen Storage rack for cassettes and compact discs
US5162257A (en) 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method
US5239447A (en) 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
JP2575566B2 (en) 1992-01-24 1997-01-29 株式会社東芝 Semiconductor device
FR2688628A1 (en) 1992-03-13 1993-09-17 Commissariat Energie Atomique Three-dimensional assembly of electronic components using microwires and blobs of solder, and method of producing this assembly
US5289925A (en) 1992-03-16 1994-03-01 Martin Newmark Organizational display for compact disc jewel boxes
US5281684A (en) 1992-04-30 1994-01-25 Motorola, Inc. Solder bumping of integrated circuit die
US5646439A (en) 1992-05-13 1997-07-08 Matsushita Electric Industrial Co., Ltd. Electronic chip component with passivation film and organic protective film
DE69330630T2 (en) 1992-05-15 2002-06-13 Irvine Sensors Corp NON-CONDUCTIVE EDGE LAYER FOR INTEGRATED STACK OF IC CHIPS
US5406701A (en) 1992-10-02 1995-04-18 Irvine Sensors Corporation Fabrication of dense parallel solder bump connections
US5739053A (en) 1992-10-27 1998-04-14 Matsushita Electric Industrial Co., Ltd. Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step
US5327327A (en) 1992-10-30 1994-07-05 Texas Instruments Incorporated Three dimensional assembly of integrated circuit chips
US5347428A (en) 1992-12-03 1994-09-13 Irvine Sensors Corporation Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
KR940023325A (en) 1993-03-11 1994-10-22 토모마쯔 켕고 Circuit boards used by precoating the solder layer and circuit boards precoated with the solder layer
DE69426695T2 (en) 1993-04-23 2001-08-09 Irvine Sensors Corp ELECTRONIC MODULE WITH A STACK OF IC CHIPS
US5886412A (en) * 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5680296A (en) 1995-11-07 1997-10-21 Sun Microsystems, Inc. Card guide with groove having a base portion and ramped portion which restrains an electronic card
US5751556A (en) 1996-03-29 1998-05-12 Intel Corporation Method and apparatus for reducing warpage of an assembly substrate
US5793116A (en) 1996-05-29 1998-08-11 Mcnc Microelectronic packaging using arched solder columns
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits
US6082610A (en) * 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6297548B1 (en) * 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
JP3360655B2 (en) * 1999-07-08 2002-12-24 日本電気株式会社 Semiconductor device
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6731009B1 (en) * 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6627980B2 (en) * 2001-04-12 2003-09-30 Formfactor, Inc. Stacked semiconductor device assembly with microelectronic spring contacts
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892230A (en) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp Semiconductor device
US6388333B1 (en) * 1999-11-30 2002-05-14 Fujitsu Limited Semiconductor device having protruding electrodes higher than a sealed portion
US20020005577A1 (en) * 2000-07-14 2002-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
EP1248295A2 (en) * 2001-04-06 2002-10-09 Shinko Electric Industries Co. Ltd. Semiconductor element, connection structure thereof, semiconductor device using a plurality of such elements and processes for making the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0071, no. 90 (E-194), 19 August 1983 (1983-08-19) -& JP 58 092230 A (MITSUBISHI DENKI KK), 1 June 1983 (1983-06-01) *

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