WO2004040866A2 - Method for optimizing a link schedule - Google Patents
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- WO2004040866A2 WO2004040866A2 PCT/US2003/033577 US0333577W WO2004040866A2 WO 2004040866 A2 WO2004040866 A2 WO 2004040866A2 US 0333577 W US0333577 W US 0333577W WO 2004040866 A2 WO2004040866 A2 WO 2004040866A2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/28—Flow control; Congestion control in relation to timing considerations
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- A—HUMAN NECESSITIES
- A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
- A01K—ANIMAL HUSBANDRY; CARE OF BIRDS, FISHES, INSECTS; FISHING; REARING OR BREEDING ANIMALS, NOT OTHERWISE PROVIDED FOR; NEW BREEDS OF ANIMALS
- A01K15/00—Devices for taming animals, e.g. nose-rings or hobbles; Devices for overturning animals in general; Training or exercising equipment; Covering boxes
- A01K15/02—Training or exercising equipment, e.g. mazes or labyrinths for animals ; Electric shock devices ; Toys specially adapted for animals
- A01K15/025—Toys specially adapted for animals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
- H04L47/2475—Traffic characterised by specific attributes, e.g. priority or QoS for supporting traffic characterised by the type of applications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/28—Flow control; Congestion control in relation to timing considerations
- H04L47/283—Flow control; Congestion control in relation to timing considerations in response to processing delays, e.g. caused by jitter or round trip time [RTT]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/4026—Bus for use in automation systems
Definitions
- the invention relates generally to communications networks and more particularly to communications networks that operate on a periodically executed schedule.
- FOUNDATIONTM FIELDBUS technology is an open technology provided by the FIELDBUS Foundation of Austin, Texas, USA. It is a local area network type of communications BUS based on the International Electro-Technical Commission 61158 FIELDBUS standard. That standard calls for some of the periodic communications on the BUS to be scheduled within a periodically executed schedule.
- Foundation FIELDBUS technology permits interactive communication among devices, scheduling is restricted to some degree. For instance, only one function block in a single application processor device may execute at a time. Further, only one device may publish (that is, a publication or back- calculation publication) on the link at a time, and client-server activity may only take place between publications.
- Function blocks are typically scheduled in "natural order", from input to output, following primary connections. Particularly when many devices are sharing a link, "natural order” scheduling tends to produce a large number of relatively “short” publication gaps. These “short” gaps often reflect wasted bandwidth because large queued communications, and all communications queued behind them, are delayed until a large enough gap arises in the schedule. For example, display call-ups and operator station display call— ups are often most severely affected since they typically require relatively large gaps to satisfy their heavy information transfer demands. Accordingly, the number of client-server messages transmitted per macrocycle is limited, and less than optimum application performance is achieved.
- Such a method should allow for greater communications usage from a fixed bandwidth; shorten the overall scheduled portion of the link schedule; and, minimize loop latencies to achieve better control.
- a mixed scheduled/unscheduled network schedule including a FIELDBUS and, particularly, a Foundation FIELDBUS.
- the present invention therefore, provides a method of creating a schedule for a network that communicates in accordance to a periodically executed schedule, which includes the steps of first identifying a plurality of function blocks requiring execution and then identifying each of the function blocks as members of one or more groups. Next, the groups are prioritized such that each group has a priority relative to the other group, and then each of the groups containing at least one unscheduled function block is scheduled, one group at a time, in an order based on the priority of each group for communication on the network.
- the present invention reduces the scheduled portion of the link schedule (that is, for example, as compared with "natural scheduling"). Consequently, more activities can be accommodated and the macrocyle may be shortened.
- publications are also grouped in order to eliminate potential publication gaps. Alternatively, since larger gaps have a greater potential of permitting longer unscheduled messages to be issued, a publication may be positioned between two other publications so that the two publication gaps formed provide a very large and a very small gap. For instance, since back-calculation publications do not have critical timing requirements, they can often be scheduled to execute immediately before or after back-calculation publications and non-back-calculation publications. In this way, less bandwidth is wasted and application performance is increased.
- FIG. 1 is a block diagram associated with Example 1.
- FIG. 2 is a timing diagram associated with the natural schedule of Example 1.
- FIG. 3 is a timing diagram associated with the optimized schedule of Example 1.
- FIG. 4 is a block diagram associated with Example 2.
- FIG. 5 is a timing diagram associated with the natural schedule of Example 2.
- FIG. 6 is a timing diagram associated with the optimized schedule of Example 2.
- FIG. 7 is a block diagram associated with Example 3.
- FIG. 8 is a timing diagram associated with the natural schedule of Example 3.
- FIG. 9 is a timing diagram associated with the optimized schedule of Example 3. '
- FIG. 10 is a block diagram associated with Example 4.
- FIG. 11 is a timing diagram associated with the natural schedule of Example 4.
- FIG. 12 is a timing diagram associated with the optimized schedule of Example 4. DETAILED DESCRIPTION OF THE INVENTION
- Loop Latency The time that elapses between the input function block's process sampling until the control element is commanded to correct a deviation by the output function block.
- Critical Loop Latency The time that elapses in the highest priority loop between the input function block's process sampling until the control element is commanded to correct a deviation by the output function block.
- Latency Factor Ratio of "optimized” Critical Loop Latencies to "natural” Critical Loop Latencies.
- Latency Improvement 100% minus the Latency Factor, expressed as a percentage.
- Publication a message, often scheduled, made available on a network to one or more nodes at the same time.
- Non-Back-Calculation Publication a publication that is not associated with back-calculation information.
- Back-Calculation Publication a publication which is associated with back- calculation information, usually used on a subsequent execution cycle by a previously executed block to initialize, prevent reset windup, and provide status information.
- Publication Gap Time between the end of one publication and the start of the next scheduled publication.
- Extra Time Associated With Any Communication (or "Associated Time”): An estimate average length of time lost with any message. This may include, for example, the time attributed to access delays, average time lost due to a next-queued message that exceeds available time, conflicts with "housekeeping" activities such as passing tokens, probing nodes, distributing time, etc. It is assumed that the Associated Time is 15 ms in the examples in this document.
- Usable Publication Gap (or Usable Gap): The portion of the publication gap available for messages other than publications or back-calculation publications.
- the Usable Gap is calculated by subtracting the "Associated Time” from the "Publication Gap".
- Minimum Time Needed For Unscheduled Communication (or “Minimum Time”): The minimum length of time that unscheduled communication on the link, including client server interaction, requires in order to fully execute. It is assumed that the Minimum Time Needed For Any Communication is greater than 30 ms for the examples in this document.
- Publication Gap Factor Ratio of the usable gaps of the natural macrocycle to the usable gaps of the optimized macrocycle.
- Macrocycle Utilization Factor Ratio of the of the optimized macrocycle time to the natural macrocycle time, expressed as a percentage.
- Macrocycle Improvement 100% minus the Macrocycle Utilization Factor, expressed as a percentage.
- Natural Macrocycle The macrocycle created by arranging function block executions in the order of input to output, following primary connections, with each publication occurring immediately after execution of the function block that calculates it.
- Function Block An object that has inputs and/or outputs that may be interconnected to or from other function blocks and executes an algorithm on its inputs to produce its outputs.
- Input Function Block (or Input Class Function Block): A function block that usually originates with a value derived from a process (e.g., Al, DI, PI). The term "usually” is employed because in most cases, the input block is at the beginning of the string of blocks. There are, however, obscure cases that someone skilled in the art would recognize.
- Output Function Block (or Output Class Function Block): A function block that usually terminates with a value provided to a process (e.g., AO, DO, CAO, CDO).
- a value provided to a process (e.g., AO, DO, CAO, CDO).
- the term "usually” is employed because in most cases, the output block is at the end of the string of blocks. However, it is possible to take the output value and connect it to another block to do auxiliary calculations or even to loop it back as a simulated plant value for demonstration or test purposes. These are obscure uses that someone skilled in the art would recognize.
- Control Function Block A function block whose primary function is to compare a process-influenced value to a setpoint, or target value, and provide one or more outputs that are somehow directed to control the process to the setpoint, or target value, usually through an output function block.
- Sequence in this document is defined as a series of function blocks wherein the term sequence is defined as:
- Control Loop Sequence A Sequence of Function Blocks that starts with an input block and ends with an output block.
- Monitoring Sequence A sequence of one or more Function Blocks that starts with an input block and does not contain a control block or an output block. Accordingly, a "Monitoring Sequence” is any sequence that is not a Control Loop Sequence or a Cascade Loop Sequence.
- Primary Connection Input A "Primary Input", “Process Variable”, or “Cascade Input” as defined by the formal models of the FOUNDATION FIELDBUS Function Block Application Process Specifications and as designated by the authors of each type of block or as otherwise designated by a user for a particular application.
- Primary Connection Output A "Primary Output" as defined by the formal models of the FOUNDATION FIELDBUS Function Block Application Process Specifications and as designated by the authors of each type of block or as otherwise designated by a user for a particular application. For example, OUT, OUT_D, etc.
- Primary Connection A reference by a "Primary Connection Input” to a “Primary Connection Output”, as defined by the formal models of the FOUNDATION FIELDBUS Function Block Application Process Specifications or as otherwise designated by a user for a particular application.
- Cascade Loop Sequence A Sequence of Function Blocks that starts with an input block and ends with a control function block, the control function block in turn providing an output (directly or indirectly) to a block in a downstream control loop sequence.
- Setpoint (or Control Target): The value that a downstream, or inner, control block uses as a target for the primary process variable it also receives.
- An upstream, or outer, cascade loop sequence's control function block provides a setpoint to a downstream, or inner, cascade loop sequence's control function block.
- Downstream refers to a function block or sequence of function blocks whose input is provided by an output of the referenced function block.
- Upstream refers to a function block or sequence of function blocks whose output is provided to an input of a referencing function block.
- Inner Control Loop A control loop sequence or cascade loop sequence that is provided a setpoint (control target) by another sequence. Inner control loops are downstream relative to outer control loops.
- Outer Control Loop A control loop sequence or cascade loop sequence that provides a setpoint (control target) to another sequence. Outer control loops are upstream relative to inner control loops.
- Sample-Skew A time difference between the sampling times of set of multiple inputs (or samples). When a group of input function blocks are used together, as in a calculation involving each (e.g., average of several sampling locations or mass flow involving temperature, pressure, and differential pressure) or as in a comparison (minimum, maximum, median) of several sampling locations, the times of each of the samplings relative to each other may or may not be important to the application. "Sample-Skew" indicates that relative times of each sampling are not important to the application.
- No-Sample-Skew No time difference between the sampling times of set of multiple inputs (or samples).
- a group of input function blocks are used together, as in a calculation involving each (e.g., average of several sampling locations or mass flow involving temperature, pressure, and differential pressure) or as in a comparison (minimum, maximum, median) of several sampling locations, the times of each of the samplings relative to each other may or may not be important to the application.
- “No-Sample-Skew” indicates that relative times of each sampling are important to the application.
- sequences, or other groups of function blocks may be identified in numerous, less preferable ways that will be apparent to one skilled in the art. Moreover, each individual block could be considered a separate group in alternative embodiments.
- each sequence preferably one sequence at a time, by starting at each input class function block and following each primary connection from the input class function block's primary connection output to the output's use by a subsequent "referencing" block (through the "referencing" block's primary connection input, such as IN, IN_D, PV, PV_D, CASJN, CAS_IN_D, SEL_n, etc.). If there is no reference to a primary connection output, consider the single block-whether it is an input class function block, a block via Section 1.4, etc.-a sequence.
- referencing block has already been included in this sequence, do not include the referencing block, as it would form an unwanted circular reference. 1.1.2 If the referencing block's input connection is a cascade setpoint connection of a control block, other than a Control Selector block or an Output Splitter block (or the like), terminate the sequence without including the referencing block because it will be included in another control loop sequence.
- the "old referencing” block is the input class function block.
- the "new referencing” block essentially becomes the "old referencing” block.
- a manually-controlled output class block or function block sequence used for a specialized purpose could have a sequence starting with a non-input-class block.
- Section 1.5 is primarily, but not exclusively, intended to address circular function block references.
- sequences are prioritized.
- the sequences are prioritized according to both period type and period length.
- Control Loop Sequences and Cascade Loop Sequences are higher priority than Monitoring Sequences.
- Control Loop Sequences have higher priority than Cascade Loop Sequences. This is because the Control Sequences are in direct control, whereas the Cascade Sequences control indirectly by providing a setpoint to a downstream Control Loop Sequence or another Cascade Loop Sequence.
- sequences are scheduled by assigning block executions and publications to the link schedule, based on priorities as set forth below.
- the schedule is preferably normalized after the sequences are scheduled, but alternative embodiments may perform normalizing at other times.
- the macrocycle length (i.e., the time duration) is determined before scheduling.
- the length is preferably the least common multiple of contributing function block's periods. However, this may be performed at other times, and such options will readily be known to those skilled in the art.
- publication and block executions are preferably scheduled to minimize delays between:
- 3.2(C) A function block execution that produces an output that does not require a publication and a function block execution that directly inputs such output.
- 3.2(D) An execution of a publication-producing block, and the publication produced by that publication-producing block.
- the first (i.e., highest priority) function block sequence is scheduled first at relative time "zero" in the macrocycle.
- other options will be known to those skilled in the art.
- provisos 3.2(A) and 3.2(B) operate such that the "to be scheduled" element is retreated appropriately to minimize the delay between the elements in conflict. That is:
- Reverse order scheduling involves first scheduling the start of the execution of the function block, or publication, in the "to be scheduled” sequence as close as possible to the element already in the schedule that requires it. (Accordingly, reverse order scheduling is to a large degree the opposite of forward order scheduling, as described in Section 3.2.3.1.) That is, the end of the execution of the "to be scheduled” function block is scheduled as close as possible to the beginning of the element that requires it. It should thus be evident that this scheduling requires the start of these "to be scheduled” elements be defined such that the time duration of each element is considered.
- a function block sequence that directly utilizes an output of a previously assigned function block within the link schedule, or directly utilizes a publication, is scheduled in forward order (as set forth in 3.2.3.1.), one at a time, with minimal delay, from that need. Further, the scheduling should proceed from the beginning to end of the "to be scheduled" function block sequence with preferably minimal delays.
- provisos 3.2(A) and 3.2(B) operate such that:
- 3.2.3(B) Since the schedule time of any two publications may not overlap, the publication is scheduled as soon as possible after this conflict. Thus, 3.2.3(A) and 3.2.3(B) operate such that the "to be scheduled" element is advanced appropriately to minimize the delay between the elements in conflict.
- Forward order scheduling involves first scheduling the start of the execution of the first function block in the "to be scheduled” sequence as close as possible to the block (or publication) that provides the required output (or publication).
- a function block sequence that does not directly utilize an output of a function block that is already assigned to the link schedule (or directly utilize a publication) and does not provide an output connection (or produce a publication) that is received by a previously scheduled function block, is considered independent for latency purposes. Therefore, it is assigned to the link schedule-with minimal delays between any of the sequence's elements- as close to the beginning of the macrocycle as possible.
- any portion of the "to be scheduled” sequence is preferably adjusted within the macrocycle so as to minimize delay between the elements of the "to be scheduled” sequence.
- another-but less-preferable-option compared to minimizing latency would be to arrange the new sequence such that as many of the new publication(s) are placed immediately adjacent to (either before or after) another already-assigned publication. In this way, one or more publication gaps may be eliminated. This should most preferably be performed according to 3.3.
- each back-calculation publication is scheduled. Each of these may be scheduled to occur at any time after its availability and before its usage (usually within the next execution cycle). Publication gaps meeting this criterion are qualifying publication gaps.
- the optimization objective is to arrange, if possible, for the back-calculation publication to be immediately adjacent to (either before or after) another already-assigned publication (that is, of either sort) so as to minimize a "potential publication gap" (as defined in the context of Section 3.3).
- the publication should preferably be placed adjacent to another previously- scheduled publication so as to minimize (i.e., eliminate completely) one of the two "potential publication gaps" inherent in this situation. If the publication cannot be placed adjacent to a previously-scheduled publication, it should be placed so that the larger of the two “potential publication gaps” is maximized. That is, if publication adjacency not possible, it is better to position it such that the two "potential publication gaps" created by its presence are as different in size as possible (i.e., one large and one small).
- the back-calculation publication should be placed in the smallest publication gap to leave the larger publication gap unbroken for longer messages.
- the larger of the two “potential publication gaps” inherent in the smaller "not perfectly sized publication gap” is maximized.
- the underlying rationale is that a large “potential publication gap” has a greater potential of usage than two smaller ones since unscheduled messages vary in length, and longer messages can block other messages that are waiting in a queue to be transmitted over the network.
- step 3.3 the scheduling of back-publications according to step 3.3 can be performed in conjunction with other scheduling algorithms.
- the natural link schedule set forth below, and reflected in FIG. 2, indicates that the blocks of the first loop are executed first, in natural sequence.
- the optimized link schedule is set forth below and is reflected in FIG. 3.
- the second sequence is assigned via 3.2.4 to the link at the beginning of the macrocycle. It then is adjusted via 3.2.4.1 to minimize the delay between the elements. In this way, and as reflected below and in FIG. 3, the entire scheduled portion of the macrocycle is shortened significantly. (The time offsets are in milliseconds.)
- Example 2 Two Simple Loops, Control in Transmitter Although the functionality is identical to the previous example (two simple control loops), the link scheduling differs. When simple loop control is coresident with the transmitter, there are two publications: one, the output from the controller to the actuator, and a second, the back-calculation parameter from the actuator back to the controller. As indicated in FIG. 4, these occur for each of the two loops.
- the natural link schedule executes the blocks of the first loop first with the publication of the PIDI's output done as soon as the value is calculated, and the back-calculation of the actuator published as soon as it is available.
- the second loop sequences identically, but does not start until the first loop completes its execution in its entirety, including the back-calculation.
- the back-calculation publications are adjacent to one another. Accordingly, the original publication gap that they severed cannot be made any more unequal given that the back-calculation publications cannot be issued earlier than the completion of their respective PID function block executions; and issuing them just before their respective requiring PID function block executions in the next cycle would form less unequal publication gaps.
- an input-selector block chooses one- -or the average of some or all of the inputs— depending on the goals of the configuration.
- FIG. 7 sets forth an example using a triple signal selector.
- the natural link schedule executes the first Al block that immediately publishes its output. Then, the second Al block is executed, publishing its output immediately. Next, the third Al block is executed, publishing its output immediately. Finally, the Input-Selector block executes, followed by the PID and AO blocks.
- FIG. 10 sets forth an example of a typical application.
- the natural link schedule executes the first Al function block and its controller and then follows the path of connections within each device, beginning with Al function block, towards the AO function block. It also includes the execution of the integrator function block in its natural diagrammatic location.
- Sequences of input-to-output blocks are control loop sequences
- Sequences of input-to-control blocks are cascade loop sequences
- Sequences of input alone or input-to-other blocks are monitoring sequences
- the optimized link schedule is created using the sequence chart above and the steps described below.
- the optimized link schedule set forth below, and reflected in FIG. 12, is created as follows:
- Sequence ID #1 is scheduled first since it is the highest priority unscheduled sequence. It is the highest priority in light of its speed (.5 seconds) and its type (control).
- Sequence ID #5 was chosen as the second sequence since it possessed the "smallest" (fastest) period of the remaining non-monitoring type sequences (i.e., sequences 3, 5, and 6) and is a "cascade" sequence.
- the output of the sequence's blocks (AI2-PID2) is needed by PID3 exec, just prior to execution, so PID2 PUB is scheduled in reverse order from that need.
- Sequences ID #3 and #6 are both involved in control and unassigned portions execute at a 2-second period. Sequence ID #3 takes precedence, however, since it is a control sequence and ID #6 is a cascade sequence. Since the output of the sequence is used by the Arithmetic block, it is scheduled in reverse from that need. However, since AI3 publishes its output immediately prior to the execution of the Arithmetic block, AI4's publication is retreated so that it completes just prior to the start of AI3's publication.
- sequence #6 The only remaining sequence involved in control is identified to be sequence #6. This cascade sequence ends with PIDI's publication, which is needed by the previously scheduled PID2 block. Hence, PID1 PUB is scheduled to complete immediately before the execution of PID2. Further, PID1 is scheduled so as to complete just before the publication is scheduled; and the AH block is scheduled to execute completely just before the PID1 block executes.
- the monitoring sequences with unscheduled blocks are next scheduled (i.e., sequences #2 and #4). Since AI3, AI4, and the Arithmetic block have already been scheduled, the Integrator block is the only remaining unscheduled block in both of these sequences. Accordingly, either may be selected for scheduling next.
- the Integrator's input is dependent on the execution of the Arithmetic block, it is scheduled to execute as soon as possible after the Arithmetic block has completed execution.
- the Integrator since the Integrator resides in the same single-application processor as PID3 and AO, which have been previously scheduled in accordance with their higher priority, the Integrator cannot be scheduled until immediately after the AO completes its execution.
- PID3 is the innermost of the cascaded control blocks so it is higher priority, with PID2 next. (PID1 need not publish its back-calculation output because there are no blocks that require it.)
- PID3 BK is available for publication when PID3 completes its execution and its publication must be completed by the time PID2 starts its execution. Accordingly, it can be scheduled after PID3 completes until the end of the macrocycle or from the start of the macrocycle up to the time that PID2 starts execution (less its publication duration time).
- PIDI's publication Since it cannot be published after that (i.e., it is too late), it is scheduled just prior to PID1 PUB. Accordingly, this adjacency eliminates a "potential publication gap" in accordance with Section 3.3.
- PID2 BK is available for publication when PID2 completes its execution and its publication must be completed by the time PID1 , its user, starts its execution. It can be scheduled from PID2's completion until the end of the macrocycle, or between the start of the macrocycle and the time that PID1 starts its execution (less the publication duration time). There is only one other publication already scheduled within those bounds, and that is PID2's publication. Since it cannot be published before PID2's publication (i.e., it is not ready yet), it is scheduled just after PID2's publication in order to eliminate a "potential publication gap" in accordance with Section 3.3.
- the present invention has been described herein primarily as a method for optimising a Foundation FIELDBUS link schedule. However, it will be appreciated by those skilled in the art that the invention is not limited to this particular field of use and can be applicable and used to advantage in any communication network that operates on a periodically-executed schedule.
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AU2003282997A AU2003282997B2 (en) | 2002-10-29 | 2003-10-22 | Method for optimizing a link schedule |
JP2004548427A JP2006505189A (en) | 2002-10-29 | 2003-10-22 | How to optimize the link schedule |
EP03774930A EP1566021A2 (en) | 2002-10-29 | 2003-10-22 | Method for optimizing a link schedule |
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US10/283,766 US7363380B2 (en) | 2002-10-29 | 2002-10-29 | Method for optimizing a link schedule |
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AU2003282997B2 (en) | 2008-03-06 |
EP1566021A2 (en) | 2005-08-24 |
US20080229317A1 (en) | 2008-09-18 |
US20040081162A1 (en) | 2004-04-29 |
CN1729653A (en) | 2006-02-01 |
US7363380B2 (en) | 2008-04-22 |
WO2004040866A3 (en) | 2004-08-05 |
JP2006505189A (en) | 2006-02-09 |
US7945682B2 (en) | 2011-05-17 |
AU2003282997A1 (en) | 2004-05-25 |
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