WO2004045162A2 - Traffic management architecture - Google Patents
Traffic management architecture Download PDFInfo
- Publication number
- WO2004045162A2 WO2004045162A2 PCT/GB2003/004893 GB0304893W WO2004045162A2 WO 2004045162 A2 WO2004045162 A2 WO 2004045162A2 GB 0304893 W GB0304893 W GB 0304893W WO 2004045162 A2 WO2004045162 A2 WO 2004045162A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- processor
- packets
- packet
- sorting
- queue
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/466—Transaction processing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
- H04L47/2441—Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/56—Queue scheduling implementing delay-aware scheduling
- H04L47/562—Attaching a time tag to queues
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/60—Queue scheduling implementing hierarchical scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/6215—Individual queue per QOS, rate or priority
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/624—Altering the ordering of packets in an individual queue
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload
Definitions
- a router's switch fabric can deliver packets from multiple ingress ports to one of a number of egress ports. The linecard connected to this egress port must then transmit these packets over some communication medium to the next router in the network.
- the rate of transmission is normally limited to a standard rate.
- an OC-768 link would transmit packets over an optical fibre at a rate of 40 Gbits/s.
- the time-averaged rate of delivery cannot exceed 40 Gbits/s for this example.
- the short term delivery of traffic by the fabric is "bursty" in nature with rates often peaking above the 40 Gbits/s threshold. Since the rate of receipt can be greater than the rate of transmission, short term packet queueing is required at egress to prevent packet loss.
- a simple FIFO queue is adequate for this purpose for routers which provide a flat grade of service to all packets. However, more complex schemes are required in routers which provide Traffic Management.
- Email can be carried on a best effort service where no guarantees are made regarding rate of or delay in delivery.
- Real-time voice data has a much more demanding requirement for reserved transmission bandwidth and guaranteed minimum delay in delivery. This cannot be achieved if all traffic is buffered in the same FLFO queue.
- a queue per so-called "Class of Service” is required so that traffic routed through higher priority queues can bypass that in lower priority queues. Certain queues may also be assured a guaranteed portion of the available output line bandwidth.
- Packets are placed in queues according to their required class of service. For every forwarding treatment that a system provides, a queue must be implemented. These queues are then managed by the following mechanisms:
- Scheduling controls the de-queuing process by dividing the available output line bandwidth between the queues.
- WFQ Weighted Fair Queueing
- DRR Deficit Round Robin
- WRED Weighted Random Early Detect
- Priority queue ordering for some (FQ) scheduling algorithms is a non-trivial problem at high speeds.
- Figure 1 shows the basic layout of the current approach to traffic management. It can be thought of as a "queue first, think later" strategy.
- Data received at the input l is split into a number of queues in parallel channels 2.1 to 2.n.
- a traffic scheduler processor 3 receives the data from the parallel channels and sorts them into order. The order may be determined by the priority attributes, for example, mentioned above. State is stored in memory 4 accessible by the processor. The output from the processor represents the new order as determined by the processor in dependence on the quality of service attributes assigned to the data at the outset.
- the traffic scheduler 3 determines the order of de-queuing. Since the scheduling decision can be processing-intensive as the number of input queues increases, queues are often arranged into small groups which are locally scheduled into an intermediate output queue.
- This output queue is then the input queue to a following scheduling stage.
- the scheduling problem is thus simplified using a "divide-and-conquer" approach, whereby high performance can be achieved through parallelism between groups of queues in a tree type structure, or so-called hierarchical link sharing scheme.
- the invention provides a system comprising means for sorting incoming data packets in real time before said packets are stored in memory.
- the invention provides a data packet handling system, comprising means whereby incoming data packets are assigned an exit order before being stored in memory.
- the sorting means may be responsive to information contained within a packet and/or within a table and/or information associated with a data packet stream in which said packet is located, whereby to determine an exit order number for that packet.
- the packets may be inserted into one or more queues by a queue manager adapted to insert packets into the queue means in exit order. There may be means to drop certain packets before being output from said queue means or before being queued in the queue means.
- the system may be such that the sorting means and the queue means process only packet records containing information about the packets, whereas data portions of the packets are stored in the memory for output in accordance with an exit order determined for the corresponding packet record.
- a state engine may control access to the shared state.
- Tables of information for sorting said packets or said packet records may be provided, wherein said tables are stored locally to each processor or to each processor element of a parallel processor.
- the tables may be the same on each processor or on each processor element of a parallel processor.
- the tables may be different on different processors or on different processor elements of a parallel processor.
- the processors or processor elements may share information from their respective tables, such that: (a) the information held in the table for one processor is directly accessible by a different processor or the information held in the table in one processor element may be accessible by other processing element(s) of the processor; and (b) processors may have access to tables in other processors or processor elements have access to other processor elements in the processor, whereby processors or processor elements can perform table lookups on behalf of other processor(s) or processor elements of the processor.
- the invention also encompasses a computer system, comprising a data handling system as previously specified; a network processing system, comprising a data handling system as previously specified; and a data carrier containing program means adapted to perform a corresponding method.
- Figure 1 is a schematic representation of a prior art traffic handler
- Figure 2 is a schematic representation of a traffic handler in accordance with the invention.
- FIG. 2 shows schematically the basic structure underlying the new strategy for effective traffic management. It could be described as a "think first, queue later TM" strategy.
- Packet data (traffic) received at the input 20 has the header portions stripped off and record portions of fixed length generated therefrom, containing information about the data, so that the record portions and the data portions can be handled separately.
- the data portions take the lower path and are stored in Memory Hub 21.
- a processor 22 such as a SIMD parallel processor, comprising one or more arrays of processor elements (PEs).
- PEs processor elements
- each PE typically, each PE contains its own processor unit, local memory and register(s).
- the present architecture shares state 23 in the PE arrays under the control of a State Engine (not shown) communicating with the PE array(s). It should be emphasised that only the record portions are processed in the PE array. The record portions are all the same length, so their handling is predictable, at least in terms of length. The record portions are handled in the processor 22. Here, information about the incoming packets is distributed amongst the PEs in the array. This array basically performs the same function as the processor 3 in the prior art ( Figure 1) but the operations are spread over the PE array for vastly more rapid processing.
- the memory hub 21 can handle packets streaming in at real time.
- the memory hub can nevertheless divide larger data portions into fragments, if necessary, and store them in physically different locations, provided, of course, there are pointers to the different fragments to ensure read out of the entire content of such data packets.
- multiple PEs are permitted to access (and modify) the state variables.
- the chip will also include necessary additional components, such as a distributor and a collector per PE array to distribute data to the individual PEs and to collect processed data from the PEs, plus semaphore block(s) and interface elements.
- a distributor and a collector per PE array to distribute data to the individual PEs and to collect processed data from the PEs, plus semaphore block(s) and interface elements.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2003801085295A CN1736068B (en) | 2002-11-11 | 2003-11-11 | Flow management structure system |
US10/534,346 US20050243829A1 (en) | 2002-11-11 | 2003-11-11 | Traffic management architecture |
GB0511589A GB2412035B (en) | 2002-11-11 | 2003-11-11 | Traffic management architecture |
AU2003283559A AU2003283559A1 (en) | 2002-11-11 | 2003-11-11 | Traffic management architecture |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0226249.1 | 2002-11-11 | ||
GBGB0226249.1A GB0226249D0 (en) | 2002-11-11 | 2002-11-11 | Traffic handling system |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004045162A2 true WO2004045162A2 (en) | 2004-05-27 |
WO2004045162A3 WO2004045162A3 (en) | 2004-09-16 |
Family
ID=9947583
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2003/004893 WO2004045162A2 (en) | 2002-11-11 | 2003-11-11 | Traffic management architecture |
PCT/GB2003/004867 WO2004044733A2 (en) | 2002-11-11 | 2003-11-11 | State engine for data processor |
PCT/GB2003/004866 WO2004045161A1 (en) | 2002-11-11 | 2003-11-11 | Packet storage system for traffic handling |
PCT/GB2003/004854 WO2004045160A2 (en) | 2002-11-11 | 2003-11-11 | Data packet handling in computer or communication systems |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2003/004867 WO2004044733A2 (en) | 2002-11-11 | 2003-11-11 | State engine for data processor |
PCT/GB2003/004866 WO2004045161A1 (en) | 2002-11-11 | 2003-11-11 | Packet storage system for traffic handling |
PCT/GB2003/004854 WO2004045160A2 (en) | 2002-11-11 | 2003-11-11 | Data packet handling in computer or communication systems |
Country Status (5)
Country | Link |
---|---|
US (5) | US7522605B2 (en) |
CN (4) | CN1736069B (en) |
AU (4) | AU2003283539A1 (en) |
GB (5) | GB0226249D0 (en) |
WO (4) | WO2004045162A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010107413A1 (en) | 2009-03-18 | 2010-09-23 | Texas Research International, Inc. | Environmental damage sensor |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004524617A (en) | 2001-02-14 | 2004-08-12 | クリアスピード・テクノロジー・リミテッド | Clock distribution system |
GB0226249D0 (en) * | 2002-11-11 | 2002-12-18 | Clearspeed Technology Ltd | Traffic handling system |
US7210059B2 (en) | 2003-08-19 | 2007-04-24 | Micron Technology, Inc. | System and method for on-board diagnostics of memory modules |
US7310752B2 (en) * | 2003-09-12 | 2007-12-18 | Micron Technology, Inc. | System and method for on-board timing margin testing of memory modules |
US7120743B2 (en) | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
US6944636B1 (en) * | 2004-04-30 | 2005-09-13 | Microsoft Corporation | Maintaining time-date information for syncing low fidelity devices |
US7310748B2 (en) * | 2004-06-04 | 2007-12-18 | Micron Technology, Inc. | Memory hub tester interface and method for use thereof |
US8316431B2 (en) * | 2004-10-12 | 2012-11-20 | Canon Kabushiki Kaisha | Concurrent IPsec processing system and method |
US20060101210A1 (en) * | 2004-10-15 | 2006-05-11 | Lance Dover | Register-based memory command architecture |
US20060156316A1 (en) * | 2004-12-18 | 2006-07-13 | Gray Area Technologies | System and method for application specific array processing |
EP1832054B1 (en) * | 2004-12-23 | 2018-03-21 | Symantec Corporation | Method and apparatus for network packet capture distributed storage system |
US20100195538A1 (en) * | 2009-02-04 | 2010-08-05 | Merkey Jeffrey V | Method and apparatus for network packet capture distributed storage system |
US7392229B2 (en) * | 2005-02-12 | 2008-06-24 | Curtis L. Harris | General purpose set theoretic processor |
US7746784B2 (en) * | 2006-03-23 | 2010-06-29 | Alcatel-Lucent Usa Inc. | Method and apparatus for improving traffic distribution in load-balancing networks |
US8065249B1 (en) | 2006-10-13 | 2011-11-22 | Harris Curtis L | GPSTP with enhanced aggregation functionality |
US7774286B1 (en) | 2006-10-24 | 2010-08-10 | Harris Curtis L | GPSTP with multiple thread functionality |
US8166212B2 (en) * | 2007-06-26 | 2012-04-24 | Xerox Corporation | Predictive DMA data transfer |
US7830918B2 (en) * | 2007-08-10 | 2010-11-09 | Eaton Corporation | Method of network communication, and node and system employing the same |
JP5068125B2 (en) * | 2007-09-25 | 2012-11-07 | 株式会社日立国際電気 | Communication device |
US8521732B2 (en) | 2008-05-23 | 2013-08-27 | Solera Networks, Inc. | Presentation of an extracted artifact based on an indexing technique |
US8625642B2 (en) | 2008-05-23 | 2014-01-07 | Solera Networks, Inc. | Method and apparatus of network artifact indentification and extraction |
US8004998B2 (en) * | 2008-05-23 | 2011-08-23 | Solera Networks, Inc. | Capture and regeneration of a network data using a virtual software switch |
US20090292736A1 (en) * | 2008-05-23 | 2009-11-26 | Matthew Scott Wood | On demand network activity reporting through a dynamic file system and method |
JP5300355B2 (en) * | 2008-07-14 | 2013-09-25 | キヤノン株式会社 | Network protocol processing apparatus and processing method thereof |
US9213665B2 (en) * | 2008-10-28 | 2015-12-15 | Freescale Semiconductor, Inc. | Data processor for processing a decorated storage notify |
US8627471B2 (en) * | 2008-10-28 | 2014-01-07 | Freescale Semiconductor, Inc. | Permissions checking for data processing instructions |
US8266498B2 (en) | 2009-03-31 | 2012-09-11 | Freescale Semiconductor, Inc. | Implementation of multiple error detection schemes for a cache |
US20110125748A1 (en) * | 2009-11-15 | 2011-05-26 | Solera Networks, Inc. | Method and Apparatus for Real Time Identification and Recording of Artifacts |
US20110125749A1 (en) * | 2009-11-15 | 2011-05-26 | Solera Networks, Inc. | Method and Apparatus for Storing and Indexing High-Speed Network Traffic Data |
US8472455B2 (en) * | 2010-01-08 | 2013-06-25 | Nvidia Corporation | System and method for traversing a treelet-composed hierarchical structure |
US8295287B2 (en) * | 2010-01-27 | 2012-10-23 | National Instruments Corporation | Network traffic shaping for reducing bus jitter on a real time controller |
US8990660B2 (en) | 2010-09-13 | 2015-03-24 | Freescale Semiconductor, Inc. | Data processing system having end-to-end error correction and method therefor |
US8504777B2 (en) | 2010-09-21 | 2013-08-06 | Freescale Semiconductor, Inc. | Data processor for processing decorated instructions with cache bypass |
US8667230B1 (en) | 2010-10-19 | 2014-03-04 | Curtis L. Harris | Recognition and recall memory |
KR20120055779A (en) * | 2010-11-23 | 2012-06-01 | 한국전자통신연구원 | System and method for communicating audio data based zigbee and method thereof |
KR20120064576A (en) * | 2010-12-09 | 2012-06-19 | 한국전자통신연구원 | Apparatus for surpporting continuous read/write in asymmetric storage system and method thereof |
US8849991B2 (en) | 2010-12-15 | 2014-09-30 | Blue Coat Systems, Inc. | System and method for hypertext transfer protocol layered reconstruction |
US8666985B2 (en) | 2011-03-16 | 2014-03-04 | Solera Networks, Inc. | Hardware accelerated application-based pattern matching for real time classification and recording of network traffic |
US8566672B2 (en) | 2011-03-22 | 2013-10-22 | Freescale Semiconductor, Inc. | Selective checkbit modification for error correction |
US8607121B2 (en) | 2011-04-29 | 2013-12-10 | Freescale Semiconductor, Inc. | Selective error detection and error correction for a memory interface |
US8990657B2 (en) | 2011-06-14 | 2015-03-24 | Freescale Semiconductor, Inc. | Selective masking for error correction |
US9525642B2 (en) | 2012-01-31 | 2016-12-20 | Db Networks, Inc. | Ordering traffic captured on a data connection |
US9100291B2 (en) | 2012-01-31 | 2015-08-04 | Db Networks, Inc. | Systems and methods for extracting structured application data from a communications link |
US9092318B2 (en) * | 2012-02-06 | 2015-07-28 | Vmware, Inc. | Method of allocating referenced memory pages from a free list |
US9665233B2 (en) * | 2012-02-16 | 2017-05-30 | The University Utah Research Foundation | Visualization of software memory usage |
WO2014110281A1 (en) | 2013-01-11 | 2014-07-17 | Db Networks, Inc. | Systems and methods for detecting and mitigating threats to a structured data storage system |
CN103338159B (en) * | 2013-06-19 | 2016-08-10 | 华为技术有限公司 | Polling dispatching implementation method and device |
WO2015085087A1 (en) * | 2013-12-04 | 2015-06-11 | Db Networks, Inc. | Ordering traffic captured on a data connection |
JP6249403B2 (en) * | 2014-02-27 | 2017-12-20 | 国立研究開発法人情報通信研究機構 | Optical delay line and electronic buffer fusion type optical packet buffer control device |
US10210592B2 (en) | 2014-03-30 | 2019-02-19 | Teoco Ltd. | System, method, and computer program product for efficient aggregation of data records of big data |
WO2016145405A1 (en) * | 2015-03-11 | 2016-09-15 | Protocol Insight, Llc | Intelligent packet analyzer circuits, systems, and methods |
KR102449333B1 (en) | 2015-10-30 | 2022-10-04 | 삼성전자주식회사 | Memory system and read request management method thereof |
US10924416B2 (en) | 2016-03-23 | 2021-02-16 | Clavister Ab | Method for traffic shaping using a serial packet processing algorithm and a parallel packet processing algorithm |
SE1751244A1 (en) * | 2016-03-23 | 2017-10-09 | Clavister Ab | Method for traffic shaping using a serial packet processing algorithm and a parallel packet processing algorithm |
CN107786465B (en) * | 2016-08-27 | 2021-06-04 | 华为技术有限公司 | Method and device for processing low-delay service flow |
WO2018081582A1 (en) * | 2016-10-28 | 2018-05-03 | Atavium, Inc. | Systems and methods for random to sequential storage mapping |
CN107656895B (en) * | 2017-10-27 | 2023-07-28 | 上海力诺通信科技有限公司 | Orthogonal platform high-density computing architecture with standard height of 1U |
RU2718215C2 (en) * | 2018-09-14 | 2020-03-31 | Общество С Ограниченной Ответственностью "Яндекс" | Data processing system and method for detecting jam in data processing system |
US11138044B2 (en) * | 2018-09-26 | 2021-10-05 | Micron Technology, Inc. | Memory pooling between selected memory resources |
US11093403B2 (en) | 2018-12-04 | 2021-08-17 | Vmware, Inc. | System and methods of a self-tuning cache sizing system in a cache partitioning system |
EP3866417A1 (en) * | 2020-02-14 | 2021-08-18 | Deutsche Telekom AG | Method for an improved traffic shaping and/or management of ip traffic in a packet processing system, telecommunications network, network node or network element, program and computer program product |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0372795A2 (en) * | 1988-12-06 | 1990-06-13 | AT&T Corp. | Bandwidth allocation and congestion control scheme for an integrated voice and data network |
EP1137225A1 (en) * | 2000-02-28 | 2001-09-26 | Alcatel | A switch and a switching method |
US20020075882A1 (en) * | 1998-05-07 | 2002-06-20 | Marc Donis | Multiple priority buffering in a computer network |
Family Cites Families (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5187780A (en) * | 1989-04-07 | 1993-02-16 | Digital Equipment Corporation | Dual-path computer interconnect system with zone manager for packet memory |
DE69132495T2 (en) * | 1990-03-16 | 2001-06-13 | Texas Instruments Inc | Distributed processing memory |
US5280483A (en) * | 1990-08-09 | 1994-01-18 | Fujitsu Limited | Traffic control system for asynchronous transfer mode exchange |
US5765011A (en) * | 1990-11-13 | 1998-06-09 | International Business Machines Corporation | Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams |
ATE180586T1 (en) * | 1990-11-13 | 1999-06-15 | Ibm | PARALLEL ASSOCIATIVE PROCESSOR SYSTEM |
JP2596718B2 (en) * | 1993-12-21 | 1997-04-02 | インターナショナル・ビジネス・マシーンズ・コーポレイション | How to manage network communication buffers |
US5949781A (en) * | 1994-08-31 | 1999-09-07 | Brooktree Corporation | Controller for ATM segmentation and reassembly |
US5513134A (en) | 1995-02-21 | 1996-04-30 | Gte Laboratories Incorporated | ATM shared memory switch with content addressing |
US5633865A (en) * | 1995-03-31 | 1997-05-27 | Netvantage | Apparatus for selectively transferring data packets between local area networks |
DE69841486D1 (en) * | 1997-05-31 | 2010-03-25 | Texas Instruments Inc | Improved packet switching |
US6757798B2 (en) * | 1997-06-30 | 2004-06-29 | Intel Corporation | Method and apparatus for arbitrating deferred read requests |
US5956340A (en) * | 1997-08-05 | 1999-09-21 | Ramot University Authority For Applied Research And Industrial Development Ltd. | Space efficient fair queuing by stochastic Memory multiplexing |
US6088771A (en) * | 1997-10-24 | 2000-07-11 | Digital Equipment Corporation | Mechanism for reducing latency of memory barrier operations on a multiprocessor system |
US6052375A (en) * | 1997-11-26 | 2000-04-18 | International Business Machines Corporation | High speed internetworking traffic scaler and shaper |
US6097403A (en) * | 1998-03-02 | 2000-08-01 | Advanced Micro Devices, Inc. | Memory including logic for operating upon graphics primitives |
US6359879B1 (en) * | 1998-04-24 | 2002-03-19 | Avici Systems | Composite trunking |
US6314489B1 (en) * | 1998-07-10 | 2001-11-06 | Nortel Networks Limited | Methods and systems for storing cell data using a bank of cell buffers |
US6356546B1 (en) * | 1998-08-11 | 2002-03-12 | Nortel Networks Limited | Universal transfer method and network with distributed switch |
US6829218B1 (en) * | 1998-09-15 | 2004-12-07 | Lucent Technologies Inc. | High speed weighted fair queuing system for ATM switches |
US6396843B1 (en) * | 1998-10-30 | 2002-05-28 | Agere Systems Guardian Corp. | Method and apparatus for guaranteeing data transfer rates and delays in data packet networks using logarithmic calendar queues |
SE9803901D0 (en) * | 1998-11-16 | 1998-11-16 | Ericsson Telefon Ab L M | a device for a service network |
US6246682B1 (en) * | 1999-03-05 | 2001-06-12 | Transwitch Corp. | Method and apparatus for managing multiple ATM cell queues |
US6952401B1 (en) * | 1999-03-17 | 2005-10-04 | Broadcom Corporation | Method for load balancing in a network switch |
US6574231B1 (en) * | 1999-05-21 | 2003-06-03 | Advanced Micro Devices, Inc. | Method and apparatus for queuing data frames in a network switch port |
US6671292B1 (en) * | 1999-06-25 | 2003-12-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and system for adaptive voice buffering |
US6643298B1 (en) * | 1999-11-23 | 2003-11-04 | International Business Machines Corporation | Method and apparatus for MPEG-2 program ID re-mapping for multiplexing several programs into a single transport stream |
US7102999B1 (en) * | 1999-11-24 | 2006-09-05 | Juniper Networks, Inc. | Switching device |
US6662263B1 (en) * | 2000-03-03 | 2003-12-09 | Multi Level Memory Technology | Sectorless flash memory architecture |
ATE331369T1 (en) * | 2000-03-06 | 2006-07-15 | Ibm | SWITCHING DEVICE AND METHOD |
US6907041B1 (en) * | 2000-03-07 | 2005-06-14 | Cisco Technology, Inc. | Communications interconnection network with distributed resequencing |
CA2301973A1 (en) * | 2000-03-21 | 2001-09-21 | Spacebridge Networks Corporation | System and method for adaptive slot-mapping input/output queuing for tdm/tdma systems |
US6975629B2 (en) * | 2000-03-22 | 2005-12-13 | Texas Instruments Incorporated | Processing packets based on deadline intervals |
US7139282B1 (en) * | 2000-03-24 | 2006-11-21 | Juniper Networks, Inc. | Bandwidth division for packet processing |
CA2337674A1 (en) * | 2000-04-20 | 2001-10-20 | International Business Machines Corporation | Switching arrangement and method |
JP4484317B2 (en) * | 2000-05-17 | 2010-06-16 | 株式会社日立製作所 | Shaping device |
US6937561B2 (en) | 2000-06-02 | 2005-08-30 | Agere Systems Inc. | Method and apparatus for guaranteeing data transfer rates and enforcing conformance with traffic profiles in a packet network |
JP3640160B2 (en) * | 2000-07-26 | 2005-04-20 | 日本電気株式会社 | Router device and priority control method used therefor |
DE60119866T2 (en) * | 2000-09-27 | 2007-05-10 | International Business Machines Corp. | Switching device and method with separate output buffers |
US20020062415A1 (en) * | 2000-09-29 | 2002-05-23 | Zarlink Semiconductor N.V. Inc. | Slotted memory access method |
US6647477B2 (en) * | 2000-10-06 | 2003-11-11 | Pmc-Sierra Ltd. | Transporting data transmission units of different sizes using segments of fixed sizes |
US6871780B2 (en) * | 2000-11-27 | 2005-03-29 | Airclic, Inc. | Scalable distributed database system and method for linking codes to internet information |
US6888848B2 (en) * | 2000-12-14 | 2005-05-03 | Nortel Networks Limited | Compact segmentation of variable-size packet streams |
US7035212B1 (en) * | 2001-01-25 | 2006-04-25 | Optim Networks | Method and apparatus for end to end forwarding architecture |
US20020126659A1 (en) * | 2001-03-07 | 2002-09-12 | Ling-Zhong Liu | Unified software architecture for switch connection management |
US6728857B1 (en) * | 2001-06-20 | 2004-04-27 | Cisco Technology, Inc. | Method and system for storing and retrieving data using linked lists |
US7382787B1 (en) * | 2001-07-30 | 2008-06-03 | Cisco Technology, Inc. | Packet routing and switching device |
US7349403B2 (en) * | 2001-09-19 | 2008-03-25 | Bay Microsystems, Inc. | Differentiated services for a network processor |
US6900920B2 (en) * | 2001-09-21 | 2005-05-31 | The Regents Of The University Of California | Variable semiconductor all-optical buffer using slow light based on electromagnetically induced transparency |
US20030081623A1 (en) * | 2001-10-27 | 2003-05-01 | Amplify.Net, Inc. | Virtual queues in a single queue in the bandwidth management traffic-shaping cell |
US7215666B1 (en) * | 2001-11-13 | 2007-05-08 | Nortel Networks Limited | Data burst scheduling |
US20030145086A1 (en) * | 2002-01-29 | 2003-07-31 | O'reilly James | Scalable network-attached storage system |
US20040022094A1 (en) * | 2002-02-25 | 2004-02-05 | Sivakumar Radhakrishnan | Cache usage for concurrent multiple streams |
US6862639B2 (en) * | 2002-03-11 | 2005-03-01 | Harris Corporation | Computer system including a receiver interface circuit with a scatter pointer queue and related methods |
US7126959B2 (en) * | 2002-03-12 | 2006-10-24 | Tropic Networks Inc. | High-speed packet memory |
US6928026B2 (en) * | 2002-03-19 | 2005-08-09 | Broadcom Corporation | Synchronous global controller for enhanced pipelining |
US20030188056A1 (en) * | 2002-03-27 | 2003-10-02 | Suresh Chemudupati | Method and apparatus for packet reformatting |
US7239608B2 (en) * | 2002-04-26 | 2007-07-03 | Samsung Electronics Co., Ltd. | Router using measurement-based adaptable load traffic balancing system and method of operation |
JP3789395B2 (en) * | 2002-06-07 | 2006-06-21 | 富士通株式会社 | Packet processing device |
US20040039884A1 (en) * | 2002-08-21 | 2004-02-26 | Qing Li | System and method for managing the memory in a computer system |
US6950894B2 (en) * | 2002-08-28 | 2005-09-27 | Intel Corporation | Techniques using integrated circuit chip capable of being coupled to storage system |
US7180899B2 (en) * | 2002-10-29 | 2007-02-20 | Cisco Technology, Inc. | Multi-tiered Virtual Local area Network (VLAN) domain mapping mechanism |
GB0226249D0 (en) * | 2002-11-11 | 2002-12-18 | Clearspeed Technology Ltd | Traffic handling system |
KR100532325B1 (en) * | 2002-11-23 | 2005-11-29 | 삼성전자주식회사 | Input control method and apparatus for turbo decoder |
GB2421158B (en) * | 2003-10-03 | 2007-07-11 | Avici Systems Inc | Rapid alternate paths for network destinations |
US7668100B2 (en) * | 2005-06-28 | 2010-02-23 | Avaya Inc. | Efficient load balancing and heartbeat mechanism for telecommunication endpoints |
-
2002
- 2002-11-11 GB GBGB0226249.1A patent/GB0226249D0/en not_active Ceased
-
2003
- 2003-11-11 WO PCT/GB2003/004893 patent/WO2004045162A2/en not_active Application Discontinuation
- 2003-11-11 GB GB0509997A patent/GB2411271B/en not_active Expired - Fee Related
- 2003-11-11 WO PCT/GB2003/004867 patent/WO2004044733A2/en not_active Application Discontinuation
- 2003-11-11 AU AU2003283539A patent/AU2003283539A1/en not_active Abandoned
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- 2003-11-11 US US10/534,346 patent/US20050243829A1/en not_active Abandoned
- 2003-11-11 AU AU2003283545A patent/AU2003283545A1/en not_active Abandoned
- 2003-11-11 GB GB0511587A patent/GB2412537B/en not_active Expired - Fee Related
- 2003-11-11 US US10/534,343 patent/US7843951B2/en not_active Expired - Fee Related
- 2003-11-11 CN CN2003801085295A patent/CN1736068B/en not_active Expired - Fee Related
- 2003-11-11 AU AU2003283544A patent/AU2003283544A1/en not_active Abandoned
- 2003-11-11 WO PCT/GB2003/004866 patent/WO2004045161A1/en not_active Application Discontinuation
- 2003-11-11 US US10/534,430 patent/US7882312B2/en not_active Expired - Fee Related
- 2003-11-11 GB GB0511588A patent/GB2413031B/en not_active Expired - Fee Related
- 2003-11-11 WO PCT/GB2003/004854 patent/WO2004045160A2/en not_active Application Discontinuation
- 2003-11-11 AU AU2003283559A patent/AU2003283559A1/en not_active Abandoned
- 2003-11-11 CN CNB200380108223XA patent/CN100557594C/en not_active Expired - Fee Related
- 2003-11-11 GB GB0511589A patent/GB2412035B/en not_active Expired - Fee Related
-
2010
- 2010-11-29 US US12/955,684 patent/US8472457B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0372795A2 (en) * | 1988-12-06 | 1990-06-13 | AT&T Corp. | Bandwidth allocation and congestion control scheme for an integrated voice and data network |
US20020075882A1 (en) * | 1998-05-07 | 2002-06-20 | Marc Donis | Multiple priority buffering in a computer network |
EP1137225A1 (en) * | 2000-02-28 | 2001-09-26 | Alcatel | A switch and a switching method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010107413A1 (en) | 2009-03-18 | 2010-09-23 | Texas Research International, Inc. | Environmental damage sensor |
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