WO2004049169A3 - Using a cache miss pattern to address a stride prediction table - Google Patents

Using a cache miss pattern to address a stride prediction table Download PDF

Info

Publication number
WO2004049169A3
WO2004049169A3 PCT/IB2003/005165 IB0305165W WO2004049169A3 WO 2004049169 A3 WO2004049169 A3 WO 2004049169A3 IB 0305165 W IB0305165 W IB 0305165W WO 2004049169 A3 WO2004049169 A3 WO 2004049169A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
cache miss
memory circuit
cache
cache memory
Prior art date
Application number
PCT/IB2003/005165
Other languages
French (fr)
Other versions
WO2004049169A2 (en
Inventor
De Waerdt Jan-Willem Van
Jan Hoogerbrugge
Original Assignee
Koninkl Philips Electronics Nv
Philips Corp
De Waerdt Jan-Willem Van
Jan Hoogerbrugge
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Corp, De Waerdt Jan-Willem Van, Jan Hoogerbrugge filed Critical Koninkl Philips Electronics Nv
Priority to EP03772449A priority Critical patent/EP1586039A2/en
Priority to JP2004554787A priority patent/JP2006516168A/en
Priority to AU2003280056A priority patent/AU2003280056A1/en
Priority to US10/535,591 priority patent/US20060059311A1/en
Publication of WO2004049169A2 publication Critical patent/WO2004049169A2/en
Publication of WO2004049169A3 publication Critical patent/WO2004049169A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

Data prefetching is used to reduce an average latency of memory references for retrieval of data therefrom. The prefetching process is typically based on anticipation of future processor data references. In example embodiment, there is a method of data retrieval that comprises providing a first memory circuit (610), a stride prediction (611) table (SPT) and a cache memory circuit (612). Instructions for accessing data (613) within the first memory are executed. A cache miss (614) is detected. Only when a cache miss is detected is the SPT accessed and updated (615). A feature of this embodiment includes using a stream buffer as the cache memory circuit. Another feature includes using random access cache memory as the cache memory circuit.
PCT/IB2003/005165 2002-11-22 2003-11-11 Using a cache miss pattern to address a stride prediction table WO2004049169A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP03772449A EP1586039A2 (en) 2002-11-22 2003-11-11 Using a cache miss pattern to address a stride prediction table
JP2004554787A JP2006516168A (en) 2002-11-22 2003-11-11 How to use a cache miss pattern to address the stride prediction table
AU2003280056A AU2003280056A1 (en) 2002-11-22 2003-11-11 Using a cache miss pattern to address a stride prediction table
US10/535,591 US20060059311A1 (en) 2002-11-22 2003-11-11 Using a cache miss pattern to address a stride prediction table

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US42828502P 2002-11-22 2002-11-22
US60/428,285 2002-11-22

Publications (2)

Publication Number Publication Date
WO2004049169A2 WO2004049169A2 (en) 2004-06-10
WO2004049169A3 true WO2004049169A3 (en) 2006-06-22

Family

ID=32393375

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/005165 WO2004049169A2 (en) 2002-11-22 2003-11-11 Using a cache miss pattern to address a stride prediction table

Country Status (6)

Country Link
US (1) US20060059311A1 (en)
EP (1) EP1586039A2 (en)
JP (1) JP2006516168A (en)
CN (1) CN1849591A (en)
AU (1) AU2003280056A1 (en)
WO (1) WO2004049169A2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7669194B2 (en) * 2004-08-26 2010-02-23 International Business Machines Corporation Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations
US7464246B2 (en) * 2004-09-30 2008-12-09 International Business Machines Corporation System and method for dynamic sizing of cache sequential list
US7373480B2 (en) * 2004-11-18 2008-05-13 Sun Microsystems, Inc. Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table
US7366871B2 (en) 2004-11-18 2008-04-29 Sun Microsystems, Inc. Apparatus and method for determining stack distance including spatial locality of running software for estimating cache miss rates based upon contents of a hash table
US20070150653A1 (en) * 2005-12-22 2007-06-28 Intel Corporation Processing of cacheable streaming data
US7774578B2 (en) * 2006-06-07 2010-08-10 Advanced Micro Devices, Inc. Apparatus and method of prefetching data in response to a cache miss
AU2010201718B2 (en) * 2010-04-29 2012-08-23 Canon Kabushiki Kaisha Method, system and apparatus for identifying a cache line
CN102662713B (en) 2012-04-12 2014-04-16 腾讯科技（深圳）有限公司 Method, device and terminal for increasing running speed of application programs
US20140122796A1 (en) * 2012-10-31 2014-05-01 Netapp, Inc. Systems and methods for tracking a sequential data stream stored in non-sequential storage blocks
US10140210B2 (en) 2013-09-24 2018-11-27 Intel Corporation Method and apparatus for cache occupancy determination and instruction scheduling
JP6341045B2 (en) 2014-10-03 2018-06-13 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
CN106776371B (en) * 2015-12-14 2019-11-26 上海兆芯集成电路有限公司 Span refers to prefetcher, processor and the method for pre-fetching data into processor
US10169240B2 (en) * 2016-04-08 2019-01-01 Qualcomm Incorporated Reducing memory access bandwidth based on prediction of memory request size
US20180052779A1 (en) * 2016-08-19 2018-02-22 Advanced Micro Devices, Inc. Data cache region prefetcher
US10592414B2 (en) 2017-07-14 2020-03-17 International Business Machines Corporation Filtering of redundantly scheduled write passes
US10713053B2 (en) * 2018-04-06 2020-07-14 Intel Corporation Adaptive spatial access prefetcher apparatus and method
US10467141B1 (en) 2018-06-18 2019-11-05 International Business Machines Corporation Process data caching through iterative feedback
US10671394B2 (en) 2018-10-31 2020-06-02 International Business Machines Corporation Prefetch stream allocation for multithreading systems
US11194575B2 (en) * 2019-11-07 2021-12-07 International Business Machines Corporation Instruction address based data prediction and prefetching

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761706A (en) * 1994-11-01 1998-06-02 Cray Research, Inc. Stream buffers for high-performance computer memory system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261066A (en) * 1990-03-27 1993-11-09 Digital Equipment Corporation Data processing system and method with small fully-associative cache and prefetch buffers
US5822790A (en) * 1997-02-07 1998-10-13 Sun Microsystems, Inc. Voting data prefetch engine
KR100560948B1 (en) * 2004-03-31 2006-03-14 매그나칩 반도체 유한회사 6 Transistor Dual Port SRAM Cell

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761706A (en) * 1994-11-01 1998-06-02 Cray Research, Inc. Stream buffers for high-performance computer memory system

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
CHEN T-F ET AL: "EFFECTIVE HARDWARE-BASED DATA PREFETCHING FOR HIGH-PERFORMANCE PROCESSORS", IEEE TRANSACTIONS ON COMPUTERS, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 44, no. 5, 1 May 1995 (1995-05-01), pages 609 - 623, XP000525553, ISSN: 0018-9340 *
HARIPRAKASH G ET AL: "DSTRIDE: data-cache miss-address-based stride prefetching scheme for multimedia processors", COMPUTER SYSTEMS ARCHITECTURE CONFERENCE, 2001. ACSAC 2001. PROCEEDINGS. 6TH AUSTRALASIAN 29-30 JANUARY 2001, PISCATAWAY, NJ, USA,IEEE, 29 January 2001 (2001-01-29), pages 62 - 70, XP010531908, ISBN: 0-7695-0954-1 *
KIM S ET AL: "Stride-directed prefetching for secondary caches", PARALLEL PROCESSING, 1997., PROCEEDINGS OF THE 1997 INTERNATIONAL CONFERENCE ON BLOOMINGTON, IL, USA 11-15 AUG. 1997, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 11 August 1997 (1997-08-11), pages 314 - 321, XP010245233, ISBN: 0-8186-8108-X *
SHERWOOD T ET AL: "Predictor-directed stream buffers", MICRO-33. PROCEEDINGS OF THE 33RD. ANNUAL ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE. MONTEREY, CA, DEC. 10 - 13, 2000, PROCEEDINGS OF THE ANNUAL ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, LOS ALAMITOS, CA : IEEE COMP. SOC, US, 10 December 2000 (2000-12-10), pages 42 - 53, XP010528874, ISBN: 0-7695-0924-X *
VANDERWIEL S P ET AL: "Data prefetch mechanisms", ACM COMPUTING SURVEYS, ACM, NEW YORK, NY, US, US, vol. 32, no. 2, June 2000 (2000-06-01), pages 174 - 199, XP002977351, ISSN: 0360-0300 *
ZUCKER D F ET AL: "HARDWARE AND SOFTWARE CACHE PREFETCHING TECHNIQUES FOR MPEG BENCHMARKS", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 10, no. 5, August 2000 (2000-08-01), pages 782 - 796, XP000950209, ISSN: 1051-8215 *

Also Published As

Publication number Publication date
AU2003280056A1 (en) 2004-06-18
WO2004049169A2 (en) 2004-06-10
JP2006516168A (en) 2006-06-22
CN1849591A (en) 2006-10-18
EP1586039A2 (en) 2005-10-19
AU2003280056A8 (en) 2004-06-18
US20060059311A1 (en) 2006-03-16

Similar Documents

Publication Publication Date Title
WO2004049169A3 (en) Using a cache miss pattern to address a stride prediction table
CN106537362B (en) Data processing apparatus and method of processing address conversion in data processing apparatus
TWI451334B (en) Microprocessor and method for reducing tablewalk time
JP6859361B2 (en) Performing memory bandwidth compression using multiple Last Level Cache (LLC) lines in a central processing unit (CPU) -based system
US6961820B2 (en) System and method for identifying and accessing streaming data in a locked portion of a cache
US5778422A (en) Data processing system memory controller that selectively caches data associated with write requests
US20050268046A1 (en) Compressed cache lines incorporating embedded prefetch history data
TW200601045A (en) Adaptive caching
WO2000043854A3 (en) Preloading data in a cache memory according to user-specified preload criteria
US20030105938A1 (en) Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcher
US20050144387A1 (en) Mechanism to include hints within compressed data
WO2002019114A3 (en) Multi-tier caching system
WO2005114669A3 (en) System and method for improving performance in computer memory systems supporting multiple memory access latencies
CA2538568A1 (en) Data profiling
EP1622007A3 (en) Information processing apparatus and software pre-fetch control method
US20220283955A1 (en) Data cache region prefetcher
EP2284712A3 (en) Method of controlling a cache memory to increase an access speed to a main memory, and a computer using the method
CA2249392A1 (en) Pixel engine data caching mechanism
JPH06266616A (en) Memory access controller
MX2007005861A (en) Method and system for exchanging data.
TW243509B (en) Data processor with memory cache and method of operation
KR20150057798A (en) Apparatus and method for controlling a cache
US20150081983A1 (en) Pre-fetch in a multi-stage memory management system
US20030105937A1 (en) Method and apparatus for content-aware prefetching
ATE389208T1 (en) ASSOCIATIVE MEMORY FOR CACHE STORAGE

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003772449

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2004554787

Country of ref document: JP

ENP Entry into the national phase

Ref document number: 2006059311

Country of ref document: US

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 10535591

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 20038A39526

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2003772449

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 10535591

Country of ref document: US

WWW Wipo information: withdrawn in national office

Ref document number: 2003772449

Country of ref document: EP