WO2004049393A3 - Annealing process of semiconductor wafer and device thereof - Google Patents

Annealing process of semiconductor wafer and device thereof Download PDF

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Publication number
WO2004049393A3
WO2004049393A3 PCT/IB2003/006178 IB0306178W WO2004049393A3 WO 2004049393 A3 WO2004049393 A3 WO 2004049393A3 IB 0306178 W IB0306178 W IB 0306178W WO 2004049393 A3 WO2004049393 A3 WO 2004049393A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
budget
layer
annealing process
embrittlement zone
Prior art date
Application number
PCT/IB2003/006178
Other languages
French (fr)
Other versions
WO2004049393A2 (en
Inventor
Walter Schwarzenbach
Jean-Marc Waechter
Original Assignee
Soitec Silicon On Insulator
Walter Schwarzenbach
Jean-Marc Waechter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Walter Schwarzenbach, Jean-Marc Waechter filed Critical Soitec Silicon On Insulator
Priority to AU2003294158A priority Critical patent/AU2003294158A1/en
Priority to DE10393798T priority patent/DE10393798T5/en
Priority to JP2004554852A priority patent/JP5111730B2/en
Publication of WO2004049393A2 publication Critical patent/WO2004049393A2/en
Publication of WO2004049393A3 publication Critical patent/WO2004049393A3/en

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

The invention relates to a thermal annealing process for a wafer (T) of material chosen among the semiconductor materials for the purpose of detaching a layer from the said wafer at an embrittlement zone, characterised in that during annealing: -a basic thermal budget is applied to the wafer, said basic thermal budget being slightly inferior to the budget necessary to detach the layer, this budget being distributed in an even manner over the embrittlement zone; -an additional thermal budget is also applied to the wafer locally in a set region of the embrittlement zone so as to initiate the layer in this region. The invention also relates to a device for the implementation of such a process.
PCT/IB2003/006178 2002-11-27 2003-11-27 Annealing process of semiconductor wafer and device thereof WO2004049393A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003294158A AU2003294158A1 (en) 2002-11-27 2003-11-27 Annealing process of semiconductor wafer and device thereof
DE10393798T DE10393798T5 (en) 2002-11-27 2003-11-27 Annealing process and device of a semiconductor wafer
JP2004554852A JP5111730B2 (en) 2002-11-27 2003-11-27 Semiconductor wafer annealing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0214864 2002-11-27
FR0214864A FR2847714B1 (en) 2002-11-27 2002-11-27 SEMICONDUCTOR WAFER RECOVERY METHOD AND DEVICE

Publications (2)

Publication Number Publication Date
WO2004049393A2 WO2004049393A2 (en) 2004-06-10
WO2004049393A3 true WO2004049393A3 (en) 2004-08-05

Family

ID=32241658

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/006178 WO2004049393A2 (en) 2002-11-27 2003-11-27 Annealing process of semiconductor wafer and device thereof

Country Status (6)

Country Link
US (2) US7094668B2 (en)
JP (1) JP5111730B2 (en)
AU (1) AU2003294158A1 (en)
DE (1) DE10393798T5 (en)
FR (1) FR2847714B1 (en)
WO (1) WO2004049393A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2858715B1 (en) * 2003-08-04 2005-12-30 Soitec Silicon On Insulator METHOD FOR DETACHING SEMICONDUCTOR LAYER
WO2007080013A1 (en) * 2006-01-09 2007-07-19 International Business Machines Corporation Method and apparatus for treating bonded wafer semiconductor substrates
US8476147B2 (en) * 2010-02-03 2013-07-02 Semiconductor Energy Laboratory Co., Ltd. SOI substrate and manufacturing method thereof
CN107918686A (en) * 2016-10-09 2018-04-17 苏州能讯高能半导体有限公司 Improve the method for high annealing heat distribution
CN111048451B (en) * 2019-12-20 2022-11-25 浙江爱旭太阳能科技有限公司 Gas circulation device, annealing furnace and method for annealing solar cell

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0291147A1 (en) * 1987-05-14 1988-11-17 Semitherm Inc. Vertical thermal processor
WO1999049501A2 (en) * 1998-03-26 1999-09-30 Applied Materials, Inc. A high temperature multi-layered alloy heater assembly and related methods
US6013563A (en) * 1997-05-12 2000-01-11 Silicon Genesis Corporation Controlled cleaning process
EP1100127A1 (en) * 1999-04-09 2001-05-16 Shin-Etsu Handotai Co., Ltd Soi wafer and method for producing soi wafer
DE10008829A1 (en) * 2000-02-25 2001-09-06 Steag Rtp Systems Gmbh Process for removing adsorbed molecules from a chamber
EP1256973A1 (en) * 2001-04-12 2002-11-13 Infineon Technologies SC300 GmbH & Co. KG Heating system and method for heating an atmospheric reactor
EP1258909A2 (en) * 2001-05-16 2002-11-20 Asm International N.V. Method and device for the heat treatment of substrates

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616264A (en) * 1993-06-15 1997-04-01 Tokyo Electron Limited Method and apparatus for controlling temperature in rapid heat treatment system
US6291313B1 (en) 1997-05-12 2001-09-18 Silicon Genesis Corporation Method and device for controlled cleaving process
US6582999B2 (en) 1997-05-12 2003-06-24 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
AU7685198A (en) * 1997-05-12 1998-12-08 Silicon Genesis Corporation A controlled cleavage process
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
JP2001319885A (en) * 2000-03-02 2001-11-16 Hitachi Kokusai Electric Inc Processing system for substrate and method for producing semiconductor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0291147A1 (en) * 1987-05-14 1988-11-17 Semitherm Inc. Vertical thermal processor
US6013563A (en) * 1997-05-12 2000-01-11 Silicon Genesis Corporation Controlled cleaning process
US6048411A (en) * 1997-05-12 2000-04-11 Silicon Genesis Corporation Silicon-on-silicon hybrid wafer assembly
WO1999049501A2 (en) * 1998-03-26 1999-09-30 Applied Materials, Inc. A high temperature multi-layered alloy heater assembly and related methods
EP1100127A1 (en) * 1999-04-09 2001-05-16 Shin-Etsu Handotai Co., Ltd Soi wafer and method for producing soi wafer
DE10008829A1 (en) * 2000-02-25 2001-09-06 Steag Rtp Systems Gmbh Process for removing adsorbed molecules from a chamber
EP1256973A1 (en) * 2001-04-12 2002-11-13 Infineon Technologies SC300 GmbH & Co. KG Heating system and method for heating an atmospheric reactor
EP1258909A2 (en) * 2001-05-16 2002-11-20 Asm International N.V. Method and device for the heat treatment of substrates

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LIN C-T ET AL: "Temperature control of rapid thermal processing system using adaptive fuzzy network", FUZZY SETS AND SYSTEMS, NORTH-HOLLAND, AMSTERDAM, NL, vol. 103, no. 1, 1 April 1999 (1999-04-01), pages 49 - 65, XP004157901, ISSN: 0165-0114 *

Also Published As

Publication number Publication date
US7466907B2 (en) 2008-12-16
DE10393798T5 (en) 2005-11-17
FR2847714A1 (en) 2004-05-28
WO2004049393A2 (en) 2004-06-10
JP5111730B2 (en) 2013-01-09
FR2847714B1 (en) 2005-02-18
US20060204230A1 (en) 2006-09-14
AU2003294158A1 (en) 2004-06-18
AU2003294158A8 (en) 2004-06-18
US20040137762A1 (en) 2004-07-15
JP2006508533A (en) 2006-03-09
US7094668B2 (en) 2006-08-22

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