WO2004053879A3 - Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency - Google Patents

Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency Download PDF

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Publication number
WO2004053879A3
WO2004053879A3 PCT/US2003/039187 US0339187W WO2004053879A3 WO 2004053879 A3 WO2004053879 A3 WO 2004053879A3 US 0339187 W US0339187 W US 0339187W WO 2004053879 A3 WO2004053879 A3 WO 2004053879A3
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WO
WIPO (PCT)
Prior art keywords
power
write latency
memory device
low
mode
Prior art date
Application number
PCT/US2003/039187
Other languages
French (fr)
Other versions
WO2004053879A2 (en
Inventor
Christopher S Johnson
Brian Johnson
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to EP03812914A priority Critical patent/EP1573270A4/en
Priority to KR1020057010745A priority patent/KR100929333B1/en
Priority to AU2003296420A priority patent/AU2003296420A1/en
Priority to JP2004558629A priority patent/JP4310544B2/en
Priority to CN2003801096800A priority patent/CN1748261B/en
Publication of WO2004053879A2 publication Critical patent/WO2004053879A2/en
Publication of WO2004053879A3 publication Critical patent/WO2004053879A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Abstract

A logic circuit (110) operates write receivers in a dynamic random access memory device (20, 22) in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit (110) receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit (110) maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.
PCT/US2003/039187 2002-12-11 2003-12-09 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency WO2004053879A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP03812914A EP1573270A4 (en) 2002-12-11 2003-12-09 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
KR1020057010745A KR100929333B1 (en) 2002-12-11 2003-12-09 Memory device and method having low power, high write latency mode and high power, low write latency mode and / or independently selectable write latency
AU2003296420A AU2003296420A1 (en) 2002-12-11 2003-12-09 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
JP2004558629A JP4310544B2 (en) 2002-12-11 2003-12-09 Storage device and method with low power / high write latency mode and high power / low write latency mode and / or independently selectable write latency
CN2003801096800A CN1748261B (en) 2002-12-11 2003-12-09 Method and device write latency control of memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/317,429 US6934199B2 (en) 2002-12-11 2002-12-11 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
US10/317,429 2002-12-11

Publications (2)

Publication Number Publication Date
WO2004053879A2 WO2004053879A2 (en) 2004-06-24
WO2004053879A3 true WO2004053879A3 (en) 2005-07-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/039187 WO2004053879A2 (en) 2002-12-11 2003-12-09 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency

Country Status (8)

Country Link
US (7) US6934199B2 (en)
EP (1) EP1573270A4 (en)
JP (1) JP4310544B2 (en)
KR (1) KR100929333B1 (en)
CN (1) CN1748261B (en)
AU (1) AU2003296420A1 (en)
TW (1) TWI314736B (en)
WO (1) WO2004053879A2 (en)

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Also Published As

Publication number Publication date
US7826283B2 (en) 2010-11-02
US20040114448A1 (en) 2004-06-17
US6934199B2 (en) 2005-08-23
AU2003296420A1 (en) 2004-06-30
US20050122797A1 (en) 2005-06-09
US20110038217A1 (en) 2011-02-17
WO2004053879A2 (en) 2004-06-24
US20060152983A1 (en) 2006-07-13
US7254067B2 (en) 2007-08-07
JP2006515453A (en) 2006-05-25
US20090067267A1 (en) 2009-03-12
TWI314736B (en) 2009-09-11
US7149141B2 (en) 2006-12-12
US8164965B2 (en) 2012-04-24
KR20050085606A (en) 2005-08-29
CN1748261A (en) 2006-03-15
US20050117414A1 (en) 2005-06-02
JP4310544B2 (en) 2009-08-12
AU2003296420A8 (en) 2004-06-30
CN1748261B (en) 2010-05-26
EP1573270A2 (en) 2005-09-14
US20070268756A1 (en) 2007-11-22
KR100929333B1 (en) 2009-12-03
US7450447B2 (en) 2008-11-11
EP1573270A4 (en) 2009-07-22
US7027337B2 (en) 2006-04-11
TW200511317A (en) 2005-03-16

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