WO2004061677A3 - Speculative distributed conflict resolution for a cache coherency protocol - Google Patents

Speculative distributed conflict resolution for a cache coherency protocol Download PDF

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Publication number
WO2004061677A3
WO2004061677A3 PCT/US2003/037782 US0337782W WO2004061677A3 WO 2004061677 A3 WO2004061677 A3 WO 2004061677A3 US 0337782 W US0337782 W US 0337782W WO 2004061677 A3 WO2004061677 A3 WO 2004061677A3
Authority
WO
WIPO (PCT)
Prior art keywords
node
conflicts
conflict resolution
conflict
conflicting
Prior art date
Application number
PCT/US2003/037782
Other languages
French (fr)
Other versions
WO2004061677A2 (en
Inventor
Herbert Hum
James Goodman
Robert Beers
Ghughal Rajnish
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to DE10393919.9T priority Critical patent/DE10393919B4/en
Priority to AU2003295949A priority patent/AU2003295949A1/en
Priority to JP2004565115A priority patent/JP4261487B2/en
Publication of WO2004061677A2 publication Critical patent/WO2004061677A2/en
Publication of WO2004061677A3 publication Critical patent/WO2004061677A3/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/622—State-only directory, i.e. not recording identity of sharing or owning nodes

Abstract

A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.
PCT/US2003/037782 2002-12-19 2003-11-26 Speculative distributed conflict resolution for a cache coherency protocol WO2004061677A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10393919.9T DE10393919B4 (en) 2002-12-19 2003-11-26 Speculative distributed conflict resolution for a cache coherence protocol
AU2003295949A AU2003295949A1 (en) 2002-12-19 2003-11-26 Speculative distributed conflict resolution for a cache coherency protocol
JP2004565115A JP4261487B2 (en) 2002-12-19 2003-11-26 Speculative distributed contention resolution for cache coherence protocols

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/325,427 2002-12-19
US10/325,427 US7917646B2 (en) 2002-12-19 2002-12-19 Speculative distributed conflict resolution for a cache coherency protocol

Publications (2)

Publication Number Publication Date
WO2004061677A2 WO2004061677A2 (en) 2004-07-22
WO2004061677A3 true WO2004061677A3 (en) 2006-02-16

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PCT/US2003/037782 WO2004061677A2 (en) 2002-12-19 2003-11-26 Speculative distributed conflict resolution for a cache coherency protocol

Country Status (7)

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US (2) US7917646B2 (en)
JP (1) JP4261487B2 (en)
KR (1) KR100841484B1 (en)
CN (1) CN100468365C (en)
AU (1) AU2003295949A1 (en)
DE (1) DE10393919B4 (en)
WO (1) WO2004061677A2 (en)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7526672B2 (en) * 2004-02-25 2009-04-28 Microsoft Corporation Mutual exclusion techniques in a dynamic peer-to-peer environment
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
US20070073977A1 (en) * 2005-09-29 2007-03-29 Safranek Robert J Early global observation point for a uniprocessor system
US20070150664A1 (en) * 2005-12-28 2007-06-28 Chris Dombrowski System and method for default data forwarding coherent caching agent
US7506108B2 (en) * 2006-06-30 2009-03-17 Intel Corporation Requester-generated forward for late conflicts in a cache coherency protocol
US7536515B2 (en) * 2006-06-30 2009-05-19 Intel Corporation Repeated conflict acknowledgements in a cache coherency protocol
US7721050B2 (en) * 2006-06-30 2010-05-18 Intel Corporation Re-snoop for conflict resolution in a cache coherency protocol
US7836144B2 (en) * 2006-12-29 2010-11-16 Intel Corporation System and method for a 3-hop cache coherency protocol
US7500037B2 (en) * 2007-01-30 2009-03-03 International Business Machines Corporation System, method and program for managing locks
US7934059B2 (en) * 2008-01-29 2011-04-26 International Business Machines Corporation Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching
US8190820B2 (en) * 2008-06-13 2012-05-29 Intel Corporation Optimizing concurrent accesses in a directory-based coherency protocol
US8250311B2 (en) 2008-07-07 2012-08-21 Intel Corporation Satisfying memory ordering requirements between partial reads and non-snoop accesses
US8205045B2 (en) * 2008-07-07 2012-06-19 Intel Corporation Satisfying memory ordering requirements between partial writes and non-snoop accesses
JP4600700B2 (en) * 2009-03-17 2010-12-15 日本電気株式会社 Method, apparatus, and program for arranging program in memory space
JP5408713B2 (en) * 2009-09-29 2014-02-05 エヌイーシーコンピュータテクノ株式会社 Cache memory control system and cache memory control method
US8244986B2 (en) * 2009-12-30 2012-08-14 Empire Technology Development, Llc Data storage and access in multi-core processor architectures
US8463960B2 (en) * 2011-08-08 2013-06-11 Arm Limited Synchronisation of data processing systems
US10204049B2 (en) 2012-01-06 2019-02-12 Intel Corporation Value of forward state by increasing local caching agent forwarding
US10268583B2 (en) * 2012-10-22 2019-04-23 Intel Corporation High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier
US9906597B2 (en) * 2015-04-07 2018-02-27 Microsoft Technology Licensing, Llc Collaboration data proxy system in cloud computing platforms
US10230583B1 (en) 2015-09-18 2019-03-12 Amazon Technologies, Inc. Multi-node object simulation
US10506031B1 (en) 2015-09-18 2019-12-10 Amazon Technologies, Inc. Scalable network for processing virtual environments
US10911535B1 (en) * 2015-09-18 2021-02-02 Amazon Technologies, Inc. Object ownership migration
US10104173B1 (en) 2015-09-18 2018-10-16 Amazon Technologies, Inc. Object subscription rule propagation
US10484249B1 (en) 2015-09-18 2019-11-19 Amazon Technologies, Inc. Dynamic distribution of simulation load
US10298679B1 (en) 2015-09-18 2019-05-21 Amazon Technologies, Inc. Object ownership migration
US10230809B2 (en) * 2016-02-29 2019-03-12 Intel Corporation Managing replica caching in a distributed storage system
US10802971B2 (en) 2016-10-13 2020-10-13 International Business Machines Corporation Cache memory transaction shielding via prefetch suppression
US10585800B2 (en) * 2017-06-16 2020-03-10 International Business Machines Corporation Reducing cache transfer overhead in a system
CN109840216B (en) * 2017-11-28 2023-05-09 华为技术有限公司 Data processing method for cache and related elements, devices and systems
CN110083548B (en) * 2018-01-26 2023-01-13 华为技术有限公司 Data processing method and related network element, equipment and system
US11229038B2 (en) * 2018-08-09 2022-01-18 Qualcomm Incorporated Multi-link network coordination

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020129211A1 (en) * 2000-12-30 2002-09-12 Arimilli Ravi Kumar Data processing system and method for resolving a conflict between requests to modify a shared cache line

Family Cites Families (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026A (en) * 1849-01-09 Cast-iron car-wheel
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
JP2952128B2 (en) * 1992-01-27 1999-09-20 キヤノン株式会社 Fabric for inkjet printing, inkjet printing method and printed matter
US5190386A (en) * 1992-01-28 1993-03-02 Eudy James R Printer with edge strip trimmer
US5463629A (en) * 1992-07-13 1995-10-31 Ko; Cheng-Hsu Dynamic channel allocation method and system for integrated services digital network
EP0600626A1 (en) * 1992-11-13 1994-06-08 Cyrix Corporation Coherency for write-back cache in a system designed for write-through cache
JP2819982B2 (en) * 1993-03-18 1998-11-05 株式会社日立製作所 Multiprocessor system with cache match guarantee function that can specify range
JP3183993B2 (en) * 1993-03-31 2001-07-09 株式会社東芝 Disk control system
US5623644A (en) * 1994-08-25 1997-04-22 Intel Corporation Point-to-point phase-tolerant communication
US5819296A (en) * 1996-10-31 1998-10-06 Veritas Software Corporation Method and apparatus for moving large numbers of data files between computer systems using import and export processes employing a directory of file handles
US6636944B1 (en) * 1997-04-24 2003-10-21 International Business Machines Corporation Associative cache and method for replacing data entries having an IO state
US6189043B1 (en) * 1997-06-09 2001-02-13 At&T Corp Dynamic cache replication in a internet environment through routers and servers utilizing a reverse tree generation
US6092155A (en) * 1997-07-10 2000-07-18 International Business Machines Corporation Cache coherent network adapter for scalable shared memory processing systems
US6085276A (en) * 1997-10-24 2000-07-04 Compaq Computers Corporation Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies
US6009488A (en) * 1997-11-07 1999-12-28 Microlinc, Llc Computer having packet-based interconnect channel
US6460119B1 (en) * 1997-12-29 2002-10-01 Intel Corporation Snoop blocking for cache coherency
US6341337B1 (en) * 1998-01-30 2002-01-22 Sun Microsystems, Inc. Apparatus and method for implementing a snoop bus protocol without snoop-in and snoop-out logic
US6067611A (en) * 1998-06-30 2000-05-23 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that buffers potential third node transactions to decrease communication latency
US6430657B1 (en) * 1998-10-12 2002-08-06 Institute For The Development Of Emerging Architecture L.L.C. Computer system that provides atomicity by using a tlb to indicate whether an exportable instruction should be executed using cache coherency or by exporting the exportable instruction, and emulates instructions specifying a bus lock
US6275907B1 (en) * 1998-11-02 2001-08-14 International Business Machines Corporation Reservation management in a non-uniform memory access (NUMA) data processing system
US6477535B1 (en) * 1998-11-25 2002-11-05 Computer Associates Think Inc. Method and apparatus for concurrent DBMS table operations
US6338122B1 (en) * 1998-12-15 2002-01-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node
US6275905B1 (en) * 1998-12-21 2001-08-14 Advanced Micro Devices, Inc. Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system
US6370621B1 (en) * 1998-12-21 2002-04-09 Advanced Micro Devices, Inc. Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation
US6263409B1 (en) * 1998-12-22 2001-07-17 Unisys Corporation Data processing system and method for substituting one type of request for another for increased performance when processing back-to-back requests of certain types
US6275995B1 (en) * 1999-02-26 2001-08-21 Sweports Limited Hand covering with reversible cleaning membrane
JP4363539B2 (en) * 1999-06-04 2009-11-11 諏訪熱工業株式会社 Ball for ballpoint pen
US6442597B1 (en) * 1999-07-08 2002-08-27 International Business Machines Corporation Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory
US6484220B1 (en) * 1999-08-26 2002-11-19 International Business Machines Corporation Transfer of data between processors in a multi-processor system
US6457100B1 (en) * 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
US6405289B1 (en) * 1999-11-09 2002-06-11 International Business Machines Corporation Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response
JP3959914B2 (en) * 1999-12-24 2007-08-15 株式会社日立製作所 Main memory shared parallel computer and node controller used therefor
US6493809B1 (en) * 2000-01-28 2002-12-10 International Business Machines Corporation Maintaining order of write operations in a multiprocessor for memory consistency
US6922755B1 (en) * 2000-02-18 2005-07-26 International Business Machines Corporation Directory tree multinode computer system
US6769017B1 (en) * 2000-03-13 2004-07-27 Hewlett-Packard Development Company, L.P. Apparatus for and method of memory-affinity process scheduling in CC-NUMA systems
US7062541B1 (en) * 2000-04-27 2006-06-13 International Business Machines Corporation System and method for transferring related data objects in a distributed data storage environment
US6640287B2 (en) * 2000-06-10 2003-10-28 Hewlett-Packard Development Company, L.P. Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests
US6795900B1 (en) * 2000-07-20 2004-09-21 Silicon Graphics, Inc. Method and system for storing data at input/output (I/O) interfaces for a multiprocessor system
US6760728B1 (en) * 2000-09-27 2004-07-06 Palmsource, Inc. Method and apparatus for importing and exporting directory and calendar information to and from personal information management applications
US6594733B1 (en) * 2000-09-27 2003-07-15 John T. Cardente Cache based vector coherency methods and mechanisms for tracking and managing data use in a multiprocessor system
US6631449B1 (en) * 2000-10-05 2003-10-07 Veritas Operating Corporation Dynamic distributed data system and method
DE10052443A1 (en) * 2000-10-23 2002-05-08 Boehringer Werkzeugmaschinen Combination machine
US6826591B2 (en) * 2000-12-15 2004-11-30 International Business Machines Corporation Flexible result data structure and multi-node logging for a multi-node application system
US6571322B2 (en) * 2000-12-28 2003-05-27 International Business Machines Corporation Multiprocessor computer system with sectored cache line mechanism for cache intervention
US6615319B2 (en) * 2000-12-29 2003-09-02 Intel Corporation Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture
US6842830B2 (en) * 2001-03-31 2005-01-11 Intel Corporation Mechanism for handling explicit writeback in a cache coherent multi-node architecture
US6877026B2 (en) * 2001-06-08 2005-04-05 Sun Microsystems, Inc. Bulk import in a directory server
US6901485B2 (en) * 2001-06-21 2005-05-31 International Business Machines Corporation Memory directory management in a multi-node computer system
US6691192B2 (en) * 2001-08-24 2004-02-10 Intel Corporation Enhanced general input/output architecture and related methods for establishing virtual channels therein
US20030074430A1 (en) * 2001-10-05 2003-04-17 Gieseke Eric James Object oriented provisioning server object model
US6785774B2 (en) * 2001-10-16 2004-08-31 International Business Machines Corporation High performance symmetric multiprocessing systems via super-coherent data mechanisms
JP2005519391A (en) * 2002-02-28 2005-06-30 シリコン、グラフィクス、インコーポレイテッド Method and system for cache coherence in a DSM multiprocessor system without increasing shared vectors
US7269709B2 (en) * 2002-05-15 2007-09-11 Broadcom Corporation Memory controller configurable to allow bandwidth/latency tradeoff
US6944719B2 (en) * 2002-05-15 2005-09-13 Broadcom Corp. Scalable cache coherent distributed shared memory processing system
US7209976B2 (en) * 2002-07-16 2007-04-24 Jeremy Benjamin Protocol communication and transit packet forwarding routed between multiple virtual routers within a single physical router
US7051163B2 (en) * 2002-10-03 2006-05-23 Hewlett-Packard Development Company, L.P. Directory structure permitting efficient write-backs in a shared memory computer system
US6934814B2 (en) * 2002-11-05 2005-08-23 Newisys, Inc. Cache coherence directory eviction mechanisms in multiprocessor systems which maintain transaction ordering
US7111128B2 (en) * 2002-12-19 2006-09-19 Intel Corporation Hierarchical virtual model of a cache hierarchy in a multiprocessor system
JP3944449B2 (en) * 2002-12-19 2007-07-11 株式会社日立製作所 Computer system, magnetic disk device, and disk cache control method
US6954829B2 (en) * 2002-12-19 2005-10-11 Intel Corporation Non-speculative distributed conflict resolution for a cache coherency protocol
US7130969B2 (en) * 2002-12-19 2006-10-31 Intel Corporation Hierarchical directories for cache coherency in a multiprocessor system
US7818391B2 (en) * 2004-01-20 2010-10-19 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration
US8145847B2 (en) * 2004-01-20 2012-03-27 Hewlett-Packard Development Company, L.P. Cache coherency protocol with ordering points
US7533134B2 (en) 2004-04-01 2009-05-12 Microsoft Corporation Systems and methods for the propagation of conflict resolution to enforce item convergence (i.e., data convergence)

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020129211A1 (en) * 2000-12-30 2002-09-12 Arimilli Ravi Kumar Data processing system and method for resolving a conflict between requests to modify a shared cache line

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
AZIMI M ET AL: "Scalability port: a coherent interface for shared memory multiprocessors", HIGH PERFORMANCE INTERCONNECTS, 2002. PROCEEDINGS. 10TH SYMPOSIUM ON 21-23 AUGUST 2002, PISCATAWAY, NJ, USA,IEEE, 21 August 2002 (2002-08-21), pages 65 - 70, XP010606264, ISBN: 0-7695-1650-5 *
ENDER BILIR E ET AL: "MULTICAST SNOOPING: A NEW COHERENCE METHOD USING A MULTICAST ADDRESS NETWORK", COMPUTER ARCHITECTURE NEWS, ACM, NEW YORK, NY, US, vol. 27, no. 2, May 1999 (1999-05-01), pages 294 - 304, XP000975516, ISSN: 0163-5964 *
LILJA D J: "CACHE COHERENCE IN LARGE-SCALE SHARED-MEMORY MULTIPROCESSORS: ISSUES AND COMPARISONS", ACM COMPUTING SURVEYS, NEW YORK, NY, US, vol. 25, no. 3, September 1993 (1993-09-01), pages 303 - 338, XP008008665, ISSN: 0360-0300 *
RAJWAR R ET AL: "Improving the throughput of synchronization by insertion of delays", 8 January 2000, HIGH-PERFORMANCE COMPUTER ARCHITECTURE, 2000. HPCA-6. PROCEEDINGS. SIXTH INTERNATIONAL SYMPOSIUM ON TOULUSE, FRANCE 8-12 JAN. 2000, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, PAGE(S) 168-179, ISBN: 0-7695-0550-3, XP010371897 *

Also Published As

Publication number Publication date
KR20050086922A (en) 2005-08-30
JP4261487B2 (en) 2009-04-30
JP2006516058A (en) 2006-06-15
DE10393919T5 (en) 2006-01-12
KR100841484B1 (en) 2008-06-25
CN100468365C (en) 2009-03-11
WO2004061677A2 (en) 2004-07-22
US8171095B2 (en) 2012-05-01
AU2003295949A1 (en) 2004-07-29
US20040122966A1 (en) 2004-06-24
CN1849592A (en) 2006-10-18
DE10393919B4 (en) 2019-10-10
AU2003295949A8 (en) 2004-07-29
US20110161451A1 (en) 2011-06-30
US7917646B2 (en) 2011-03-29

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