WO2004068546A3 - Tunnel device level shift circuit - Google Patents

Tunnel device level shift circuit Download PDF

Info

Publication number
WO2004068546A3
WO2004068546A3 PCT/US2004/001811 US2004001811W WO2004068546A3 WO 2004068546 A3 WO2004068546 A3 WO 2004068546A3 US 2004001811 W US2004001811 W US 2004001811W WO 2004068546 A3 WO2004068546 A3 WO 2004068546A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
circuit
tunnel
level shift
tunnel device
Prior art date
Application number
PCT/US2004/001811
Other languages
French (fr)
Other versions
WO2004068546A2 (en
Inventor
William Owen
Original Assignee
Xicor Inc
William Owen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xicor Inc, William Owen filed Critical Xicor Inc
Publication of WO2004068546A2 publication Critical patent/WO2004068546A2/en
Publication of WO2004068546A3 publication Critical patent/WO2004068546A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates

Abstract

A floating gate circuit having a level shift circuit is disclosed. The floating gate circuit includes: a floating gate; a first and second tunnel device formed respectively between a first and second tunnel electrode; a first circuit coupled to the floating gate for generating an output voltage at an output terminal; a level shift circuit having a third tunnel device coupled between the output terminal and the first tunnel electrode; and a second circuit for causing a first current to flow through the first and second tunnel devices and for causing a second current to flow through the third tunnel device. The floating gate circuit then settles to a steady state condition during the set mode such that the first and second currents are approximately equal and the floating gate voltage and the output voltage are approximately equal.
PCT/US2004/001811 2003-01-28 2004-01-23 Tunnel device level shift circuit WO2004068546A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/353,621 US6914812B2 (en) 2003-01-28 2003-01-28 Tunnel device level shift circuit
US10/353,621 2003-01-28

Publications (2)

Publication Number Publication Date
WO2004068546A2 WO2004068546A2 (en) 2004-08-12
WO2004068546A3 true WO2004068546A3 (en) 2005-06-30

Family

ID=32736217

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/001811 WO2004068546A2 (en) 2003-01-28 2004-01-23 Tunnel device level shift circuit

Country Status (2)

Country Link
US (1) US6914812B2 (en)
WO (1) WO2004068546A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7113017B2 (en) * 2004-07-01 2006-09-26 Intersil Americas Inc. Floating gate analog voltage level shift circuit and method for producing a voltage reference that operates on a low supply voltage
TWI462496B (en) * 2007-10-03 2014-11-21 Airoha Tech Corp The biasing circuit of the wireless transceiver
US7838342B2 (en) * 2008-06-06 2010-11-23 Spansion Llc Memory device and method
US7830716B2 (en) * 2008-06-06 2010-11-09 Spansion Llc Non-volatile memory string module with buffer and method
US7983089B2 (en) * 2008-06-06 2011-07-19 Spansion Llc Sense amplifier with capacitance-coupled differential sense amplifier
WO2011055660A1 (en) 2009-11-06 2011-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8184489B2 (en) 2010-05-05 2012-05-22 Micron Technology, Inc. Level shifting circuit
ITUA20164741A1 (en) * 2016-06-29 2017-12-29 St Microelectronics Srl READING CIRCUIT OF A CIRCUIT STAGE AT A LONG CONSTANT TIME AND ITS READING METHOD

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629891A (en) * 1991-05-09 1997-05-13 Synaptics, Incorporated Writable analog reference voltage storage device
US5898613A (en) * 1996-07-24 1999-04-27 California Institute Of Technology pMOS analog EEPROM cell

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059920A (en) * 1988-12-09 1991-10-22 Synaptics, Incorporated CMOS amplifier with offset adaptation
US4935702A (en) * 1988-12-09 1990-06-19 Synaptics, Inc. Subthreshold CMOS amplifier with offset adaptation
US4980859A (en) * 1989-04-07 1990-12-25 Xicor, Inc. NOVRAM cell using two differential decouplable nonvolatile memory elements
US4953928A (en) * 1989-06-09 1990-09-04 Synaptics Inc. MOS device for long-term learning
US5095284A (en) * 1990-09-10 1992-03-10 Synaptics, Incorporated Subthreshold CMOS amplifier with wide input voltage range
US5166562A (en) * 1991-05-09 1992-11-24 Synaptics, Incorporated Writable analog reference voltage storage device
US5875126A (en) * 1995-09-29 1999-02-23 California Institute Of Technology Autozeroing floating gate amplifier
US6297689B1 (en) * 1999-02-03 2001-10-02 National Semiconductor Corporation Low temperature coefficient low power programmable CMOS voltage reference

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629891A (en) * 1991-05-09 1997-05-13 Synaptics, Incorporated Writable analog reference voltage storage device
US5898613A (en) * 1996-07-24 1999-04-27 California Institute Of Technology pMOS analog EEPROM cell

Also Published As

Publication number Publication date
US20040145945A1 (en) 2004-07-29
WO2004068546A2 (en) 2004-08-12
US6914812B2 (en) 2005-07-05

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