WO2004068551A3 - Patterning layers comprised of spin-on ceramic films - Google Patents

Patterning layers comprised of spin-on ceramic films Download PDF

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Publication number
WO2004068551A3
WO2004068551A3 PCT/US2004/002126 US2004002126W WO2004068551A3 WO 2004068551 A3 WO2004068551 A3 WO 2004068551A3 US 2004002126 W US2004002126 W US 2004002126W WO 2004068551 A3 WO2004068551 A3 WO 2004068551A3
Authority
WO
WIPO (PCT)
Prior art keywords
ceramic layer
spin
underlying substrate
layers comprised
ceramic films
Prior art date
Application number
PCT/US2004/002126
Other languages
French (fr)
Other versions
WO2004068551A2 (en
Inventor
Stephen M Gates
Jeffrey C Hedrick
Elbert E Huang
Dirk Pfeiffer
Original Assignee
Ibm
Stephen M Gates
Jeffrey C Hedrick
Elbert E Huang
Dirk Pfeiffer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Stephen M Gates, Jeffrey C Hedrick, Elbert E Huang, Dirk Pfeiffer filed Critical Ibm
Priority to EP04705307A priority Critical patent/EP1595276A4/en
Priority to KR1020057012386A priority patent/KR100656225B1/en
Priority to JP2006503032A priority patent/JP2006517742A/en
Priority to CNB2004800028675A priority patent/CN100552542C/en
Publication of WO2004068551A2 publication Critical patent/WO2004068551A2/en
Publication of WO2004068551A3 publication Critical patent/WO2004068551A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3125—Layers comprising organo-silicon compounds layers comprising silazane compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S430/00—Radiation imagery chemistry: process, composition, or product thereof
    • Y10S430/146—Laser beam
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31652—Of asbestos
    • Y10T428/31663—As siloxane, silicone or silane

Abstract

The present invention comprises a method for forming a hardmask including the steps of depositing a polymeric preceramic precursor film atop a substrate; converting the polymeric preceramic precursor film into at least one ceramic layer, where the ceramic layer has a composition of SivNWCXOyHZ where 0.1≤ v≤ 0.9, 0≤w< 0.5, 0.05≤ x≤ 0.9, 0≤ y≤ 0.5, 0.05≤ z≤ 0.8 for v+w+x+y+z=l; forming a patterned photoresist atop the ceramic layer; patterning the ceramic layer to expose regions of the underlying substrate, where a remaining region of the underlying substrate is protected by the patterned ceramic layer; and etching the exposed region of the underlying substrate. Another aspect of the present invention is a buried etch stop layer having a composition of SivNWCXOyHZ where 0.05<v<0.8, 0<w<0.9, 0.05<x<0.8, 0<y<0.8, 0.05<z<0.8 for v+w+x+y+z=1.
PCT/US2004/002126 2003-01-29 2004-01-26 Patterning layers comprised of spin-on ceramic films WO2004068551A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP04705307A EP1595276A4 (en) 2003-01-29 2004-01-26 Patterning layers comprised of spin-on ceramic films
KR1020057012386A KR100656225B1 (en) 2003-01-29 2004-01-26 Patterning layers comprised of spin-on ceramic films
JP2006503032A JP2006517742A (en) 2003-01-29 2004-01-26 Patterning layer made of spin-on ceramic film
CNB2004800028675A CN100552542C (en) 2003-01-29 2004-01-26 The patterned layer of forming by the ceramic membrane in the spin coating

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US44336103P 2003-01-29 2003-01-29
US60/443,361 2003-01-29
US10/627,790 2003-07-25
US10/627,790 US6803660B1 (en) 2003-01-29 2003-07-25 Patterning layers comprised of spin-on ceramic films

Publications (2)

Publication Number Publication Date
WO2004068551A2 WO2004068551A2 (en) 2004-08-12
WO2004068551A3 true WO2004068551A3 (en) 2005-05-26

Family

ID=32829823

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/002126 WO2004068551A2 (en) 2003-01-29 2004-01-26 Patterning layers comprised of spin-on ceramic films

Country Status (7)

Country Link
US (2) US6803660B1 (en)
EP (1) EP1595276A4 (en)
JP (1) JP2006517742A (en)
KR (1) KR100656225B1 (en)
CN (1) CN100552542C (en)
TW (1) TWI262575B (en)
WO (1) WO2004068551A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6940173B2 (en) * 2003-01-29 2005-09-06 International Business Machines Corporation Interconnect structures incorporating low-k dielectric barrier films
US7060637B2 (en) * 2003-05-12 2006-06-13 Micron Technology, Inc. Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials
US6947311B2 (en) * 2003-06-10 2005-09-20 University Of Basel Two-dimensional structural transition controlled by an electric field, memory storage device thereof, and method of making a memory storage device
DE602004021085D1 (en) * 2004-03-11 2009-06-25 Corning Inc Ceramic composition with a silsesquioxane polymer
JP4878434B2 (en) * 2004-09-22 2012-02-15 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
TW200736855A (en) * 2006-03-22 2007-10-01 Quanta Display Inc Method of fabricating photoresist thinner
US8288271B2 (en) * 2009-11-02 2012-10-16 International Business Machines Corporation Method for reworking antireflective coating over semiconductor substrate
WO2011136403A1 (en) * 2010-04-28 2011-11-03 주식회사 웨이브닉스이에스피 Method for manufacturing a metal-based package having a via structure
US20170358445A1 (en) 2016-06-13 2017-12-14 Gvd Corporation Methods for plasma depositing polymers comprising cyclic siloxanes and related compositions and articles
US11679412B2 (en) 2016-06-13 2023-06-20 Gvd Corporation Methods for plasma depositing polymers comprising cyclic siloxanes and related compositions and articles
CN108878287A (en) * 2018-06-29 2018-11-23 苏州研材微纳科技有限公司 The processing passivation protection method of silicon substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6699810B2 (en) * 2001-08-14 2004-03-02 Thor Technologies, Inc. Method of producing hybrid metal/ceramic composites

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
EP0379277A3 (en) * 1989-01-17 1991-05-29 Teijin Limited Napthtalocyanine based compound and optical recording medium containing the same
EP1146555B1 (en) * 1999-03-09 2007-12-12 Tokyo Electron Limited Production method for a semiconductor device
US6136707A (en) * 1999-10-02 2000-10-24 Cohen; Uri Seed layers for interconnects and methods for fabricating such seed layers
US6489030B1 (en) 2000-04-14 2002-12-03 Honeywell International, Inc. Low dielectric constant films used as copper diffusion barrier
JP2002012761A (en) * 2000-04-28 2002-01-15 Toray Ind Inc Heat-resistant resin composition
US6656532B2 (en) * 2001-05-17 2003-12-02 Honeywell International Inc. Layered hard mask and dielectric materials and methods therefor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6699810B2 (en) * 2001-08-14 2004-03-02 Thor Technologies, Inc. Method of producing hybrid metal/ceramic composites

Also Published As

Publication number Publication date
KR100656225B1 (en) 2006-12-13
CN1742231A (en) 2006-03-01
KR20050102620A (en) 2005-10-26
EP1595276A4 (en) 2012-03-28
TW200428585A (en) 2004-12-16
CN100552542C (en) 2009-10-21
US6803660B1 (en) 2004-10-12
EP1595276A2 (en) 2005-11-16
WO2004068551A2 (en) 2004-08-12
TWI262575B (en) 2006-09-21
US20050008959A1 (en) 2005-01-13
US6929982B2 (en) 2005-08-16
JP2006517742A (en) 2006-07-27

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