WO2004070406A1 - 検出装置、検出方法、及びプログラム - Google Patents
検出装置、検出方法、及びプログラム Download PDFInfo
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- WO2004070406A1 WO2004070406A1 PCT/JP2004/001106 JP2004001106W WO2004070406A1 WO 2004070406 A1 WO2004070406 A1 WO 2004070406A1 JP 2004001106 W JP2004001106 W JP 2004001106W WO 2004070406 A1 WO2004070406 A1 WO 2004070406A1
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- change point
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- timing
- unit
- output signal
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31932—Comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31922—Timing generation or clock distribution
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31924—Voltage or current aspects, e.g. driver, receiver
Definitions
- the present invention relates to a detection device that detects a change point of a signal level of a signal under measurement.
- This application is also related to the following Japanese patent application. For those designated countries that are permitted to be incorporated by reference to the literature, the contents described in the following application shall be incorporated into this application by reference, and shall be part of the description of this application.
- test of an electronic device such as a semiconductor circuit
- an output signal output by the electronic device is measured, and a force of the electronic device outputting an output signal as expected is measured.
- the test device that tests the electronic device measures how and when the value of the output signal changes.
- the test equipment performs a measurement called an edge strobe to measure the change point of the output signal value.
- the edge strobe is a measurement in which strobes whose phases are sequentially shifted are generated, and the signal level of an output signal at the timing of the generated strobe is sequentially detected (for example, see Patent Document 1).
- the signal level of the output signal at a plurality of timings having different phases is detected, the change point of the value of the output signal is detected, and the timing at which the signal level changes and how the signal level changes are detected. Measuring.
- the detection of the signal level in the edge strobe described above is performed by a level comparator which receives the output signal and uses the strobe as an operation clock.
- the level comparator compares the signal level of the output signal at the timing indicated by the strobe with a predetermined threshold, and detects whether the signal level is H level or L level.
- Japanese Patent Application Laid-Open Publication No. 2000-35056 (Page 7, FIG. 15-16)
- the conventional test apparatus uses the method described above to generate the rising edge and the falling edge of the output signal. Edge timing is detected.
- an error may occur between the two measurement results. For example, even when a rising edge and a falling edge whose values change at the same timing are measured, the measurement results of the two may not be the same.
- the above-mentioned error may be caused by the hysteresis characteristic of the level comparator used for detecting the signal level of the output signal.
- the threshold value used by the level comparator to compare the output signal to detect the H level is different from the threshold value used to compare the output signal to detect the L level, the rising edge of the rising edge that changes from the L level to the H level is different.
- a measurement error occurs between the two.
- Another possible cause is a difference in propagation delay time between a rising edge and a falling edge when an output signal passes through a logic circuit, a buffer, or the like in the test apparatus.
- the measurement error described above occurs due to various causes. To test devices that operate at higher speeds, it is desirable to reduce such measurement errors. However, even if the circuit characteristics in the test equipment are adjusted in order to reduce such measurement errors, it is difficult to sufficiently reduce the measurement errors, and such a correction circuit must be created. It is difficult to do. Also, it is not desirable to consider design costs.
- an object of the present invention is to provide a detection device, a detection method, and a program that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention. Disclosure of the invention
- a detection device for detecting a change point at which a signal level of an output signal output from an electronic device changes, comprising: receiving an output signal; A change point detecting section to detect, a timing comparing section to detect a signal level of the output signal before or after the changing point in the output signal, and a change inspection based on a signal level of the output signal detected by the timing comparing section. And a correction unit that corrects the timing of the change point detected by the output unit.
- the timing comparing section may detect the signal level of the output signal at a timing separated from the change point by a predetermined time.
- the image processing apparatus further includes an edge type determination unit that determines whether the change point indicates a rising edge or a falling edge based on the signal level detected by the timing comparison unit. Based on the determination result, the timing of the change point detected by the change point detection unit may be corrected.
- the image processing apparatus further includes a correction value storage unit that stores a plurality of correction values corresponding to each of the rising edge and the falling edge, and the correction unit uses the correction value according to the determination result in the edge type determination unit to determine a change point.
- the timing may be corrected.
- the apparatus further includes a correction value storage unit that stores a predetermined correction value, and the correction unit stores the correction value storage unit when the determination result in the edge type determination unit is a predetermined result. The timing of the change point may be corrected using the corrected value.
- a timing comparing unit that has a plurality of cascaded variable delay circuits that sequentially delays and outputs a strobe signal, and further includes a multi-strobe generating unit that generates a plurality of strobes indicating a plurality of timings having different phases; Has a plurality of comparators provided corresponding to the variable delay circuits, for detecting the signal level of the output signal at the timing of the strobe signal output from the corresponding variable delay circuit, and the plurality of strobes indicated by the plurality of strobes.
- the output unit detects a change point when two signal levels at adjacent timings are different from each other at a plurality of signal levels at a plurality of timings, and the edge type determination unit detects the plurality of signal levels detected by the timing comparison unit. Among them, the signal level at the timing before or after the change point may be received, and whether the change point indicates a rising edge or a falling edge may be determined based on the received signal level.
- the change point detection unit receives two signal levels at adjacent timings, and outputs H logic when two corresponding signal levels are different, and outputs the H logic to the output results of the plurality of exclusive OR circuits. And an encoder for generating an encode signal indicating the timing of the change point based on the change.
- the correction unit receives the encode signal and outputs a correction signal obtained by adding a correction value to the encode signal.
- the correction unit receives the encode signal and the correction signal, and, based on the determination result in the edge type determination unit, encodes the encoded signal.
- a selector may be provided for outputting one of the correction signals as the timing of the change point.
- the edge type determination unit further determines whether or not the change point detection unit has detected a change point based on the encode signal, and the selection unit determines whether or not the change point detection unit has detected the change point. Further, either the encode signal or the correction signal may be selected and output.
- the correction unit stores the timing of the change point detected by the change point detection unit and the type of edge determined by the edge type determination unit in association with each other, based on the fail memory and the type of edge stored by the fail memory. Correction means for correcting the timing of the corresponding change point.
- a detection method for detecting a change point at which a signal level of an output signal output by an electronic device changes the change point receiving step including receiving an output signal and detecting the change point. And a timing comparing step of detecting a signal level of the output signal before or after the change point in the output signal, and detecting the signal level of the output signal in the change point detecting step based on the signal level of the output signal detected in the timing comparing step. Correcting the timing of the change point.
- a program for causing a detection device to detect a change point at which a signal level of an output signal output from an electronic device changes, the program receiving an output signal of the detection device, and detecting the change point.
- a change point detecting section that detects a signal level of the output signal before or after the change point in the output signal; and a change point detecting section that detects a change point based on the signal level of the output signal detected by the timing comparing section.
- a program is provided which functions as a correction unit for correcting the timing of a change point detected by the unit.
- FIG. 1 is a diagram illustrating an example of a configuration of a detection device 100 according to an embodiment of the present invention.
- FIG. 2 is a diagram showing an example of a data configuration in the fail memory 50.
- FIG. 3 is a diagram illustrating an example of a waveform of an output signal output by the electronic device.
- FIG. 4 is a diagram showing an example of the operation of the detection device 100 described in FIG.
- FIG. 5 is a diagram illustrating an example of a configuration of a computer 200 that controls the detection device 100.
- FIG. 1 shows an example of a configuration of a detection device 100 according to an embodiment of the present invention.
- the detection device 100 is a device that outputs an output signal from an electronic device that is a device under test (DUT). This is a device that detects a change point where the signal level changes and corrects the timing of the detected change point.
- DUT device under test
- the detection device 100 includes a plurality of multi-strobe circuits (10a, 10b), a plurality of buffer units (30a, 30b), a plurality of change point detection units (34a, 34b), and a plurality of stored calibration values. (36a, 36b), a plurality of correction units (52a, 52b), a plurality of edge type determination units (54a, 54b), a selection circuit 48, and a fail memory 50.
- the multi-stroke circuit 10a receives the output signal output from the electronic device via the external level comparator 60a.
- the level comparator 60a compares the output signal with a given threshold value ViH, and converts the output signal into a binary signal having an H level and an L level.
- the multi-strobe circuit 10a has a multi-strobe generating unit 14, a timing comparing unit 12, and a plurality of cascaded delay circuits (16-1 to 16-n).
- the multi-strobe generating section 14 has a plurality of cascaded variable delay circuits (20-1 to 20-n) and generates a plurality of strobes indicating a plurality of timings having different phases.
- Each of the variable delay circuits (20-l to 20-n) receives a strobe signal (STRBH) from an external or preceding variable delay circuit, delays the output sequentially, and outputs a plurality of strobe signals having different phases. To generate a multi-strobe.
- STRBH strobe signal
- the timing comparing section 12 has a plurality of comparators (18_0 to 18-n), and detects signal levels of output signals at a plurality of timings using the multi-strobe generated by the multi-strobe generating section 14.
- the comparators (18-1 to 18-n) are provided corresponding to the variable delay circuits (20-1 to 20-n), and output by the corresponding variable delay circuits (20-1 to 20-n). The signal level of the output signal at the timing of the strobe signal is detected. Further, the comparator 18-0 detects the signal level of the output signal at the timing indicated by the strobe signal provided to the multi-strobe generating unit 14.
- a plurality of delay circuits (16-1 to 16-n) are provided corresponding to the comparators (18- :! to 18-n).
- Multiple delay circuits (16-l to 16-n) receive the output signal SH. The signals are sequentially delayed and supplied to the comparators (18-l to 18-n).
- Each of the comparators (18-1 to 18-n) detects the signal level of the received output signal according to the strobe signal generated by the corresponding variable delay circuit (16-1 to 16-n). Put out.
- the delay amount in each of the delay circuits (16-l to 16-n) is preferably set to a delay amount substantially equal to the offset delay amount in the variable delay circuit (20-l to 20-n).
- the buffer section 30a has a plurality of first-in first-out circuits (32-0 to 32-n) provided corresponding to the plurality of comparators (18-0 to 18-n).
- a first-in first-out circuit 32-n is provided corresponding to the comparator 18-0
- a first-in first-out circuit 32-0 is provided corresponding to the comparator 18-n.
- the plurality of first-in first-out circuits (32-0 to 32-n) receive the signal levels of the output signals detected by the corresponding comparators (18-0 to 18-n), and refer to the received signal levels respectively. Output sequentially in synchronization with the clock (REF CLK).
- the change point detecting section 34a detects a change point of the output signal based on the signal level of the output signal received from the buffer section 30a.
- the transition point means that the signal level of the output signal changes from a signal level below a predetermined threshold to a signal level above a predetermined threshold, or from a signal level above a predetermined threshold to a signal level below a predetermined threshold.
- Point The change point detection unit 34a detects a change when two signal levels at adjacent timings are different at a plurality of signal levels at a plurality of timings detected by the comparators (18-0 to: 18-n). Find points.
- the change point detection unit 34a receives two signal levels at adjacent timings, and outputs H logic when two corresponding signal levels are different, and outputs a plurality of exclusive OR circuits (56-0 to An encoder 3 that generates an encode signal indicating the timing of a transition point based on the output result of 56- (nD) and a plurality of exclusive OR circuits (56-0 to 56_ (n-1)) 8a.
- the encoder 38a converts an n-bit signal output from a plurality of exclusive OR circuits (5 6-0 to 5 6- (n-D)) into a binary signal.
- the n-bit signal output by the exclusive-OR circuit indicates the timing of the transition point depending on the position of the bit indicating the H logic.
- the n-bit signal is converted into a signal representing the timing of the change point by a numerical value.
- the edge type determination unit 54a determines whether the change point indicates a rising edge or a falling edge based on the signal level detected by the timing comparison unit 12.
- the edge detector 54 a receives the signal level received by the first-in first-out circuit 32-n as an edge determination bit, and determines an edge type at a change point based on the edge determination bit.
- the FIFO circuit 32-n receives the signal level detected by the comparator 18-0, that is, the signal level before the transition point. If the edge determination bit is H level ⁇ , the edge type determination unit 54a determines that the transition point is a falling edge, and if the edge determination bit is L level, the transition point is a rising edge. Judge that there is.
- the edge type determination unit 54a may use the signal level detected by the other comparator 18 as the edge determination bit.
- the signal level detected by the comparator 18-0 that is, the signal level after the change point may be used as an edge determination bit. Even in this case, it can be similarly determined whether the changing point is a rising edge or a falling edge.
- the correction unit 52a calculates the timing of the change point detected by the change point detection unit 34a based on the result of determining whether the change point is the rising edge or the falling edge in the edge type determination unit 54a. Is corrected. That is, the correction unit 52 a corrects the timing of the change point detected by the change point detection unit 34 a based on the signal level before or after the change point detected by the timing comparison unit 12.
- the correction value storage unit 36a stores a correction value for the correction unit 52a to correct the timing of the change point.
- the correction value storage 36 a stores a predetermined correction value. Alternatively, a plurality of correction values corresponding to each of the rising edge and the falling edge may be stored.
- the correction value storage unit 36 a stores the correction value of ⁇
- the correction unit 52 a is provided with a correction value storage unit when the determination result in the edge type determination unit 54 a is a predetermined result.
- the timing of the change point is corrected using the correction value stored in 36a.
- the correction value storage unit 36a stores a plurality of correction values
- the correction unit 52a corrects the timing of the change point using the correction value according to the judgment result in the edge type judgment unit 54a. You. In this example, a case where the correction value storage unit 36a stores one correction value will be described.
- the correction unit 52 a receives the encode signal, and outputs a correction signal obtained by adding the correction value stored in the correction value storage unit 36 a to the encode signal, and an add unit 40 a.
- a selection unit 44a that receives the signal and the correction signal, and outputs either the encode signal or the correction signal as the timing of the change point according to the determination result in the edge type determination unit 54a.
- the edge type determination unit 54a detects a falling edge
- the selection unit 44a outputs a correction signal to which the correction value is added in the addition unit 40a, and determines the edge type.
- the section 54a detects a rising edge, it outputs an encode signal. This makes it possible to compensate for a relative error between the timing of the rising edge and the timing of the falling edge.
- the edge type determination unit 54a further determines whether or not the change point detection unit 34a has detected a change point based on the encoded signal. 4a may select and output either the encode signal or the correction signal based on whether or not a change point has been detected.
- the edge type determination unit 54a includes a detection unit 42a and an AND circuit 46a.
- the encoder 38a If the change point is not detected by the change point detection section 34a, the encoder 38a outputs a signal indicating zero.
- the detection unit 42a receives the encoded signal, determines whether or not the force of the encoded signal indicates zero, and determines whether or not the change point detection unit 34a has detected a change point.
- the AND circuit 46a causes the selector 44a to select a correction signal when the encode signal is not zero and the change point is a falling edge, and the encoder signal is zero. When a certain force or a change point is a rising edge, the selection unit 44a is caused to select an encode signal.
- the correction value storage unit 36a stores the correction value corresponding to the rising edge. In this case, the timing of the change point can be corrected by the same operation.
- the timing comparison section 12 detects the signal level of the output signal at a timing separated by a predetermined time from the change point
- the correction section 52 a detects the signal level at a timing separated by a predetermined time from the change point.
- the timing of the change point may be corrected based on the signal level of the output signal. For example, when an analog output signal is given, the slope of the change point is calculated based on the difference between the timing of the change point and the timing of the detected signal level, and the detected signal level. Based on this, the timing of the change point may be corrected. In this case, even when the waveform of the output signal changes according to the frequency of the output signal, the timing of the change point can be corrected further based on the slope of the waveform.
- the multi-stroop circuit 10b, the buffer section 30b, the change point detection section 34b, the correction value storage section 36b, the edge type determination section 54b, and the correction section 52b are The same or similar functions and functions as the rope circuit 10a, buffer section 30a, change point detection section 34a, correction value storage section 36a, edge type determination section 54a, and correction section 52a It has a configuration.
- the multi-stroop circuit 10b receives the output signal SL via an external level comparator 60b.
- the level comparator 60b receives the output signal of the electronic device, compares the output signal with a given threshold value V i L, converts the output signal into a binary signal of H level and L level, and outputs the binary signal. I do.
- the level comparator 60 b receives a signal having a value substantially equal to the threshold V i H as the threshold V i L, and substantially inverts the output signal output from the level comparator 60 a. Output the output signal.
- the threshold value Vi L and the threshold value Vi H may not be equal.
- the selection circuit 48 determines the timing of the change point output from the correction section 52a and the edge type determination. Select either the judgment result output by the section 54a or the change point timing output by the correction section 52b or the judgment result output by the edge type judgment section 54b, and store them in the fail memory 50. I do.
- the timing for detecting the change point when the change point is a rising edge and the change for detecting the change point when the change point is a falling edge It is possible to easily compensate for a relative error with the point detection timing.
- FIG. 2 shows an example of a data configuration in the fail memory 50.
- the fail memory 50 is used to determine the timing (change code) of the change point output by the correction unit 52a, whether the change point is a rising edge or a falling edge, and whether the change point is the output signal SH or Which of the output signals SL (EXP) is stored in association with it.
- the fail memory 50 may store an encode signal output from the encoder 38 instead of the change point code.
- the detection device 100 corrects the timing of the change point indicated by the encode signal stored in the fail memory 50 based on whether the change point is a deviation of a rising edge or a falling edge. I do.
- the detection device 100 may further include an arithmetic device as a correction unit for performing the correction.
- FIG. 3 shows an example of a waveform of an output signal output by the electronic device.
- the output signal passes through circuits such as a logic circuit and a buffer before being input to the multi-strobe circuit 10.
- the output signal is delayed, but the delay time differs between the rising edge and the falling edge of the output signal.
- the rising edge is delayed by time T, and the falling edge is delayed by ⁇ + ⁇ .
- the detection device 100 described with reference to FIG. 1 can accurately measure the output signal output from the electronic device by correcting such a timing shift due to the edge type.
- the detection timing is This can happen.
- the detection device 100 described with reference to FIG. 1 can also detect such a shift in timing.
- FIG. 4 shows an example of the operation of the detection device 100 described in FIG.
- the detection apparatus 100 first receives an output signal from the electronic device (S300).
- the multi-strobe circuit 10 generates a multi-strobe and detects the signal level of the output signal at a plurality of timings of the multi-strobe (S302).
- the change point detection unit detects a change point based on the signal level (S304).
- the signal level at the timing before or after the change point is detected, and the edge type of the change point is determined (S306).
- the edge type of the change point is determined by using the signal level detected by the comparator 18-n provided at the last stage. judge.
- FIG. 5 shows an example of the configuration of a computer 200 that controls the detection device 100.
- the computer 200 controls the detection device 100 according to a program for causing the detection device 100 to detect a change point at which the signal level of the output signal output by the electronic device changes. That is, the computer 200 stores the program that causes the detection device 100 to function as described with reference to FIGS.
- the computer 200 includes a CPU 700, a ROM 702, a RAM 704, a communication interface 706, a hard disk drive 710, an FD disk drive 712, and a CD-ROM drive 716.
- the CPU 700 operates based on a program stored in the ROM 702, the RAM 704, the hard disk 710, the FD disk 714, and / or the CD-ROM 718.
- the communication interface 706 communicates with the detection device 100 and causes the detection device 100 to function as the detection device 100 described with reference to FIGS.
- a hard disk drive 710 as an example of a storage device stores setting information and a program for operating the CPU 700.
- the ROM 702, the RAM 704, and / or the hard disk drive 7 10 described the detection device 100 in connection with FIGS.
- a program for functioning as the detection device 100 is stored.
- the flexible disk drive 712 reads the program from the flexible disk 714 and provides the program to the CPU 700.
- the CD-ROM drive 7 16 reads the program from the CD-ROM 7 18 and provides it to the CPU 7 00.
- the program may be read directly from the recording medium into the RAM and executed, or may be read into the RAM after being installed in the hard disk drive and executed. Further, the program may be stored on a single recording medium or on a plurality of recording media. Also, the program stored in the recording medium may provide each function in cooperation with the operating system. For example, the program may request the operating system to perform a part or all of the function, and provide the function based on a response from the operating system.
- Recording media for storing programs include flexible disks, CD-ROMs, optical recording media such as DVD and PD, magneto-optical recording media such as MD, tape media, magnetic recording media, IC cards and miniatures.
- a semiconductor memory such as one card can be used.
- a storage device such as a hard disk or a RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a recording medium.
- the computer 200 may have the functions of the fail memory 50 and the correction means described in FIG. 1 and FIG.
- the computer 200 may store the encoded signal output from the encoder 380, and may correct the stored encoded signal according to the type of edge at the change point. In this case, the computer 200 corrects the encode signal by a correction value given in advance.
- the timing of the change point of the output signal of the electronic device can be accurately measured.
Abstract
Description
Claims
Priority Applications (2)
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DE112004000274T DE112004000274T5 (de) | 2003-02-04 | 2004-02-04 | Erfassungsvorrichtung, Erfassungsverfahren und Programm |
US11/191,421 US7640127B2 (en) | 2003-02-04 | 2005-07-28 | Detection apparatus, detection method, and program |
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JP2003026866A JP4444570B2 (ja) | 2003-02-04 | 2003-02-04 | 検出装置、検出方法、及びプログラム |
JP2003-026866 | 2003-02-04 |
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US11/191,421 Continuation US7640127B2 (en) | 2003-02-04 | 2005-07-28 | Detection apparatus, detection method, and program |
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ITTO20060861A1 (it) * | 2006-12-04 | 2008-06-05 | St Microelectronics Srl | Dispositivo sensore dotato di un circuito di rilevamento di eventi singoli o multipli per la generazione di corrispondenti segnali di interruzione |
WO2009025020A1 (ja) | 2007-08-20 | 2009-02-26 | Advantest Corporation | 試験装置、試験方法、および、製造方法 |
JP5119255B2 (ja) * | 2007-08-20 | 2013-01-16 | 株式会社アドバンテスト | 試験装置、試験方法、および、製造方法 |
US8094766B2 (en) * | 2008-07-02 | 2012-01-10 | Teradyne, Inc. | Tracker circuit and method for automated test equipment systems |
US8067943B2 (en) * | 2009-03-24 | 2011-11-29 | Advantest Corporation | Test apparatus, calibration method, program, and recording medium |
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JPH11353352A (ja) | 1998-06-11 | 1999-12-24 | Fujitsu Ltd | Lsiテストデータ検証方法 |
JP4495308B2 (ja) | 2000-06-14 | 2010-07-07 | 株式会社アドバンテスト | 半導体デバイス試験方法・半導体デバイス試験装置 |
TWI238256B (en) * | 2000-01-18 | 2005-08-21 | Advantest Corp | Testing method for semiconductor device and its equipment |
JP2001337141A (ja) | 2000-05-30 | 2001-12-07 | Sharp Corp | 半導体集積回路の外付けテスト回路及びそのテスト方法 |
JP4782271B2 (ja) * | 2000-07-06 | 2011-09-28 | 株式会社アドバンテスト | 半導体デバイス試験方法・半導体デバイス試験装置 |
-
2003
- 2003-02-04 JP JP2003026866A patent/JP4444570B2/ja not_active Expired - Fee Related
-
2004
- 2004-02-04 DE DE112004000274T patent/DE112004000274T5/de not_active Withdrawn
- 2004-02-04 WO PCT/JP2004/001106 patent/WO2004070406A1/ja not_active Application Discontinuation
- 2004-02-04 KR KR1020057013899A patent/KR101037479B1/ko active IP Right Grant
-
2005
- 2005-07-28 US US11/191,421 patent/US7640127B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6333675A (ja) * | 1986-05-08 | 1988-02-13 | ジエンラツド インコ−ポレ−テツド | 高速動作の比較回路 |
JPH02310481A (ja) * | 1989-05-25 | 1990-12-26 | Hitachi Electron Eng Co Ltd | Ic試験装置 |
JPH09304482A (ja) * | 1996-05-21 | 1997-11-28 | Hitachi Ltd | Ic試験装置 |
JPH10332782A (ja) * | 1997-05-30 | 1998-12-18 | Ando Electric Co Ltd | Icテストシステム |
Also Published As
Publication number | Publication date |
---|---|
JP4444570B2 (ja) | 2010-03-31 |
DE112004000274T5 (de) | 2006-01-12 |
JP2004264046A (ja) | 2004-09-24 |
KR20050095632A (ko) | 2005-09-29 |
US7640127B2 (en) | 2009-12-29 |
KR101037479B1 (ko) | 2011-05-26 |
US20050259556A1 (en) | 2005-11-24 |
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