WO2004070987A3 - Analog floating gate voltage sense during dual conduction programming - Google Patents

Analog floating gate voltage sense during dual conduction programming Download PDF

Info

Publication number
WO2004070987A3
WO2004070987A3 PCT/US2004/001697 US2004001697W WO2004070987A3 WO 2004070987 A3 WO2004070987 A3 WO 2004070987A3 US 2004001697 W US2004001697 W US 2004001697W WO 2004070987 A3 WO2004070987 A3 WO 2004070987A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
voltage
causing
gate voltage
voltage sense
Prior art date
Application number
PCT/US2004/001697
Other languages
French (fr)
Other versions
WO2004070987A2 (en
WO2004070987B1 (en
WO2004070987A9 (en
Inventor
William Owen
Original Assignee
Xicor Inc
William Owen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xicor Inc, William Owen filed Critical Xicor Inc
Publication of WO2004070987A2 publication Critical patent/WO2004070987A2/en
Publication of WO2004070987A9 publication Critical patent/WO2004070987A9/en
Publication of WO2004070987A3 publication Critical patent/WO2004070987A3/en
Publication of WO2004070987B1 publication Critical patent/WO2004070987B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates

Abstract

A method for sensing the voltage on a floating gate in a floating gate circuit during a set mode is disclosed. The method includes the steps of: a) causing the floating gate circuit (30) to enter into a set mode, wherein a first predetermined voltage (Vset) is coupled to the gate of a second transistor (T2) in the floating gate circuit; b) causing the voltage on the floating gate to be sensed relative to the first voltage by a first transistor (T1); c) causing an output voltage (Vout) to be generated by the floating gate circuit; and d) causing the voltage on the floating gate to be modified as a function of the output voltage, including modifying the charge level on said floating gate under the control of a first tunnel device (Te) and a second tunnel device (Tp) operating in dual conduction during said set mode, said first tunnel device formed between said floating gate and a first tunnel electrode (Ee) and said second tunnel device formed between said floating gate and a second tunnel electrode (Ep); and e) repeating steps b) through d) until the voltage on the floating gate is approximately equal to the first voltage.
PCT/US2004/001697 2003-01-28 2004-01-21 Analog floating gate voltage sense during dual conduction programming WO2004070987A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/353,404 2003-01-28
US10/353,404 US6815983B2 (en) 2003-01-28 2003-01-28 Analog floating gate voltage sense during dual conduction programming

Publications (4)

Publication Number Publication Date
WO2004070987A2 WO2004070987A2 (en) 2004-08-19
WO2004070987A9 WO2004070987A9 (en) 2004-09-30
WO2004070987A3 true WO2004070987A3 (en) 2005-02-17
WO2004070987B1 WO2004070987B1 (en) 2005-06-16

Family

ID=32736165

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/001697 WO2004070987A2 (en) 2003-01-28 2004-01-21 Analog floating gate voltage sense during dual conduction programming

Country Status (3)

Country Link
US (1) US6815983B2 (en)
CN (1) CN100407576C (en)
WO (1) WO2004070987A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103424601A (en) * 2013-08-21 2013-12-04 矽力杰半导体技术(杭州)有限公司 Voltage detecting circuit

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101795134B (en) * 2010-03-18 2011-12-21 中国科学院上海微系统与信息技术研究所 Circuit for lowering CMOS transient power consumption
US10782420B2 (en) 2017-12-18 2020-09-22 Thermo Eberline Llc Range-extended dosimeter
CN109617410B (en) * 2018-12-28 2024-01-19 中国电子科技集团公司第五十八研究所 Novel floating voltage detection circuit
CN110045193A (en) * 2019-03-06 2019-07-23 珠海博雅科技有限公司 A kind of floating-gate device thump telegraph repeater measuring system and measurement method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430670A (en) * 1993-11-08 1995-07-04 Elantec, Inc. Differential analog memory cell and method for adjusting same
US5942936A (en) * 1995-12-29 1999-08-24 Stmicroelctronics, S.R.L. Offset compensating method and circuit for MOS differential stages

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059920A (en) * 1988-12-09 1991-10-22 Synaptics, Incorporated CMOS amplifier with offset adaptation
US4935702A (en) * 1988-12-09 1990-06-19 Synaptics, Inc. Subthreshold CMOS amplifier with offset adaptation
US4980859A (en) * 1989-04-07 1990-12-25 Xicor, Inc. NOVRAM cell using two differential decouplable nonvolatile memory elements
US4953928A (en) * 1989-06-09 1990-09-04 Synaptics Inc. MOS device for long-term learning
US5095284A (en) * 1990-09-10 1992-03-10 Synaptics, Incorporated Subthreshold CMOS amplifier with wide input voltage range
US5166562A (en) * 1991-05-09 1992-11-24 Synaptics, Incorporated Writable analog reference voltage storage device
US5875126A (en) * 1995-09-29 1999-02-23 California Institute Of Technology Autozeroing floating gate amplifier
US6297689B1 (en) * 1999-02-03 2001-10-02 National Semiconductor Corporation Low temperature coefficient low power programmable CMOS voltage reference
JP3933817B2 (en) * 1999-06-24 2007-06-20 富士通株式会社 Nonvolatile memory circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430670A (en) * 1993-11-08 1995-07-04 Elantec, Inc. Differential analog memory cell and method for adjusting same
US5942936A (en) * 1995-12-29 1999-08-24 Stmicroelctronics, S.R.L. Offset compensating method and circuit for MOS differential stages

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103424601A (en) * 2013-08-21 2013-12-04 矽力杰半导体技术(杭州)有限公司 Voltage detecting circuit
CN103424601B (en) * 2013-08-21 2015-08-19 矽力杰半导体技术(杭州)有限公司 A kind of voltage detecting circuit

Also Published As

Publication number Publication date
CN100407576C (en) 2008-07-30
CN1751437A (en) 2006-03-22
WO2004070987A2 (en) 2004-08-19
WO2004070987B1 (en) 2005-06-16
US20040145405A1 (en) 2004-07-29
WO2004070987A9 (en) 2004-09-30
US6815983B2 (en) 2004-11-09

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