WO2004072660A3 - Compressing test responses using a compactor - Google Patents

Compressing test responses using a compactor Download PDF

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Publication number
WO2004072660A3
WO2004072660A3 PCT/US2004/004271 US2004004271W WO2004072660A3 WO 2004072660 A3 WO2004072660 A3 WO 2004072660A3 US 2004004271 W US2004004271 W US 2004004271W WO 2004072660 A3 WO2004072660 A3 WO 2004072660A3
Authority
WO
WIPO (PCT)
Prior art keywords
compactor
disclosed
compressing test
test responses
compactors
Prior art date
Application number
PCT/US2004/004271
Other languages
French (fr)
Other versions
WO2004072660A2 (en
Inventor
Janusz Rajski
Jerzy Tyszer
Chen Wang
Grzegorz Mrugalski
Artur Pogiel
Original Assignee
Mentor Graphics Corp
Janusz Rajski
Jerzy Tyszer
Chen Wang
Grzegorz Mrugalski
Artur Pogiel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp, Janusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel filed Critical Mentor Graphics Corp
Priority to EP04700016A priority Critical patent/EP1595211B1/en
Priority to JP2006503551A priority patent/JP4791954B2/en
Priority to DE602004014904T priority patent/DE602004014904D1/en
Publication of WO2004072660A2 publication Critical patent/WO2004072660A2/en
Publication of WO2004072660A3 publication Critical patent/WO2004072660A3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

Abstract

The present disclosure describes embodiments of a compactor (706) for compressing test results in an integrated circuit (704) and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ('EDA') software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
PCT/US2004/004271 2003-02-13 2004-02-13 Compressing test responses using a compactor WO2004072660A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04700016A EP1595211B1 (en) 2003-02-13 2004-02-13 Compressing test responses using a compactor
JP2006503551A JP4791954B2 (en) 2003-02-13 2004-02-13 Test response compression using compactors
DE602004014904T DE602004014904D1 (en) 2003-02-13 2004-02-13 COMPRESS TEST RESPONSES USING A COMPACTOR

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US44763703P 2003-02-13 2003-02-13
US60/447,637 2003-02-13
US50649903P 2003-09-26 2003-09-26
US60/506,499 2003-09-26

Publications (2)

Publication Number Publication Date
WO2004072660A2 WO2004072660A2 (en) 2004-08-26
WO2004072660A3 true WO2004072660A3 (en) 2005-04-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/004271 WO2004072660A2 (en) 2003-02-13 2004-02-13 Compressing test responses using a compactor

Country Status (6)

Country Link
US (3) US7370254B2 (en)
EP (2) EP1595211B1 (en)
JP (1) JP4791954B2 (en)
AT (2) ATE532133T1 (en)
DE (1) DE602004014904D1 (en)
WO (1) WO2004072660A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8914694B2 (en) 2006-02-17 2014-12-16 Mentor Graphics Corporation On-chip comparison and response collection tools and techniques

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003032159A2 (en) * 2001-10-11 2003-04-17 Altera Corporation Error detection on programmable logic resources
US7058869B2 (en) * 2003-01-28 2006-06-06 Syntest Technologies, Inc. Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
US7437640B2 (en) * 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US7302624B2 (en) * 2003-02-13 2007-11-27 Janusz Rajski Adaptive fault diagnosis of compressed test responses
US7509550B2 (en) 2003-02-13 2009-03-24 Janusz Rajski Fault diagnosis of compressed test responses
EP1595211B1 (en) * 2003-02-13 2008-07-09 Mentor Graphics Corporation Compressing test responses using a compactor
US8280687B2 (en) * 2004-03-31 2012-10-02 Mentor Graphics Corporation Direct fault diagnostics using per-pattern compactor signatures
US7729884B2 (en) * 2004-03-31 2010-06-01 Yu Huang Compactor independent direct diagnosis of test hardware
US7239978B2 (en) * 2004-03-31 2007-07-03 Wu-Tung Cheng Compactor independent fault diagnosis
US7395473B2 (en) * 2004-12-10 2008-07-01 Wu-Tung Cheng Removing the effects of unknown test values from compacted test responses
US7260760B2 (en) * 2005-04-27 2007-08-21 International Business Machines Corporation Method and apparatus to disable compaction of test responses in deterministic test-set embedding-based BIST
US7272767B2 (en) * 2005-04-29 2007-09-18 Freescale Semiconductor, Inc. Methods and apparatus for incorporating IDDQ testing into logic BIST
US7451373B2 (en) 2005-06-17 2008-11-11 Infineon Technologies Ag Circuit for compression and storage of circuit diagnosis data
DE202005021320U1 (en) * 2005-06-17 2007-12-13 Infineon Technologies Ag Circuit for compressing and storing circuit diagnostic data
DE102005046588B4 (en) * 2005-09-28 2016-09-22 Infineon Technologies Ag Apparatus and method for testing and diagnosing digital circuits
US8161338B2 (en) * 2005-10-14 2012-04-17 Mentor Graphics Corporation Modular compaction of test responses
US7840862B2 (en) * 2006-02-17 2010-11-23 Mentor Graphics Corporation Enhanced diagnosis with limited failure cycles
US20070266283A1 (en) * 2006-05-01 2007-11-15 Nec Laboratories America, Inc. Method and Apparatus for Testing an Integrated Circuit
US7779322B1 (en) 2006-09-14 2010-08-17 Syntest Technologies, Inc. Compacting test responses using X-driven compactor
US7788562B2 (en) * 2006-11-29 2010-08-31 Advantest Corporation Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data
WO2008126471A1 (en) 2007-04-06 2008-10-23 Nec Corporation Semiconductor integrated circuit and its testing method
US7823034B2 (en) * 2007-04-13 2010-10-26 Synopsys, Inc. Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit
JP2010539633A (en) * 2007-09-18 2010-12-16 メンター グラフィックス コーポレイション Fault diagnosis in memory BIST environment
US7882409B2 (en) * 2007-09-21 2011-02-01 Synopsys, Inc. Method and apparatus for synthesis of augmented multimode compactors
US7949921B2 (en) * 2007-09-21 2011-05-24 Synopsys, Inc. Method and apparatus for synthesis of augmented multimode compactors
US7925947B1 (en) * 2008-01-14 2011-04-12 Syntest Technologies, Inc. X-canceling multiple-input signature register (MISR) for compacting output responses with unknowns
US7971176B2 (en) * 2008-03-18 2011-06-28 International Business Machines Corporation Method for testing integrated circuits
US8584073B2 (en) * 2008-07-21 2013-11-12 Synopsys, Inc. Test design optimizer for configurable scan architectures
US8112685B2 (en) 2009-06-11 2012-02-07 Texas Instruments Incorporated Serial compressed data I/O in a parallel test compression architecture
US8887018B2 (en) * 2010-06-11 2014-11-11 Texas Instruments Incorporated Masking circuit removing unknown bit from cell in scan chain
US8468404B1 (en) * 2010-06-25 2013-06-18 Cadence Design Systems, Inc. Method and system for reducing switching activity during scan-load operations
US8756468B2 (en) * 2011-04-28 2014-06-17 New York University Architecture, system, method, and computer-accessible medium for toggle-based masking
US9069989B2 (en) * 2012-01-27 2015-06-30 International Business Machines Corporation Chip authentication using scan chains
US20130326281A1 (en) * 2012-06-01 2013-12-05 Syntest Technologies, Inc. X-Tracer: A Reconfigurable X-Tolerance Trace Compressor for Silicon Debug
US10345369B2 (en) * 2012-10-02 2019-07-09 Synopsys, Inc. Augmented power-aware decompressor
US9081932B2 (en) 2013-02-01 2015-07-14 Qualcomm Incorporated System and method to design and test a yield sensitive circuit
US9329235B2 (en) 2013-03-13 2016-05-03 Synopsys, Inc. Localizing fault flop in circuit by using modified test pattern
US9411014B2 (en) 2013-03-22 2016-08-09 Synopsys, Inc. Reordering or removal of test patterns for detecting faults in integrated circuit
US9239897B2 (en) 2013-04-03 2016-01-19 Synopsys, Inc. Hierarchical testing architecture using core circuit with pseudo-interfaces
US9417287B2 (en) * 2013-04-17 2016-08-16 Synopsys, Inc. Scheme for masking output of scan chains in test circuit
US9588179B2 (en) 2013-06-12 2017-03-07 Synopsys, Inc. Scheme for masking output of scan chains in test circuit
US9009553B2 (en) * 2013-06-17 2015-04-14 Mentor Graphics Corporation Scan chain configuration for test-per-clock based on circuit topology
US10067187B2 (en) 2013-07-19 2018-09-04 Synopsys, Inc. Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment
EP3149630A2 (en) * 2014-05-29 2017-04-05 Universiteit Gent Integrated circuit verification using parameterized configuration
US9514844B2 (en) 2014-08-26 2016-12-06 Globalfoundries Inc. Fast auto shift of failing memory diagnostics data using pattern detection
US10215803B1 (en) 2014-10-15 2019-02-26 Santiago Remersaro Method and apparatus for concurrent inter-test response compaction and diagnosis
US9268892B1 (en) * 2014-12-19 2016-02-23 International Business Machines Corporation Identification of unknown sources for logic built-in self test in verification
US10380303B2 (en) 2015-11-30 2019-08-13 Synopsys, Inc. Power-aware dynamic encoding
US9891282B2 (en) 2015-12-24 2018-02-13 Intel Corporation Chip fabric interconnect quality on silicon
US10578672B2 (en) * 2015-12-31 2020-03-03 Stmicroelectronics (Grenoble 2) Sas Method, device and article to test digital circuits
US10060978B2 (en) * 2016-06-21 2018-08-28 International Business Machines Corporation Implementing prioritized compressed failure defects for efficient scan diagnostics
US10509072B2 (en) * 2017-03-03 2019-12-17 Mentor Graphics Corporation Test application time reduction using capture-per-cycle test points
US10705934B2 (en) * 2017-06-30 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Scan synchronous-write-through testing architectures for a memory device
DE102017121308B4 (en) 2017-06-30 2019-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. SYNCHRONOUS WRITE-THROUGH SAMPLING ARCHITECTURES FOR A MEMORY BLOCK
US10962595B1 (en) 2017-12-04 2021-03-30 Synopsys, Inc. Efficient realization of coverage collection in emulation
JP6570608B2 (en) * 2017-12-21 2019-09-04 キヤノン株式会社 Inspection equipment, imaging equipment, electronic equipment and transportation equipment
US11681843B2 (en) * 2018-01-17 2023-06-20 Siemens Industry Software Inc. Input data compression for machine learning-based chain diagnosis
US10775432B2 (en) * 2018-05-30 2020-09-15 Seagate Technology Llc Programmable scan compression
US10761131B1 (en) * 2018-09-25 2020-09-01 Cadence Design Systems, Inc. Method for optimally connecting scan segments in two-dimensional compression chains
US10908213B1 (en) * 2018-09-28 2021-02-02 Synopsys, Inc. Reducing X-masking effect for linear time compactors
CN110991295B (en) * 2019-11-26 2022-05-06 电子科技大学 Self-adaptive fault diagnosis method based on one-dimensional convolutional neural network
US11175338B2 (en) 2019-12-31 2021-11-16 Alibaba Group Holding Limited System and method for compacting test data in many-core processors
US11423202B2 (en) 2020-08-31 2022-08-23 Siemens Industry Software Inc. Suspect resolution for scan chain defect diagnosis

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790562A (en) * 1996-05-06 1998-08-04 General Motors Corporation Circuit with built-in test and method thereof
US6272653B1 (en) * 1997-11-14 2001-08-07 Intrinsity, Inc. Method and apparatus for built-in self-test of logic circuitry
US6543020B2 (en) * 1999-11-23 2003-04-01 Janusz Rajski Test pattern compression for an integrated circuit test environment

Family Cites Families (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4161041A (en) 1978-10-06 1979-07-10 The United States Of America As Represented By The Secretary Of The Air Force Pseudo random number generator apparatus
GB2049958B (en) 1979-03-15 1983-11-30 Nippon Electric Co Integrated logic circuit adapted to performance tests
US4320509A (en) 1979-10-19 1982-03-16 Bell Telephone Laboratories, Incorporated LSI Circuit logic structure including data compression circuitry
US4503537A (en) 1982-11-08 1985-03-05 International Business Machines Corporation Parallel path self-testing system
US4513418A (en) 1982-11-08 1985-04-23 International Business Machines Corporation Simultaneous self-testing system
US4602210A (en) 1984-12-28 1986-07-22 General Electric Company Multiplexed-access scan testable integrated circuit
US4687988A (en) 1985-06-24 1987-08-18 International Business Machines Corporation Weighted random pattern testing apparatus and method
US4801870A (en) 1985-06-24 1989-01-31 International Business Machines Corporation Weighted random pattern testing apparatus and method
US4754215A (en) 1985-11-06 1988-06-28 Nec Corporation Self-diagnosable integrated circuit device capable of testing sequential circuit elements
JPS63286780A (en) 1987-05-20 1988-11-24 Hitachi Ltd Fault detecting system and fault detecting device
JPH01239486A (en) 1988-03-18 1989-09-25 Nec Corp Output response compressor
JP2591825B2 (en) 1989-05-30 1997-03-19 富士通株式会社 Logic circuit testing method and apparatus using compressed data
JP2584673B2 (en) 1989-06-09 1997-02-26 株式会社日立製作所 Logic circuit test apparatus having test data change circuit
WO1991010182A1 (en) 1989-12-21 1991-07-11 Bell Communications Research, Inc. Generator of multiple uncorrelated noise sources
JPH03214809A (en) 1990-01-19 1991-09-20 Nec Corp Linear feedback shift register
US5091908A (en) * 1990-02-06 1992-02-25 At&T Bell Laboratories Built-in self-test technique for read-only memories
US5138619A (en) 1990-02-15 1992-08-11 National Semiconductor Corporation Built-in self test for integrated circuit memory
US5167034A (en) 1990-06-18 1992-11-24 International Business Machines Corporation Data integrity for compaction devices
US5173906A (en) 1990-08-31 1992-12-22 Dreibelbis Jeffrey H Built-in self test for integrated circuits
US5258986A (en) 1990-09-19 1993-11-02 Vlsi Technology, Inc. Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
US5369648A (en) 1991-11-08 1994-11-29 Ncr Corporation Built-in self-test circuit
JPH05215816A (en) 1991-12-06 1993-08-27 Nec Corp Information processing device
JP2711492B2 (en) 1992-03-05 1998-02-10 日本電信電話株式会社 Built-in self-test circuit
EP0549949B1 (en) 1991-12-16 1998-03-11 Nippon Telegraph And Telephone Corporation Built-in self test circuit
US5412665A (en) 1992-01-10 1995-05-02 International Business Machines Corporation Parallel operation linear feedback shift register
US5436653A (en) * 1992-04-30 1995-07-25 The Arbitron Company Method and system for recognition of broadcast segments
US5608870A (en) 1992-11-06 1997-03-04 The President And Fellows Of Harvard College System for combining a plurality of requests referencing a common target address into a single combined request having a single reference to the target address
US5450414A (en) 1993-05-17 1995-09-12 At&T Corp. Partial-scan built-in self-testing circuit having improved testability
US5533035A (en) * 1993-06-16 1996-07-02 Hal Computer Systems, Inc. Error detection and correction method and apparatus
US5416783A (en) 1993-08-09 1995-05-16 Motorola, Inc. Method and apparatus for generating pseudorandom numbers or for performing data compression in a data processor
US5848198A (en) 1993-10-08 1998-12-08 Penn; Alan Irvin Method of and apparatus for analyzing images and deriving binary image representations
JP2882743B2 (en) 1993-12-21 1999-04-12 川崎製鉄株式会社 Semiconductor integrated circuit device
US5631913A (en) 1994-02-09 1997-05-20 Matsushita Electric Industrial Co., Ltd. Test circuit and test method of integrated semiconductor device
JP3403814B2 (en) 1994-07-04 2003-05-06 富士通株式会社 Circuit with built-in self-test function
US5642362A (en) 1994-07-20 1997-06-24 International Business Machines Corporation Scan-based delay tests having enhanced test vector pattern generation
US5533128A (en) 1995-01-18 1996-07-02 Vobach; Arnold Pseudo-random transposition cipher system and method
US5574733A (en) 1995-07-25 1996-11-12 Intel Corporation Scan-based built-in self test (BIST) with automatic reseeding of pattern generator
US5831992A (en) * 1995-08-17 1998-11-03 Northern Telecom Limited Methods and apparatus for fault diagnosis in self-testable systems
US5680543A (en) 1995-10-20 1997-10-21 Lucent Technologies Inc. Method and apparatus for built-in self-test with multiple clock circuits
US5867507A (en) 1995-12-12 1999-02-02 International Business Machines Corporation Testable programmable gate array and associated LSSD/deterministic test methodology
EP0805458B1 (en) 1996-04-30 2001-06-27 Agilent Technologies, Inc. An electronic circuit or board tester with compressed data-sequences
US5717701A (en) 1996-08-13 1998-02-10 International Business Machines Corporation Apparatus and method for testing interconnections between semiconductor devices
US5991909A (en) 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
KR100206128B1 (en) 1996-10-21 1999-07-01 윤종용 Built-in self test circuit
US5694402A (en) 1996-10-22 1997-12-02 Texas Instruments Incorporated System and method for structurally testing integrated circuit devices
US5701308A (en) 1996-10-29 1997-12-23 Lockheed Martin Corporation Fast bist architecture with flexible standard interface
US5905986A (en) 1997-01-07 1999-05-18 Hewlett-Packard Company Highly compressible representation of test pattern data
US5991898A (en) 1997-03-10 1999-11-23 Mentor Graphics Corporation Arithmetic built-in self test of multiple scan-based integrated circuits
US6026508A (en) 1997-04-22 2000-02-15 International Business Machines Corporation Storage sub-system compression and dataflow chip offering excellent data integrity
JPH1130646A (en) 1997-07-10 1999-02-02 Nec Eng Ltd Semiconductor integrated circuit and test circuit to be comprised therein
US5883906A (en) 1997-08-15 1999-03-16 Advantest Corp. Pattern data compression and decompression for semiconductor test system
DE59813158D1 (en) 1997-09-18 2005-12-08 Infineon Technologies Ag Method for testing an electronic circuit
JP3047883B2 (en) 1998-03-17 2000-06-05 日本電気株式会社 Output circuit of semiconductor device having test mode
JP3257528B2 (en) * 1998-12-28 2002-02-18 日本電気株式会社 Test pattern generation method and apparatus, and recording medium storing test pattern generation program
GB9900432D0 (en) 1999-01-08 1999-02-24 Xilinx Inc Linear feedback shift register in a progammable gate array
US6467058B1 (en) * 1999-01-20 2002-10-15 Nec Usa, Inc. Segmented compaction with pruning and critical fault elimination
US6590929B1 (en) 1999-06-08 2003-07-08 International Business Machines Corporation Method and system for run-time logic verification of operations in digital systems
US6463561B1 (en) * 1999-09-29 2002-10-08 Agere Systems Guardian Corp. Almost full-scan BIST method and system having higher fault coverage and shorter test application time
US6353842B1 (en) 1999-11-23 2002-03-05 Janusz Rajski Method for synthesizing linear finite state machines
JP3845016B2 (en) 1999-11-23 2006-11-15 メンター・グラフィクス・コーポレーション Continuous application and decompression of test patterns to the field of circuit technology under test
US6684358B1 (en) 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US6874109B1 (en) 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
US6557129B1 (en) 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
DE60108993T2 (en) 2000-03-09 2005-07-21 Texas Instruments Inc., Dallas Customization of Scan-BIST architectures for low-consumption operation
US6300885B1 (en) 2000-04-14 2001-10-09 International Business Machines Corporation Dual aldc decompressors inside printer asic
US6668347B1 (en) * 2000-05-08 2003-12-23 Intel Corporation Built-in self-testing for embedded memory
JP4228061B2 (en) 2000-12-07 2009-02-25 富士通マイクロエレクトロニクス株式会社 Integrated circuit test apparatus and test method
US6782501B2 (en) * 2001-01-23 2004-08-24 Cadence Design Systems, Inc. System for reducing test data volume in the testing of logic products
US6950974B1 (en) 2001-09-07 2005-09-27 Synopsys Inc. Efficient compression and application of deterministic patterns in a logic BIST architecture
US7552373B2 (en) * 2002-01-16 2009-06-23 Syntest Technologies, Inc. Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
US6807646B1 (en) * 2002-03-04 2004-10-19 Synopsys, Inc. System and method for time slicing deterministic patterns for reseeding in logic built-in self-test
US7185253B2 (en) 2002-03-27 2007-02-27 Intel Corporation Compacting circuit responses
US6671839B1 (en) 2002-06-27 2003-12-30 Logicvision, Inc. Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith
US7058869B2 (en) 2003-01-28 2006-06-06 Syntest Technologies, Inc. Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
US7437640B2 (en) 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US7509550B2 (en) 2003-02-13 2009-03-24 Janusz Rajski Fault diagnosis of compressed test responses
EP1595211B1 (en) 2003-02-13 2008-07-09 Mentor Graphics Corporation Compressing test responses using a compactor
US7302624B2 (en) * 2003-02-13 2007-11-27 Janusz Rajski Adaptive fault diagnosis of compressed test responses
US7032148B2 (en) 2003-07-07 2006-04-18 Syntest Technologies, Inc. Mask network design for scan-based integrated circuits
US7574640B2 (en) 2003-09-05 2009-08-11 Intel Corporation Compacting circuit responses

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790562A (en) * 1996-05-06 1998-08-04 General Motors Corporation Circuit with built-in test and method thereof
US6272653B1 (en) * 1997-11-14 2001-08-07 Intrinsity, Inc. Method and apparatus for built-in self-test of logic circuitry
US6543020B2 (en) * 1999-11-23 2003-04-01 Janusz Rajski Test pattern compression for an integrated circuit test environment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8914694B2 (en) 2006-02-17 2014-12-16 Mentor Graphics Corporation On-chip comparison and response collection tools and techniques
US9250287B2 (en) 2006-02-17 2016-02-02 Mentor Graphics Corporation On-chip comparison and response collection tools and techniques

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US7370254B2 (en) 2008-05-06
WO2004072660A2 (en) 2004-08-26
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ATE532133T1 (en) 2011-11-15
EP1595211B1 (en) 2008-07-09
JP2006518855A (en) 2006-08-17
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US20100257417A1 (en) 2010-10-07
US7743302B2 (en) 2010-06-22

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