WO2004073031A3 - Alternative flip chip in leaded molded package design and method for manufacture - Google Patents

Alternative flip chip in leaded molded package design and method for manufacture Download PDF

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Publication number
WO2004073031A3
WO2004073031A3 PCT/US2004/003633 US2004003633W WO2004073031A3 WO 2004073031 A3 WO2004073031 A3 WO 2004073031A3 US 2004003633 W US2004003633 W US 2004003633W WO 2004073031 A3 WO2004073031 A3 WO 2004073031A3
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WO
WIPO (PCT)
Prior art keywords
manufacture
flip chip
package design
molded package
leaded molded
Prior art date
Application number
PCT/US2004/003633
Other languages
French (fr)
Other versions
WO2004073031A2 (en
Inventor
Romel N Manatad
Original Assignee
Fairchild Semiconductor
Romel N Manatad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor, Romel N Manatad filed Critical Fairchild Semiconductor
Priority to DE112004000258T priority Critical patent/DE112004000258T5/en
Priority to JP2006503414A priority patent/JP4699353B2/en
Priority to KR1020057014660A priority patent/KR101050721B1/en
Publication of WO2004073031A2 publication Critical patent/WO2004073031A2/en
Publication of WO2004073031A3 publication Critical patent/WO2004073031A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
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    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/351—Thermal stress

Abstract

A semiconductor package is disclosed. The package includes a leadframe structure comprising a die attach region and plurality of leads. A molding material is molded around at least a portion of the leadframe structure, and comprises a window. A semiconductor die comprising an edge is mounted on the die attach region and is within the window. A gap is present between the edge of the semiconductor die and the molding material.
PCT/US2004/003633 2003-02-11 2004-02-09 Alternative flip chip in leaded molded package design and method for manufacture WO2004073031A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE112004000258T DE112004000258T5 (en) 2003-02-11 2004-02-09 Alternative Design for a Flip Chip in Leaded Molded Package and Method of Fabrication
JP2006503414A JP4699353B2 (en) 2003-02-11 2004-02-09 Alternative FLMP package design and package manufacturing method
KR1020057014660A KR101050721B1 (en) 2003-02-11 2004-02-09 Alternative Flip Chip in Leaded Molded Package Design and Its Manufacturing Method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44691803P 2003-02-11 2003-02-11
US60/446,918 2003-02-11

Publications (2)

Publication Number Publication Date
WO2004073031A2 WO2004073031A2 (en) 2004-08-26
WO2004073031A3 true WO2004073031A3 (en) 2005-03-31

Family

ID=32869573

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/003633 WO2004073031A2 (en) 2003-02-11 2004-02-09 Alternative flip chip in leaded molded package design and method for manufacture

Country Status (7)

Country Link
US (2) US7217594B2 (en)
JP (1) JP4699353B2 (en)
KR (1) KR101050721B1 (en)
CN (1) CN100576523C (en)
DE (1) DE112004000258T5 (en)
TW (1) TWI242857B (en)
WO (1) WO2004073031A2 (en)

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US7586178B2 (en) 2009-09-08
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TW200425438A (en) 2004-11-16
JP4699353B2 (en) 2011-06-08
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US7217594B2 (en) 2007-05-15
US20070241431A1 (en) 2007-10-18
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CN100576523C (en) 2009-12-30
KR20050102638A (en) 2005-10-26

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