WO2004075265A2 - Methods for selectively bumping integrated circuit substrates and related structures - Google Patents
Methods for selectively bumping integrated circuit substrates and related structures Download PDFInfo
- Publication number
- WO2004075265A2 WO2004075265A2 PCT/US2004/005818 US2004005818W WO2004075265A2 WO 2004075265 A2 WO2004075265 A2 WO 2004075265A2 US 2004005818 W US2004005818 W US 2004005818W WO 2004075265 A2 WO2004075265 A2 WO 2004075265A2
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- WO
- WIPO (PCT)
- Prior art keywords
- layer
- barrier layer
- metal layer
- conductive bump
- substrate
- Prior art date
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006503894A JP2006518115A (en) | 2003-02-18 | 2004-02-17 | Method of selectively bumping integrated circuit boards and related structures |
EP04711949A EP1595283A2 (en) | 2003-02-18 | 2004-02-17 | Methods for selectively bumping integrated circuit substrates and related structures |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US44809603P | 2003-02-18 | 2003-02-18 | |
US60/448,096 | 2003-02-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004075265A2 true WO2004075265A2 (en) | 2004-09-02 |
WO2004075265A3 WO2004075265A3 (en) | 2004-11-04 |
Family
ID=32908533
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/005818 WO2004075265A2 (en) | 2003-02-18 | 2004-02-17 | Methods for selectively bumping integrated circuit substrates and related structures |
Country Status (7)
Country | Link |
---|---|
US (2) | US7081404B2 (en) |
EP (1) | EP1595283A2 (en) |
JP (1) | JP2006518115A (en) |
KR (1) | KR20050105223A (en) |
CN (1) | CN1784775A (en) |
TW (2) | TWI225899B (en) |
WO (1) | WO2004075265A2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
JP2006518115A (en) | 2006-08-03 |
EP1595283A2 (en) | 2005-11-16 |
KR20050105223A (en) | 2005-11-03 |
TW200416305A (en) | 2004-09-01 |
CN1784775A (en) | 2006-06-07 |
TWI225899B (en) | 2005-01-01 |
US7579694B2 (en) | 2009-08-25 |
US7081404B2 (en) | 2006-07-25 |
US20040209406A1 (en) | 2004-10-21 |
TW200507120A (en) | 2005-02-16 |
US20060231951A1 (en) | 2006-10-19 |
WO2004075265A3 (en) | 2004-11-04 |
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