WO2004092968A3 - Multi-node system with global access states - Google Patents

Multi-node system with global access states Download PDF

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Publication number
WO2004092968A3
WO2004092968A3 PCT/US2004/010895 US2004010895W WO2004092968A3 WO 2004092968 A3 WO2004092968 A3 WO 2004092968A3 US 2004010895 W US2004010895 W US 2004010895W WO 2004092968 A3 WO2004092968 A3 WO 2004092968A3
Authority
WO
WIPO (PCT)
Prior art keywords
node
nodes
coherency
active device
coherency unit
Prior art date
Application number
PCT/US2004/010895
Other languages
French (fr)
Other versions
WO2004092968A2 (en
Inventor
Robert E Cypher
Anders Landin
Erik E Hagersten
Original Assignee
Sun Microsystems Inc
Robert E Cypher
Anders Landin
Erik E Hagersten
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc, Robert E Cypher, Anders Landin, Erik E Hagersten filed Critical Sun Microsystems Inc
Priority to EP04759305A priority Critical patent/EP1616260A2/en
Publication of WO2004092968A2 publication Critical patent/WO2004092968A2/en
Publication of WO2004092968A3 publication Critical patent/WO2004092968A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods

Abstract

A system may include several nodes coupled by an inter-node network configured to convey coherency messages between the nodes. Each node may include several active devices coupled by an address network and a data network. The nodes implement a coherency protocol such that if an active device in one of the nodes has an ownership responsibility for a coherency unit, no active device in any of the other nodes has a valid access right to the coherency unit. For example, if a node receives a coherency message requesting read access to a coherency unit from another node, the node may respond by conveying a proxy address packet, receipt of which removes ownership, on the node's address network to an owning active device. In contrast, the active device's ownership responsibility may not be removed in response to a device within the same node requesting read access to the coherency unit.
PCT/US2004/010895 2003-04-11 2004-04-09 Multi-node system with global access states WO2004092968A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04759305A EP1616260A2 (en) 2003-04-11 2004-04-09 Multi-node system with global access states

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US46202703P 2003-04-11 2003-04-11
US60/462,027 2003-04-11

Publications (2)

Publication Number Publication Date
WO2004092968A2 WO2004092968A2 (en) 2004-10-28
WO2004092968A3 true WO2004092968A3 (en) 2004-12-09

Family

ID=33299892

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/010895 WO2004092968A2 (en) 2003-04-11 2004-04-09 Multi-node system with global access states

Country Status (3)

Country Link
US (1) US8024526B2 (en)
EP (1) EP1616260A2 (en)
WO (1) WO2004092968A2 (en)

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US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US8559443B2 (en) 2005-07-22 2013-10-15 Marvell International Ltd. Efficient message switching in a switching apparatus
US7957474B2 (en) 2006-01-26 2011-06-07 Texas Instruments Incorporated Robust detection of packet types
US9674283B2 (en) * 2014-01-15 2017-06-06 Cisco Technology, Inc. Method for solving coherency lock issues in proxy services
US11575504B2 (en) 2019-06-29 2023-02-07 Intel Corporation Cryptographic computing engine for memory load and store units of a microarchitecture pipeline
US11403234B2 (en) 2019-06-29 2022-08-02 Intel Corporation Cryptographic computing using encrypted base addresses and used in multi-tenant environments
US11580234B2 (en) 2019-06-29 2023-02-14 Intel Corporation Implicit integrity for cryptographic computing
US11669625B2 (en) 2020-12-26 2023-06-06 Intel Corporation Data type based cryptographic computing
US11580035B2 (en) * 2020-12-26 2023-02-14 Intel Corporation Fine-grained stack protection using cryptographic computing
CN114884713A (en) * 2022-04-26 2022-08-09 中通服慧展科技有限公司 Information protection method, device, equipment and medium

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US5335335A (en) * 1991-08-30 1994-08-02 Compaq Computer Corporation Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed
EP0817073A2 (en) * 1996-07-01 1998-01-07 Sun Microsystems, Inc. A multiprocessing system configured to perform efficient write operations
US20020124144A1 (en) * 2000-06-10 2002-09-05 Kourosh Gharachorloo Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector
US6457100B1 (en) * 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
EP1255201A1 (en) * 2001-05-01 2002-11-06 Sun Microsystems, Inc. Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols

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US6088768A (en) 1993-12-28 2000-07-11 International Business Machines Corporation Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication
US5987549A (en) * 1996-07-01 1999-11-16 Sun Microsystems, Inc. Method and apparatus providing short latency round-robin arbitration for access to a shared resource
US5940860A (en) * 1996-07-01 1999-08-17 Sun Microsystems, Inc. Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains
US5887138A (en) * 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US5983332A (en) 1996-07-01 1999-11-09 Sun Microsystems, Inc. Asynchronous transfer mode (ATM) segmentation and reassembly unit virtual address translation unit architecture
US5802582A (en) 1996-09-10 1998-09-01 International Business Machines Corporation Explicit coherence using split-phase controls
US6209064B1 (en) 1998-01-07 2001-03-27 Fujitsu Limited Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
US6631401B1 (en) * 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6868481B1 (en) * 2000-10-31 2005-03-15 Hewlett-Packard Development Company, L.P. Cache coherence protocol for a multiple bus multiprocessor system
TW591526B (en) * 2002-04-09 2004-06-11 Via Tech Inc Data maintenance method of DSM system
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US6944719B2 (en) * 2002-05-15 2005-09-13 Broadcom Corp. Scalable cache coherent distributed shared memory processing system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5335335A (en) * 1991-08-30 1994-08-02 Compaq Computer Corporation Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed
EP0817073A2 (en) * 1996-07-01 1998-01-07 Sun Microsystems, Inc. A multiprocessing system configured to perform efficient write operations
US6457100B1 (en) * 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
US20020124144A1 (en) * 2000-06-10 2002-09-05 Kourosh Gharachorloo Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector
EP1255201A1 (en) * 2001-05-01 2002-11-06 Sun Microsystems, Inc. Shared memory multiprocessing system employing mixed broadcast snooping and directory based coherency protocols

Also Published As

Publication number Publication date
US8024526B2 (en) 2011-09-20
US20040268057A1 (en) 2004-12-30
WO2004092968A2 (en) 2004-10-28
EP1616260A2 (en) 2006-01-18

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