WO2004095290A3 - System and method for dynamic mirror-bank addressing - Google Patents

System and method for dynamic mirror-bank addressing Download PDF

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Publication number
WO2004095290A3
WO2004095290A3 PCT/US2004/005522 US2004005522W WO2004095290A3 WO 2004095290 A3 WO2004095290 A3 WO 2004095290A3 US 2004005522 W US2004005522 W US 2004005522W WO 2004095290 A3 WO2004095290 A3 WO 2004095290A3
Authority
WO
WIPO (PCT)
Prior art keywords
banks
memory
mirror flag
asserted
bank
Prior art date
Application number
PCT/US2004/005522
Other languages
French (fr)
Other versions
WO2004095290A2 (en
Inventor
Robert E Jeter Jr
Kenneth H Potter Jr
Original Assignee
Cisco Tech Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cisco Tech Ind filed Critical Cisco Tech Ind
Priority to EP04715006A priority Critical patent/EP1606712B1/en
Priority to AU2004232184A priority patent/AU2004232184B2/en
Priority to DE602004004383T priority patent/DE602004004383T2/en
Priority to CA2519332A priority patent/CA2519332C/en
Publication of WO2004095290A2 publication Critical patent/WO2004095290A2/en
Publication of WO2004095290A3 publication Critical patent/WO2004095290A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2056—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant by mirroring
    • G06F11/2087—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant by mirroring with a common controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2056—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant by mirroring
    • G06F11/2069—Management of state, configuration or failover
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1448—Management of the data involved in backup or backup restore
    • G06F11/1451—Management of the data involved in backup or backup restore by selection of backup contents

Abstract

A dynamic addressing technique mirrors data across multiple banks of a memory resource. Information stored in the memory banks is organized into separately addressable blocks, and memory addresses include a mirror flag. To write information mirrored across two memory banks, a processor issues a single write transaction with the mirror flag asserted. A memory controller detects that the mirror flag is asserted and, in response, waits for both memory banks to become available. At that point, the memory controller causes the write to be performed at both banks. To read data that has been mirrored across two memory banks, the processor issues a read with the mirror flag asserted. The memory controller checks the availability of both banks having the desired information. If either bank is available, the read request is accepted and the desired data is retrieved from the available bank and returned to the processor.
PCT/US2004/005522 2003-03-21 2004-02-26 System and method for dynamic mirror-bank addressing WO2004095290A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP04715006A EP1606712B1 (en) 2003-03-21 2004-02-26 System and method for dynamic mirror-bank addressing
AU2004232184A AU2004232184B2 (en) 2003-03-21 2004-02-26 System and method for dynamic mirror-bank addressing
DE602004004383T DE602004004383T2 (en) 2003-03-21 2004-02-26 SYSTEM AND METHOD FOR THE DYNAMIC ADDRESSING OF MIRRORED MEMORY BANK
CA2519332A CA2519332C (en) 2003-03-21 2004-02-26 System and method for dynamic mirror-bank addressing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/394,984 US7194568B2 (en) 2003-03-21 2003-03-21 System and method for dynamic mirror-bank addressing
US10/394,984 2003-03-21

Publications (2)

Publication Number Publication Date
WO2004095290A2 WO2004095290A2 (en) 2004-11-04
WO2004095290A3 true WO2004095290A3 (en) 2004-12-02

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Family Applications (1)

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PCT/US2004/005522 WO2004095290A2 (en) 2003-03-21 2004-02-26 System and method for dynamic mirror-bank addressing

Country Status (8)

Country Link
US (1) US7194568B2 (en)
EP (2) EP1606712B1 (en)
CN (1) CN100383751C (en)
AT (2) ATE411560T1 (en)
AU (1) AU2004232184B2 (en)
CA (1) CA2519332C (en)
DE (2) DE602004004383T2 (en)
WO (1) WO2004095290A2 (en)

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Also Published As

Publication number Publication date
CN100383751C (en) 2008-04-23
EP1777626A1 (en) 2007-04-25
DE602004017232D1 (en) 2008-11-27
CA2519332A1 (en) 2004-11-04
DE602004004383D1 (en) 2007-03-08
WO2004095290A2 (en) 2004-11-04
CN1761947A (en) 2006-04-19
US20040186945A1 (en) 2004-09-23
EP1606712B1 (en) 2007-01-17
ATE352064T1 (en) 2007-02-15
AU2004232184B2 (en) 2010-05-27
EP1777626B1 (en) 2008-10-15
DE602004004383T2 (en) 2007-11-08
ATE411560T1 (en) 2008-10-15
US7194568B2 (en) 2007-03-20
EP1606712A2 (en) 2005-12-21
CA2519332C (en) 2011-09-13
AU2004232184A1 (en) 2004-11-04

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