WO2004097610A3 - Clock align technique for excessive static phase offset - Google Patents
Clock align technique for excessive static phase offset Download PDFInfo
- Publication number
- WO2004097610A3 WO2004097610A3 PCT/US2004/011015 US2004011015W WO2004097610A3 WO 2004097610 A3 WO2004097610 A3 WO 2004097610A3 US 2004011015 W US2004011015 W US 2004011015W WO 2004097610 A3 WO2004097610 A3 WO 2004097610A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- clock signal
- phase offset
- static phase
- jbus
- cpu clock
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
Abstract
A CPU clock signal (314) generated from a phase lock loop (PLL) circuit (312) and a feedback signal (320) of the PLL circuit (312) are used in generating a JBUS clock signal (318). The CPU clock signal (314) and the feedback signal (320) include the same amount of static phase offset introduced by the PLL circuit (312). The CPU clock signal (314) and the feedback signal (320) are input to an alignment detection circuit (316) and used in generating the JBUS clock signal (318). In one embodiment, the JBUS clock signal (318) is generated in synchronization with the CPU clock signal (314) and having the frequency of the feedback signal (320). The present invention reduces or eliminates misalignment of the leading edge of the JBUS clock signal (318) with reference to a specific leading edge of the CPU clock signal (314) due to the presence of static phase offset introduced by the PLL circuit (312).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/425,213 | 2003-04-28 | ||
US10/425,213 US7111186B2 (en) | 2003-04-28 | 2003-04-28 | Method and apparatus for static phase offset correction |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004097610A2 WO2004097610A2 (en) | 2004-11-11 |
WO2004097610A3 true WO2004097610A3 (en) | 2005-04-07 |
Family
ID=33299487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/011015 WO2004097610A2 (en) | 2003-04-28 | 2004-04-09 | Clock align technique for excessive static phase offset |
Country Status (2)
Country | Link |
---|---|
US (1) | US7111186B2 (en) |
WO (1) | WO2004097610A2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7698576B2 (en) * | 2004-09-30 | 2010-04-13 | Intel Corporation | CPU power delivery system |
US7247930B2 (en) * | 2004-09-30 | 2007-07-24 | Intel Corporation | Power management integrated circuit |
US7844847B2 (en) * | 2006-09-18 | 2010-11-30 | Samsung Electronics Co., Ltd. | System and method for tuning power consumption and group delay in wireless RFICs |
US7535272B1 (en) | 2007-11-23 | 2009-05-19 | Hong Kong Applied Science And Technology Research Institute Co. Ltd. | Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL) |
US8606989B2 (en) * | 2010-08-31 | 2013-12-10 | Lsi Corporation | Methods and apparatus for burst data transfers between double data rate (DDR) memories and embedded processors during training |
US8134393B1 (en) | 2010-09-29 | 2012-03-13 | Motorola Solutions, Inc. | Method and apparatus for correcting phase offset errors in a communication device |
JP5588577B1 (en) | 2011-06-01 | 2014-09-10 | ギャンブリット ゲーミング,エルエルシー | Systems and methods for regulated hybrid games |
US11635739B1 (en) | 2020-04-30 | 2023-04-25 | Marvell Asia Pte Ltd | System and method to manage power to a desired power profile |
US11340673B1 (en) * | 2020-04-30 | 2022-05-24 | Marvell Asia Pte Ltd | System and method to manage power throttling |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0735494A1 (en) * | 1995-03-30 | 1996-10-02 | International Business Machines Corporation | Multiple clock translator for non-integer frequency ratios |
US20020199124A1 (en) * | 2001-06-22 | 2002-12-26 | Adkisson Richard W. | System and method for synchronizing data transfer across a clock domain boundary |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5471587A (en) * | 1992-09-30 | 1995-11-28 | Intel Corporation | Fractional speed bus coupling |
US5701447A (en) * | 1995-07-28 | 1997-12-23 | Intel Corporation | Method and apparatus for eliminating latch propagation delays in an alignment unit for use in a fractional bus architecture |
US5802132A (en) * | 1995-12-29 | 1998-09-01 | Intel Corporation | Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme |
US6172937B1 (en) * | 1998-05-13 | 2001-01-09 | Intel Corporation | Multiple synthesizer based timing signal generation scheme |
US6182237B1 (en) * | 1998-08-31 | 2001-01-30 | International Business Machines Corporation | System and method for detecting phase errors in asics with multiple clock frequencies |
US6157233A (en) * | 1998-12-16 | 2000-12-05 | Intel Corporation | Always-deterministic phase-locked loop |
US6434706B1 (en) * | 1999-05-24 | 2002-08-13 | Koninklijke Philips Electronics N.V. | Clock system for multiple component system including module clocks for safety margin of data transfers among processing modules |
US6943610B2 (en) * | 2002-04-19 | 2005-09-13 | Intel Corporation | Clock distribution network using feedback for skew compensation and jitter filtering |
-
2003
- 2003-04-28 US US10/425,213 patent/US7111186B2/en active Active
-
2004
- 2004-04-09 WO PCT/US2004/011015 patent/WO2004097610A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0735494A1 (en) * | 1995-03-30 | 1996-10-02 | International Business Machines Corporation | Multiple clock translator for non-integer frequency ratios |
US20020199124A1 (en) * | 2001-06-22 | 2002-12-26 | Adkisson Richard W. | System and method for synchronizing data transfer across a clock domain boundary |
Also Published As
Publication number | Publication date |
---|---|
WO2004097610A2 (en) | 2004-11-11 |
US7111186B2 (en) | 2006-09-19 |
US20040215993A1 (en) | 2004-10-28 |
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