WO2004102635A9 - Methods for preserving strained semiconductor layers during oxide layer formation - Google Patents
Methods for preserving strained semiconductor layers during oxide layer formationInfo
- Publication number
- WO2004102635A9 WO2004102635A9 PCT/US2003/034576 US0334576W WO2004102635A9 WO 2004102635 A9 WO2004102635 A9 WO 2004102635A9 US 0334576 W US0334576 W US 0334576W WO 2004102635 A9 WO2004102635 A9 WO 2004102635A9
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- strained
- silicon
- germanium
- oxide
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 83
- 239000004065 semiconductor Substances 0.000 title claims description 88
- 230000015572 biosynthetic process Effects 0.000 title claims description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 40
- 238000000151 deposition Methods 0.000 claims abstract description 39
- 238000012216 screening Methods 0.000 claims abstract description 36
- 239000010703 silicon Substances 0.000 claims abstract description 36
- 230000008021 deposition Effects 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 65
- 229910052732 germanium Inorganic materials 0.000 claims description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 239000002019 doping agent Substances 0.000 claims description 19
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 12
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 11
- 230000000873 masking effect Effects 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 9
- 239000000956 alloy Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000007547 defect Effects 0.000 claims description 3
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 293
- 235000012431 wafers Nutrition 0.000 abstract description 30
- 239000000463 material Substances 0.000 abstract description 24
- 238000011109 contamination Methods 0.000 abstract description 3
- 239000002344 surface layer Substances 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 description 10
- 229910052906 cristobalite Inorganic materials 0.000 description 10
- 229910052682 stishovite Inorganic materials 0.000 description 10
- 229910052905 tridymite Inorganic materials 0.000 description 10
- 239000007789 gas Substances 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 230000003746 surface roughness Effects 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- PFNQVRZLDWYSCW-UHFFFAOYSA-N (fluoren-9-ylideneamino) n-naphthalen-1-ylcarbamate Chemical compound C12=CC=CC=C2C2=CC=CC=C2C1=NOC(=O)NC1=CC=CC2=CC=CC=C12 PFNQVRZLDWYSCW-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 3
- 229910003820 SiGeO2 Inorganic materials 0.000 description 3
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 3
- -1 for example Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 230000037230 mobility Effects 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000012686 silicon precursor Substances 0.000 description 2
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 2
- 239000005052 trichlorosilane Substances 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000005083 Zinc sulfide Substances 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000012864 cross contamination Methods 0.000 description 1
- OXTURSYJKMYFLT-UHFFFAOYSA-N dichlorogermane Chemical compound Cl[GeH2]Cl OXTURSYJKMYFLT-UHFFFAOYSA-N 0.000 description 1
- VXGHASBVNMHGDI-UHFFFAOYSA-N digermane Chemical compound [Ge][Ge] VXGHASBVNMHGDI-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910000167 hafnon Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- IEXRMSFAVATTJX-UHFFFAOYSA-N tetrachlorogermane Chemical compound Cl[Ge](Cl)(Cl)Cl IEXRMSFAVATTJX-UHFFFAOYSA-N 0.000 description 1
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/0251—Graded layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
Definitions
- This invention relates generally to semiconductor substrates and specifically to formation of dielectric layers on semiconductor substrates.
- the important component of a SiGe virtual substrate is a layer of SiGe heterostructure that has been relaxed to its equilibrium lattice constant (i.e., one that is larger than that of Si).
- This relaxed SiGe layer can be directly applied to a Si substrate (e.g., by wafer bonding or direct epitaxy), or atop a relaxed graded SiGe buffer layer in which the lattice constant of the SiGe material has been increased gradually over the thickness of the layer.
- the SiGe virtual substrate may also incorporate buried insulating layers, in the manner of a silicon-on-insulator (SOT) wafer.
- thin strained layers of semiconductors such as Si, Ge, or SiGe
- Si, Ge, or SiGe are grown on the relaxed SiGe virtual substrates.
- the resulting biaxial tensile or compressive strain alters the carrier mobilities in the layers, enabling the fabrication of high-speed and/ or low- power-consumption devices.
- the percentage of Ge in SiGe and the method of deposition can have - . -
- the method includes providing a monocrystalline Si substrate, and then epitaxially growing a graded Si ⁇ Ge.. layer with increasing Ge concentration at a gradient of less than 25% Ge per micrometer to a final Ge composition in the range of 0.K x ⁇ 1, using a source gas of Ge x H y Cl i _ for the Ge component, on the Si substrate at a temperature in excess of 850 °C, and then epitaxially growing a semiconductor material on the graded layer.
- the SiGe layer is, preferably, planarized or smoothed to reduce the surface roughness in the final strained Si substrate.
- Current methods of chemical mechanical polishing (“CMP") are typically used to decrease roughness and improve the planarity of surfaces in semiconductor fabrication processes.
- CMP chemical mechanical polishing
- U.S. Patent No. 6,107,653 "Controlling Threading Dislocations in Ge on Si Using Graded GeSi Layers and Planarization," incorporated herein by reference, describes how planarization can be used to improve the quality of SiGe graded layers.
- One technique suitable for fabricating strained Si wafers can include the following steps: 1.
- compositionally graded layers offer a viable route toward integration of heavily lattice-mismatched monocrystallLne semiconductor layers on a common substrate, offering a route towards increased functionality through monolithic integration.
- MODFETs modulation-doped FETs
- MOSFETs metal-oxide-semiconductor FETs
- CMOS process flows therefore, may not be suitable for these layers because conventional CMOS processes typically result in the consumption of a large portion of surface substrate material. This consumption is primarily due to thermal oxidation steps.
- thin thermally grown oxides are commonly used as screening layers (also called "passivation layers") during ion implantation steps. These passivation layers also serve to discourage out-diffusion of dopants during subsequent thermal anneals.
- thermally grown pad oxides are used as a stress-mediating underlayer beneath a silicon nitride trench mask layer for shallow trench isolation (STI) formation.
- STI shallow trench isolation
- thermal oxidation steps typically remove a total of several hundred angstroms (A) of surface Si material. Accordingly, thermal oxidation is not desirable when processing wafers that incorporate thin surface layers formed on SiGe virtual substrates, where a final minitnum thickness of 50 A of the thin strained layer (from a starting thickness of, e.g., 50 - 200 A) needs to be available for device channels.
- a method for forming a semiconductor structure having a strained semiconductor layer that overcomes the limitations of known methods.
- methods of providing dielectric layers such as, for example, oxide layers, which avoid consuming unacceptably large amounts of the surface material in Si/ SiGe heterostructure-based wafers are proposed to replace or supplement various intermediate CMOS thermal oxidation steps known in the art.
- oxide deposition methods such as chemical vapor deposition (CND)
- arbitrarily thick dielectric layers may be formed with little or no consumption of surface silicon.
- oxide layers such as a screening oxide and pad oxide layers
- oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation.
- the short thermal oxidation consumes little surface Si, and the Si/ oxide interface is of high quality.
- the oxide may then be thickened to a desired final thickness by deposition.
- the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
- a method for forming a semiconductor structure includes forming a strained semiconductor layer over a substrate and depositing a screening layer over at least a portion of a top surface of the strained semiconductor layer.
- the thickness of the strained semiconductor is substantially unchanged following the deposition of the screening layer.
- the strained semiconductor layer is tensilely strained, and includes, for example, a tensilely strained silicon or tensilely strained silicon-germanium alloy.
- the strained semiconductor layer is compressively strained, and includes, for example, compressively strained germanium or compressively strained silicon- germanium alloy.
- the strained layer may have a thickness ranging from about 50 A to about 1000 A, for example, not exceeding about 300 A. In a particular embodiment, the thickness of the strained layer does not exceed about 200 A..
- the substrate may include at least one of silicon and germanium.
- the substrate includes an insulating layer disposed underneath the strained semiconductor layer.
- the substrate includes a relaxed semiconductor layer disposed underneath the strained semiconductor layer.
- the substrate further includes a compositionally graded layer disposed underneath the relaxed semiconductor layer.
- the graded layer may include at least one of a group II, a group III, a group IN, a group N, and a group NI element, for example, at least one of silicon and germanium.
- the graded layer can be graded to a concentration of greater than about 10% germanium and may have thickness ranging from about 0.5 ⁇ m to about 10.0 ⁇ m.
- the step of depositing the screening layer may include chemical vapor deposition.
- the screening layer includes an oxide layer, for example, selected from the group consisting of silicon dioxide, silicon oxynitride, silicon germanium oxide, or germanium oxide.
- the screening layer may have thickness ranging from about 20 A to about 300 A..
- the method further includes introducing dopants into the semiconductor structure, wherein the screening layer affects the introduction of dopants into at least a portion of the structure by at least one of scattering dopants and reducing energy of the dopants.
- the method may also include subjecting the structure to a thermal anneal, wherein the screening layer hinders out-diffusion of the dopants from at least a portion of the substrate.
- an oxide layer is grown over the portion of the top surface of the strained semiconductor layer by, for example, a rapid thermal oxidation. Thickness of the oxide layer may range from about 5 A to about 30 A.
- a method for forming a structure includes forming a strained semiconductor layer over a substrate, depositing a pad oxide layer over at least a portion of a top surface of the strained semiconductor layer; and forming a masking layer over the pad oxide layer.
- the pad oxide layer substantially inhibits formation of stress-induced defects in the strained semiconductor layer.
- the masking layer may include silicon nitride.
- an oxide layer is grown over the portion of the top surface of the strained semiconductor layer, for example, by a rapid thermal oxidation.
- the thickness of the oxide layer may range from about 5 A to about 30 A.
- the substrate includes at least one of silicon and germanium.
- the substrate includes an insulating layer disposed underneath the strained semiconductor layer.
- the substrate includes a relaxed semiconductor layer disposed underneath the strained semiconductor layer.
- the substrate further includes a compositionally graded layer disposed underneath the relaxed semiconductor layer.
- the graded layer may include at least one of a gtoup II, a group III, a group IN, a group N, and a group NI element, for example, at least one of silicon and germanium.
- the graded layer can be graded to a concentration of greater than about 10% germanium and may have thickness ranging from about 0.5 ⁇ m to about 10.0 ⁇ m.
- the strained semiconductor layer may be tensilely strained, and may include, for example, a tensilely strained silicon or tensilely strained silicon-germanium alloy. In another embodiment, the strained semiconductor layer is compressively strained, and includes, for example, compressively strained germanium or compressively strained silicon-germanium alloy. The strained layer may have a thickness ranging from about 50 A to about 1000 A, for example, not exceeding about 300 A. In a particular embodiment, the thickness of the strained layer does not exceed about 200 A. [0022] In various embodiments, thickness of the strained semiconductor is substantially unchanged following the deposition of the pad oxide layer. The pad oxide layer can be deposited by, for example, chemical vapor deposition. The pad oxide layer may include silicon dioxide, silicon oxynitride, silicon germanium oxide, or germanium oxide, and have thickness ranging from about 50 A to about 500 A. BRIEF DESCRIF ⁇ ON OF THE DRAWINGS
- FIGS. 1A -ID depict schematic cross-sectional views of several substrates suitable for fabrication of semiconductor structures according to the embodiments of the invention.
- FIGS. 2A - 2B depict schematic cross-sectional views of a semiconductor substrate having a screening layer formed thereon according to the embodiments of the invention.
- FIGS. 3A - 3B depict schematic cross-sectional views of a semiconductor substrate having a pad oxide layer formed thereon according to the embodiments of the invention.
- MOS MOS
- SiGe Si j .__Ge y
- FIG. 1A which illustrates an epitaxial wafer 100 suitable to use with the present invention
- layers collectively indicated at 101 including a strained layer 102 and a relaxed layer 104, are disposed over a substrate 106.
- the substrate 106 comprises a semiconductor, such as silicon, silicon deposited over an insulator, such as, for example, SiO 2 , or a silicon- germanium alloy.
- the layers 101 are epitaxially grown over the substrate 106.
- the layers 101 and the substrate 106 may be referred to together as a "virtual substrate.”
- the ensuing discussion focuses on a strained layer 102 that is tensilely strained, but it is understood that the strained layer 102 may be tensilely or compressively strained.
- the strained layer 102 has a lattice constant other than the equilibrium lattice constant of d e material from which it is formed, and it may be tensilely or compressively strained;
- the relaxed layer 104 has a lattice constant equal to the equilibrium lattice constant of the material from which it is formed.
- the tensilely strained layer 102 shares an interface 108 with the relaxed layer 104.
- the substrate 106 and the relaxed layer 104 may be formed from various materials systems, including various combinations of group II, group III, group IN, group N, and group NI elements.
- each of the substrate 106 and the relaxed layer 104 may include a III-N compound.
- the substrate 106 may include gallium arsenide (GaAs), and the relaxed layer 104 may include indium gallium arsenide (InGaAs) or aluminum gallium arsenide (AlGaAs). These examples are merely illustrative, and many other material systems are suitable.
- the relaxed layer 104 may include Si j .-.Ge.. with a uniform composition, containing, for example, Ge in the range 0J ⁇ x ⁇ 0.9 and having a thickness T j of, e.g., 0.2 - 2 ⁇ m. In one particular embodiment, ⁇ 1 is about 1.5 ⁇ m.
- the strained layer 102 may include a semiconductor such as at least one of a group II, a group III, a group IN, a group N, and a group NI element.
- the strained semiconductor layer 102 may include, for example, Si, Ge, SiGe, GaAs, indium phosphide (InP), and/ or zinc selenide (ZnSe).
- the strained semiconductor layer 102 may include approximately 100% Ge, and may be compressively strained.
- tensilely strained layer 102 is formed of silicon.
- the tensilely strained layer 102 has a thickness T 2 of, for example, 50 - 1000 A. In a particular embodiment, thickness T 2 is less than about 300 A, preferably below 200 A.
- a thin silicon cap layer may be disposed over strained layer 102. This silicon cap layer may have a thickness of, for example, between about 5 A and about 50 A.
- the epitaxially grown layers 101 can be grown in any suitable epitaxial deposition system, including, but not limited to, atmospheric- pressure CND (APCND), low- (or reduced-) pressure CND (LPCND), ultra-high-vacuum CND (UHNCND), by molecular beam epitaxy (MBE), or by atomic layer deposition (ALD).
- APCND atmospheric- pressure CND
- LPCND low- (or reduced-) pressure CND
- UHNCND ultra-high-vacuum CND
- MBE molecular beam epitaxy
- ALD atomic layer deposition
- the epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. The growth system also may utilize low-energy plasma to enhance the layer growth kinetics.
- Suitable CND systems commonly used for volume epitaxy in manufacturing applications include, for example, EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, CA, or EPSILON single-wafer epitaxial reactors available from ASM International based in Bilthoven, The Netherlands.
- obtaining epitaxial growth typically involves introducing a source gas into the chamber.
- the source gas may include at least one precursor gas and a carrier gas, such as, for example hydrogen.
- silicon precursor gases such as, for example, silane, disilane, trisilane, or dichlorosilane (DCS) trichlorosilane (TCS), or silicon tetrachloride may be used.
- germanium precursor gases such as, for example, germane (GeH 4 ), digermane, germanium tetrachloride, or dichlorogermane, or other Ge-containing precursors may be used.
- germane precursor gases such as, for example, germane (GeH 4 ), digermane, germanium tetrachloride, or dichlorogermane, or other Ge-containing precursors may be used.
- germane precursor gases such as, for example, germane (GeH 4 ), digermane, germanium tetrachloride, or dichlorogermane, or other Ge-containing precursors
- SiGe alloy a combination of silicon and germanium precursor gases in various proportions is used.
- the strained layer 102 may be formed in a dedicated chamber of a deposition tool that is not exposed to Ge source gases, thereby avoiding cross-contamination and improving the quality of the interface 108 between the strained layer 102 and the relaxed layer 104. Furthermore, the strained layer 102 - y -
- relaxed layer 104 and/ or strained layer 102 may be planarized or smoothed to improve the quaUty of subsequent wafer bonding. Planarization or smoothing may be accomplished by CMP or in situ epitaxy-based methods, for example, although other techniques are acceptable as weU.
- the relaxed layer 104 may have a surface roughness less than 1 nm
- the strained layer 102 may have a surface roughness, e.g., less than 0.5 nanometer (nm) root mean square (RMS).
- an epitaxial wafer 200 amenable for use with the present invention may include layers in addition to those indicated in FIG. 1 A.
- several layers coUectively indicated at 202 are disposed over a semiconductor substrate 204 formed from, e.g. silicon.
- the layers 202 may be epitaxiaUy grown by, for example, APCND, LPCND, or UHNCND.
- the layers 202 and the substrate 204 may be referred to together as a "virtual substrate.' 1
- the layers 202 include a graded layer 206 having a thickness T 3 ranging from about 0J ⁇ m to about 10 ⁇ m, is disposed over substrate 204.
- the relaxed layer 104 described above is disposed over the graded layer 206.
- the graded layer 206 includes Si and Ge with a grading rate of, for example, 10% Ge per ⁇ m of thickness, and a thickness ranging from about 2 ⁇ m to about 9 ⁇ m.
- the graded layer 206 includes Si and Ge with a grading rate of, for example, over about 5% Ge per ⁇ m of thickness, and generaUy in the range of >5% Ge/ ⁇ m to 100% Ge/ ⁇ m, preferably between 5% Ge/ ⁇ m and 50% Ge/ ⁇ m, to a final Ge content of between about 10% to about 100%Ge. While the overaU grading rate of the graded layer is generaUy defined as the ratio of total change in Ge content to the total thickness of the layer, a "local grading rate" within a portion of the graded layer may be different from the overaU grading rate.
- a graded layer including a 1 ⁇ m region graded from 0% Ge to 10% Ge (a local grading rate of 10% Ge/ ⁇ m) and a 1 ⁇ m region graded from 10% Ge to 30% Ge (a local grading rate of 20% Ge/ ⁇ m) wiU have an overaU grading rate of 15% Ge/ ⁇ m.
- a relaxed graded layer may not necessarily have a linear profile, but may comprise smaUer regions having different local grading rates.
- the graded layer 206 is grown, for example, at 600 - 1200 °C. Higher growth temperatures, for example, exceeding 900°C may be preferred to enable faster growth rates while minimizing the nucleation of threading dislocations.
- a compressively strained layer 208 including a semiconductor material is disposed over the relaxed layer 104.
- the compressively strained layer 208 includes group IN elements, such as Si j .-.Ge.,, with a Ge content (y) higher than the Ge content (x) of the relaxed (Si ⁇ Ge ⁇ cap layer, for example, in the range 0.25 ⁇ y ⁇ 1.
- the compressively strained layer 208 may contain, for example, 1 - 100% Ge, preferably over 40% Ge, and may have a thickness T 4 ranging from about 10 to about 500 angstroms (A), preferably below 200 A.
- the compressively strained layer 208 includes at least one group III and one group N element, e.g., indium gallium arsenide, indium gallium phosphide, or gallium arsenide.
- the compressively strained layer 160 includes at least one group II and one group NI element, e.g., zinc selenide, zinc sulfide, cadmium teUuride, or mercury teUuride.
- the tensilely strained layer 102 is disposed over the compressively strained layer 208, sharing an interface 210 therewith.
- the compressively strained layer 208 may be disposed not under, but over the tensUely strained layer 102.
- a relaxed constant-composition regrowth layer (not shown) is disposed over the relaxed layer 104, sharing an interface therewith, and a tensUely strained layer is disposed over the constant-composition regrowth layer, sharing an interface with that layer.
- the regrowth layer may, for example, include Si j .-.Ge.. with a uniform composition, containing, e.g., 1 - 100% Ge and having a thickness of, for example, 0.01 - 2 ⁇ m.
- the substrate 206 with layers 202 disposed thereon has a threading dislocation density of 10 4 -10 5 cm "2 .
- an epitaxial wafer 300 amenable for use with the present invention is a strained-semiconductor-on-semiconductor SSOS substrate 302, having a strained layer 102 disposed in contact with a crystalline semiconductor handle wafer.
- the handle wafer may include a bulk semiconductor material, such as silicon.
- the strain of the strained layer 102 is not induced by underlying handle wafer 310, and is independent of any lattice mismatch between the strained layer 102 and die handle wafer 310.
- the strained layer 102 and the handle wafer 310 include the same semiconductor material, e.g., silicon.
- the handle wafer 310 may have a lattice constant equal to a lattice constant of the strained layer 102 in the absence of strain.
- the strained layer 102 may have a strain greater dian approximately 10J
- the strained layer 102 may have been formed by epitaxy, and may have a thickness T2 ranging from approximately 20 A to approximately 1000 A, widi a thickness uniformity of better than approximately ⁇ 10%. In various embodiments, the strained layer 102 may have a thickness uniformity of better than approximately ⁇ 5%.
- the strained layer 102 may have a surface roughness of less than 20 A.
- the SSOS substrate 302 may be formed, as described in U.S. Serial Nos. 10/456,708, 10/456,103, 10/264,935, and 10/629,498, the entire disclosures of each of the four appHcations being incorporated herein by reference.
- the SSOS substrate formation process may include the formation of the strained layer 102 over the substrate 106 as described above with reference to FIG. 1A.
- a cleave plane may be defined in, e.g., the relaxed layer 104.
- the strained layer 102 may be bonded to the handle wafer 310, and a spHt may be induced at the cleave plane. Portions of the relaxed layer 104 remaining on the strained layer 102 may be removed by, e.g., oxidation and/ or wet etching.
- a SSOI wafer 400 has the strained layer 102 disposed over an insulator, such as a dielectric layer 410 formed on a semiconductor substrate 402.
- the SSOI wafer 400 may be formed by methods analogous to the methods described above in the formation of the SSOS wafer 300.
- the dielectric layer 410 may include, for example, SiO 2 .
- the dielectric layer 410 includes a material having a melting point (T.J higher than a T m of pure SiO 2 , i.e., higher than 1700 °C.
- the dielectric layer 410 includes a high-k material with a dielectric constant higher than that of SiO 2 , such as aluminum oxide (Al j O j ), hafnium oxide (HfO j ) or hafnium silicate (HfSiON or HfSiO 4 ).
- the semiconductor substrate 402 includes a semiconductor material such as, for example, Si, Ge, or SiGe.
- the strained layer 102 has a thickness T 2 ranging, for example, from about 50 to about 1000 A, with a thickness uniformity of better than approximately ⁇ 5% and a surface roughness of less than approximately 20 A.
- the dielectric layer 410 has a thickness T 5 selected from a range of, for example, 500 - 3000 A.
- the strained layer 102 includes approximately 100% Si or 100% Ge having one or more of the foUowing material characteristics: misfit dislocation density of, e.g., 0 - 10 5 cm "1 ; a threading dislocation density of about 10-10 7 dislocations/cm 2 ; a surface roughness of approximately 0.01 - 1 nm RMS; and a thickness uniformity across the SOI substrate 400 of better than approximately ⁇ 10% of a mean desired thickness; and a thickness T 2 of less than approximately 200 A.
- the SSOI substrate 400 has a thickness uniformity of better than approximately ⁇ 5% of a mean desired thickness.
- the dielectric layer 410 has a T m greater than that of SiO 2 .
- SSOI substrate 400 may be subjected to high temperatures, i.e., up to 1100 °C. High temperatures may result in the relaxation of strained layer 102 at an interface 430 between strained layer 102 and dielectric layer 410.
- the use of dielectric layer with a T m greater than 1700 °C may help keep strained layer 102 from relaxing at the interface 430 between strained layer 102 and dielectric layer 410 when the SSOI substrate is subjected to high temperatures.
- the misfit dislocation density of the strained layer 102 may be lower than its initial misfit dislocation density.
- the initial dislocation density may be lowered by, for example, performing an etch of a top surface 440 of the strained layer 102.
- This etch may be a wet etch, such as a standard microelectronics clean step such as an RCA SCI, Le., hydrogen peroxide, ammonium hydroxide, and water (H 2 O 2 + NH 4 OH + H 2 O), which at, e.g., 80 °C may remove silicon.
- a screening layer 500 is formed over the strained layer 102 of the semiconductor wafer 550.
- the wafer 550 can be any one of the wafers 100, 200, 300, or 400 described above.
- the screening layer 500 may include an oxygen-containing dielectric layer, for example, an oxide layer, including, but not limited to, silicon dioxide (SiO j ), silicon oxynitride (nitrided SiO ⁇ , silicon germanium oxide (SiGeOj), aluminum oxide (Al 2 O 3 ), or germanium oxide (GeO j ), having a thickness T 4 ranging from about 20 A to about 300 A.
- the screening layer 500 may be another dielectric material, such as silicon nitride or a high-k dielectric material.
- the screening layer 500 is formed by deposition, including CND, such as, for example, APCND, LPCND, or PECND, or by physical deposition methods, such as sputtering.
- the screening layer 500 is formed by atomic layer deposition (ALD).
- ALD atomic layer deposition
- dopants 560 may be introduced into component layers 570 of the wafer 550 to form features such as n-weUs or p-weUs in, e.g., the strained layer 102 and relaxed layer 104 shown in FIG. 1A, for CMOS devices.
- the dopants 560 may be n-type or p-type.
- strained layer 102 includes group IN material such as Si
- n-type dopants for example, arsenic (As), phosphorus (P), or antimony (Sb) may be used.
- p-type dopants may include boron (B) or indium (In).
- the dopants 560 may be introduced by ion implantation.
- the screening layer 500 provides improved protection against contamination by particles, including metal particles. Further, the screening layer 500 affects the introduction of dopants 560 by scattering them during implantation, thereby reducing the probability of ion channeling. FoUowing the introduction of dopants 560, the wafer 550 may be annealed. During the annealing step, the screening layer 500 hinders out-diffusion of dopants 560 from the layers 570.
- an oxide layer 580 may be grown on the strained layer 102 by, e.g., rapid thermal oxidation, prior to the formation of the screening layer 500.
- the oxide layer 580 may include, for example, SiO 2 , nitrided SiO 2 , SiGeO 2 , or GeO 2 , and may have a relatively smaU thickness T 6 , e.g., ranging from about 5 A to about 30 A. Because the oxide layer 580 is relatively thin, its growth does not consume an excessive amount of the strained layer 102. An oxide layer, when grown on silicon, typicaUy consumes a silicon thickness equal to approximately one-half of the thickness of the oxide grown. For example, if the strained layer 102 is predominandy Si, then the growth of the oxide layer 580 with a thickness T 5 of 20 A consumes approximately 10 A of the strained layer 102.
- the growth of the oxide layer 580 prior to the formation of screening layer 500 may be desirable in some embodiments.
- the oxide layer 580 may provide a clean protective coating to strained layer 102, prior to CND, a process that may be not as clean as a conventional thermal growth process.
- the screening layer 500 may be formed at other points during device processing.
- the screening layer 500 may be formed prior to a source and drain implantation, or prior to a threshold implantation before gate dielectric formation.
- a pad oxide layer 600 is formed over the strained layer 102 of the semiconductor wafer 650 as part of the STI process whereby the pad oxide layer 600 is used as a stress-mediating underlayer beneath a silicon nitride trench mask layer for STI formation.
- the wafer 650 can be any one of the wafers 100, 200, 300, or 400 described above with reference to FIGS. 1A-1D.
- the pad oxide layer 600 may be formed by, for example, CND, such as APCND, PECND, LPCND, or high-density plasma (HDP) deposition.
- the pad oxide layer 600 may include an oxide such as Si0 2 , nitrided SiO 2 , SiGeO 2 , or GeO 2 , and may have a thickness T 7 of, e.g., between about 50 A and about 500 A.
- the formation of the pad oxide layer 600 by conventional thermal growth may consume approximately 25 - 250 A of the underlying strained layer 102. In contrast, by depositing the pad oxide layer 600, substantiaUy none of the underlying strained layer 102 is consumed.
- a masking layer 660 is formed thereover.
- the masking layer 660 may include a nitride layer, such as silicon nitride, and may be formed by CND, such as LPCND, PECND, APCND, or HDP CND.
- the masking layer 600 may have a thickness T 7 ranging from about 500 A to about 2000 A.
- the masking layer 660 and the pad oxide layer 600 may be patterned by photoUthography and etching. After the masking layer 660 and the pad oxide layer 600 are patterned, exposed portions of the substrate 650 and the underlying portions of its component layers 670 are etched to define trenches (not shown). A liner oxide may be formed by oxidation or deposition, and the trenches filled with a deposited dielectric to complete STI formation.
- the oxide layer 700 may be grown by, e.g., rapid thermal oxidation on the strained layer 102 prior to the formation of the pad oxide layer 600.
- the oxide layer 700 may include, for example, SiO 2 , SiGeO 2 , or GeO 2 , and may have a relatively smaU diickness T 8 , e.g., ranging between about 5 A and about 30 A. Because the oxide layer 700 is relatively thin, its growth does not consume an excessive amount of the strained layer 102. By thermaUy growing the oxide layer 700 prior to depositing the pad oxide layer 600, the strained layer 102 is protected from potentiaUy unclean deposition processing.
- nMOSFETs n-type metal-oxide-semiconductor field-effect transistors
- pMOSFETs p-type MOSFETs
- CMOS devices CMOS devices
Abstract
Description
Claims
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Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6713810B1 (en) * | 2003-02-10 | 2004-03-30 | Micron Technology, Inc. | Non-volatile devices, and electronic systems comprising non-volatile devices |
DE10310740A1 (en) * | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Method for producing a stress-relaxed layer structure on a non-lattice-matched substrate, and use of such a layer system in electronic and / or optoelectronic components |
KR100605504B1 (en) * | 2003-07-30 | 2006-07-28 | 삼성전자주식회사 | semiconductor device comprising epitaxial layer with low dislocation density and fabricating method of the semiconductor device |
EP1542275A1 (en) * | 2003-12-10 | 2005-06-15 | S.O.I.TEC. Silicon on Insulator Technologies S.A. | A method for improving the quality of a heterostructure |
US7172949B2 (en) * | 2004-08-09 | 2007-02-06 | Micron Technology, Inc. | Epitaxial semiconductor layer and method |
US20060151787A1 (en) * | 2005-01-12 | 2006-07-13 | International Business Machines Corporation | LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTION |
CN100481345C (en) * | 2005-02-24 | 2009-04-22 | 硅绝缘体技术有限公司 | Thermal oxidation of a SiGe layer and applications thereof |
JP4654710B2 (en) * | 2005-02-24 | 2011-03-23 | 信越半導体株式会社 | Manufacturing method of semiconductor wafer |
JP4975974B2 (en) * | 2005-03-18 | 2012-07-11 | ラピスセミコンダクタ株式会社 | SOS wafer and manufacturing method thereof |
TWI259534B (en) * | 2005-05-20 | 2006-08-01 | Ind Tech Res Inst | Method for fabricating semiconductor device |
FR2887367B1 (en) * | 2005-06-15 | 2008-06-27 | Soitec Silicon On Insulator | METHOD OF MAINTAINING THE STRESS IN A SERIOUS ISLAND IN A CONCEALED THIN LAYER AND STRUCTURE OBTAINED BY CARRYING OUT THE PROCESS |
FR2891281B1 (en) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM ELEMENT |
US7648853B2 (en) * | 2006-07-11 | 2010-01-19 | Asm America, Inc. | Dual channel heterostructure |
JP5018066B2 (en) * | 2006-12-19 | 2012-09-05 | 信越半導体株式会社 | Method for manufacturing strained Si substrate |
DE102007004862B4 (en) * | 2007-01-31 | 2014-01-30 | Globalfoundries Inc. | A method of fabricating Si-Ge containing drain / source regions in lower Si / Ge loss transistors |
JP2008198656A (en) * | 2007-02-08 | 2008-08-28 | Shin Etsu Chem Co Ltd | Method of manufacturing semiconductor substrate |
US7910468B1 (en) * | 2007-06-04 | 2011-03-22 | Arizona Board of Regents, A Body of the State of Arizona Acting for and on Behalf of Arizona State University | Methods and compositions for preparing Ge/Si semiconductor substrates |
US7955936B2 (en) * | 2008-07-14 | 2011-06-07 | Chartered Semiconductor Manufacturing Ltd. | Semiconductor fabrication process including an SiGe rework method |
US8981427B2 (en) * | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
KR101666403B1 (en) * | 2010-06-09 | 2016-10-17 | 삼성전자 주식회사 | Fabricating method of semiconductor device |
DE102010046215B4 (en) | 2010-09-21 | 2019-01-03 | Infineon Technologies Austria Ag | Semiconductor body with strained region, electronic component and a method for producing the semiconductor body. |
DE102010064280B4 (en) * | 2010-12-28 | 2012-08-30 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | A method of reducing the defect rates in PFET transistors comprising a Si / GE semiconductor material by providing a gradual Ge concentration, and corresponding PFET transistors |
CN102136428B (en) * | 2011-01-25 | 2012-07-25 | 北京大学 | Preparation method of germanium-based Schottky N-type field effect transistor |
US9362123B2 (en) * | 2012-12-21 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for integrated devices on different substartes with interfacial engineering |
KR102069275B1 (en) | 2013-06-07 | 2020-01-22 | 삼성전자주식회사 | Semiconductor device having strained channel layer and method of manufacturing the same |
KR102104062B1 (en) | 2013-10-31 | 2020-04-23 | 삼성전자 주식회사 | Substrate structure, complementary metal oxide semiconductor device and method of manufacturing complementary metal oxide semiconductor |
US20150340228A1 (en) * | 2014-05-14 | 2015-11-26 | Tokyo Electron Limited | Germanium-containing semiconductor device and method of forming |
US20160225641A1 (en) * | 2015-01-29 | 2016-08-04 | International Business Machines Corporation | Defect reduction in iii-v semiconductor epitaxy through capped high temperature annealing |
CN110459479B (en) * | 2018-05-07 | 2021-07-13 | 北京北方华创微电子装备有限公司 | Barrier layer deposition method, bottom metal film of gold bump and preparation method thereof |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0143656B1 (en) * | 1983-11-29 | 1989-02-22 | Fujitsu Limited | Compound semiconductor device and method of producing it |
US4764248A (en) * | 1987-04-13 | 1988-08-16 | Cypress Semiconductor Corporation | Rapid thermal nitridized oxide locos process |
US4906585A (en) * | 1987-08-04 | 1990-03-06 | Siemens Aktiengesellschaft | Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches |
JPH03259524A (en) * | 1989-12-29 | 1991-11-19 | Oki Electric Ind Co Ltd | Forming method of insulating film |
US5442205A (en) | 1991-04-24 | 1995-08-15 | At&T Corp. | Semiconductor heterostructure devices with strained semiconductor layers |
US5221413A (en) * | 1991-04-24 | 1993-06-22 | At&T Bell Laboratories | Method for making low defect density semiconductor heterostructure and devices made thereby |
US5726087A (en) | 1992-04-30 | 1998-03-10 | Motorola, Inc. | Method of formation of semiconductor gate dielectric |
JP3234084B2 (en) * | 1993-03-03 | 2001-12-04 | 株式会社東芝 | Fine pattern forming method |
US5565690A (en) | 1995-02-02 | 1996-10-15 | Motorola, Inc. | Method for doping strained heterojunction semiconductor devices and structure |
EP0838858B1 (en) * | 1996-09-27 | 2002-05-15 | Infineon Technologies AG | CMOS integrated circuit and method of manufacturing the same |
US5780922A (en) | 1996-11-27 | 1998-07-14 | The Regents Of The University Of California | Ultra-low phase noise GE MOSFETs |
US6033974A (en) * | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
DE69827824T3 (en) | 1997-06-24 | 2009-09-03 | Massachusetts Institute Of Technology, Cambridge | CONTROL OF SEVENING DENSITY THROUGH THE USE OF GRADIENT LAYERS AND BY PLANARIZATION |
US6232138B1 (en) * | 1997-12-01 | 2001-05-15 | Massachusetts Institute Of Technology | Relaxed InxGa(1-x)as buffers |
TW415103B (en) * | 1998-03-02 | 2000-12-11 | Ibm | Si/SiGe optoelectronic integrated circuits |
IT1301729B1 (en) | 1998-06-16 | 2000-07-07 | St Microelectronics Srl | PROCESS FOR THE SELECTIVE DRUGING OF A SLICE OF SEMI-CONDUCTOR MATERIALS BY IONIC IMPLANTATION. |
US6511921B1 (en) * | 1999-01-12 | 2003-01-28 | Sumco Phoenix Corporation | Methods for reducing the reactivity of a semiconductor substrate surface and for evaluating electrical properties of a semiconductor substrate |
JP2003517726A (en) | 1999-09-20 | 2003-05-27 | アンバーウェーブ システムズ コーポレイション | Fabrication method of relaxed silicon germanium layer |
US7041170B2 (en) | 1999-09-20 | 2006-05-09 | Amberwave Systems Corporation | Method of producing high quality relaxed silicon germanium layers |
JP4269541B2 (en) * | 2000-08-01 | 2009-05-27 | 株式会社Sumco | Semiconductor substrate, field effect transistor, method of forming SiGe layer, method of forming strained Si layer using the same, and method of manufacturing field effect transistor |
JP2004519090A (en) * | 2000-08-07 | 2004-06-24 | アンバーウェーブ システムズ コーポレイション | Gate technology for strained surface channel and strained buried channel MOSFET devices |
JP2004531901A (en) * | 2001-06-21 | 2004-10-14 | マサチューセッツ インスティテュート オブ テクノロジー | MOSFET with strained semiconductor layer |
US6730551B2 (en) * | 2001-08-06 | 2004-05-04 | Massachusetts Institute Of Technology | Formation of planar strained layers |
US6838728B2 (en) * | 2001-08-09 | 2005-01-04 | Amberwave Systems Corporation | Buried-channel devices and substrates for fabrication of semiconductor-based devices |
EP1428262A2 (en) * | 2001-09-21 | 2004-06-16 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US7074623B2 (en) * | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US6680496B1 (en) * | 2002-07-08 | 2004-01-20 | Amberwave Systems Corp. | Back-biasing to populate strained layer quantum wells |
WO2004012243A2 (en) * | 2002-07-29 | 2004-02-05 | Amberwave Systems | Selective placement of dislocation arrays |
US7594967B2 (en) * | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
-
2003
- 2003-10-30 AU AU2003304129A patent/AU2003304129A1/en not_active Abandoned
- 2003-10-30 JP JP2004571905A patent/JP4949628B2/en not_active Expired - Lifetime
- 2003-10-30 WO PCT/US2003/034576 patent/WO2004102635A2/en active Application Filing
- 2003-10-30 EP EP03816979A patent/EP1593145A2/en not_active Withdrawn
- 2003-10-30 US US10/696,994 patent/US7071014B2/en not_active Expired - Lifetime
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2005
- 2005-05-19 US US11/132,856 patent/US7208332B2/en not_active Expired - Lifetime
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2006
- 2006-03-09 US US11/371,687 patent/US7202121B2/en not_active Expired - Lifetime
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2007
- 2007-02-06 US US11/702,825 patent/US7416909B2/en not_active Expired - Lifetime
- 2007-02-09 US US11/704,464 patent/US7541208B2/en not_active Expired - Lifetime
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US20070161196A1 (en) | 2007-07-12 |
US7202121B2 (en) | 2007-04-10 |
EP1593145A2 (en) | 2005-11-09 |
JP4949628B2 (en) | 2012-06-13 |
US20070042538A1 (en) | 2007-02-22 |
US7416909B2 (en) | 2008-08-26 |
US7541208B2 (en) | 2009-06-02 |
AU2003304129A1 (en) | 2004-12-03 |
AU2003304129A8 (en) | 2004-12-03 |
US20080020551A1 (en) | 2008-01-24 |
WO2004102635A3 (en) | 2005-06-02 |
US7071014B2 (en) | 2006-07-04 |
JP2006511096A (en) | 2006-03-30 |
US20040092051A1 (en) | 2004-05-13 |
WO2004102635A2 (en) | 2004-11-25 |
US20050215069A1 (en) | 2005-09-29 |
US7208332B2 (en) | 2007-04-24 |
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