WO2005001840A2 - Mirror image non-volatile memory cell transistor pairs with single poly layer - Google Patents
Mirror image non-volatile memory cell transistor pairs with single poly layer Download PDFInfo
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- WO2005001840A2 WO2005001840A2 PCT/US2004/015651 US2004015651W WO2005001840A2 WO 2005001840 A2 WO2005001840 A2 WO 2005001840A2 US 2004015651 W US2004015651 W US 2004015651W WO 2005001840 A2 WO2005001840 A2 WO 2005001840A2
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- transistors
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- 238000007667 floating Methods 0.000 claims abstract description 35
- 238000003860 storage Methods 0.000 claims abstract description 13
- 230000005641 tunneling Effects 0.000 claims abstract description 7
- 239000002356 single layer Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 13
- 239000010410 layer Substances 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000002784 hot electron Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000005055 memory storage Effects 0.000 claims 1
- 238000010276 construction Methods 0.000 description 10
- 238000002955 isolation Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000007943 implant Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- PWPJGUXAGUPAHP-UHFFFAOYSA-N lufenuron Chemical compound C1=C(Cl)C(OC(F)(F)C(C(F)(F)F)F)=CC(Cl)=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F PWPJGUXAGUPAHP-UHFFFAOYSA-N 0.000 description 2
- 230000035508 accumulation Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
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- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
Definitions
- the invention relates to non-volatile memory transistors and, in particular, to a compact arrangement of such memory cells for an array and a method of making them.
- MOS nonvolatile memory transistor construction wherein a pair of transistors shares a common well in a semiconductor substrate for subsurface electrode formation in a memory array, whereby two compact transistors can be formed in place of one in most prior art arrays.
- This is achieved by construction of pairs of floating polysilicon gate transistors facing each other, with underlying channels and laterally adjacent subsurface sources and drains for each floating gate transistor.
- the floating gates extend back to form a capacitive relation with a word line and forward to form a band-to-band tunneling relation with the subsurface electrodes.
- a non-volatile memory array described in top projection by orthogonal stripes has parallel pairs of stripes in one direction, being word lines, and pairs of stripes in the orthogonal direction, being bit lines, the intersection resembling a tic-tac-toe pattern.
- the pair of MOS memory transistors is formed using only a single layer of poly for floating gate formation, with each floating gate extending from a respective word line to which it is electrically coupled.
- Sources and drains are symmetrically formed on opposite lateral sides of the forward portion of the poly but within the semiconductor substrate . The sources and drains are in contact with two parallel bit lines.
- the bit lines may be phased to provide a high electrode and a low electrode, with the transistor channel therebetween, and then reversed in polarity.
- the voltage between source and drain in the write mode is low, yet sufficient to generate hot electrons that are driven to the floating gate. While the sources and drains are laterally symmetric, the pair of memory transistors are symmetric about an imaginary line running across the center of the pattern, parallel to the word lines.
- the array is suitable for use as a flash memory.
- FIG. 3 is a top projection of a pair of facing memory transistors illustrating construction of two adjacent symmetric memory cells in the memory array of Fig. 2.
- Figs. 4-11 are side sectional views taken along lines A-A in Fig. 3 illustrating progressive construction steps for making two adjacent symmetric memory cells.
- Fig. 12 is a side sectional view taken along lines B-B in Fig. 3 illustrating construction steps for making two adjacent symmetric memory cells.
- Fig. 13 is a side sectional view taken along lines C-C in Fig. 3 illustrating construction of a single memory transistor having a single poly layer.
- a MOS memory array featuring a plurality of memory transistors 11, 13, 15, 21, 23, 25, 31, 33, 35, and so on.
- Memory transistors 11, 13 and 15 are aligned in a first column 102.
- Memory transistors 21, 23 and 25 are aligned in a second column 104.
- Memory transistors 31, 33, and 35 are aligned in a third column 106.
- Memory transistors 11, 21, and 31 are aligned in a first row.
- Memory transistors 13, 23 and 33 are aligned in a second row.
- Memory transistors 15, 25 and 35 are aligned in a third row, and so on.
- Each memory transistor, such as memory transistor 11, includes a capacitor 12 associated with a floating gate transistor 14.
- Each floating gate transistor in a column is connected between two bit lines, including a first bit line 10 and a second bit line 20 in the column with memory transistors 11, 13 and 15.
- two bit lines 16 and 18 are associated with the next column having memory transistors 21, 23 and 25 with bit line 16 on the left side of the memory transistors and bit line 18 on the right side.
- two memory transistors 11 and 13 are symmetrically built together, as explained below, in a transistor region indicated by dashed line 100.
- the two devices 11 and 13 are independent, but in construction the two devices are constructed almost like a single device, as described below.
- a first word line 22 is associated with a first row of memory transistors 11, 21, 31, and so on.
- a second word line 24 is associated with a second row of memory transistors 13, 23 and 33 .
- Each word line such as the zero order word line 22, is connected to a capacitor 12 associated with memory transistor 14.
- Capacitor 12 is illustrated like a transistor because it is fabricated like a transistor, but with the substrate bulk or body connected to source and drain electrodes, using processes to define a capacitor plate 26 which, with an extension, explained below, forms gate 28 of transistor 14.
- Gate 28 is a floating gate, i.e. a charge storage structure where charge, or lack of charge, is indicative of the state of the transistor.
- a sense amplifier, associated with each word line, not shown, is used to read the state of the floating gate.
- Each charge storage transistor can be addressed individually using row and column decoders, not shown, connected to sense transistors.
- Source 32 of transistor 14 is connected to the zero order bit line with phase one, 10, while drain 34 is connected to the zero order bit line with phase two, 20. Phasing of the bit lines in optional. Other voltage application schemes are known in the art.
- Figs. 2 and 3 active regions of devices are shown, with Fig. 2 showing an array and Fig. 3 showing the top projection within dashed line 100 of Fig. 2 and of Fig. 1. Regions outside of the active regions are separated by isolation techniques, such as shallow trench isolation (STI) , LOCOS oxidation, or similar techniques.
- STI shallow trench isolation
- a first n-t- implant into the substrate establishes all of the word lines as parallel stripes, shaded by forward diagonal lines, including first word line 22 WL0 ( ⁇ l) and second word line 24 WL0 ( ⁇ 2) .
- the word lines are co-extensive with the width of the array.
- an n- well implant is made, defining a region 30, shaded by regular stippling, where two symmetric memory transistors will be built.
- This implant has an almost square shape with a length approximately twice the length of each of the two memory transistors that are mirror-image symmetric relative to an imaginary line M, shown as a wavy line, joining contacts 36 and 38.
- each of the bit lines 10 and 20 has associated implanted source and drain regions, forming source and drain electrodes 32 and 34, respectively, for transistor 14, with similar implanted electrodes for its mirror-image partner, transistor 30.
- Each memory cell has a T-shaped deposit of polysilicon over the oxide covering the substrate, most clearly seen in Fig. 2.
- the T-shape is shaded with short parallel segments, with each poly deposit having a T-base 42 in both Figs. 2 and 3, and a T-top 40 superposed over the word line.
- the T-top 40 is a stripe deposit parallel to the word line 22 and is generally superposed over the word line 22 orthogonal to bit lines 10 and 20.
- a single poly T-shape layer 81 is seen to have a T-top 83 and a T-base 85.
- the T-base 42 has an underlying oxide layer spacing the T- base 42 from the substrate, with source 32 and drain 34 on opposite lateral sides of the T-base.
- the T-top acts in capacitive relation with the underlying word line, conducting during forward bias conditions.
- Two symmetric memory transistors are built in N-well region 30, namely transistors 11 and 13 seen in Fig. 1, with the two transistors mirrored across an imaginary line M in Fig. 3 which is parallel to two adjacent word lines and midway therebetween.
- the two transistors have sources 32 and drains 34 which are implanted into the N-well after the T-base is constructed, so that sources and drains are self- aligned with the poly T-base.
- substrate 10 is seen having shallow trench isolation (STI) regions 51-55 for two facing memory cells, including the transistors proximate to T-base 42 and T-base 44 in Fig. 3, with supporting word and bit lines.
- STI regions are boundaries or walls that define active areas as regions between STI boundaries and are formed after the initial doping of the substrate.
- N-well photomask portions 56 and 57 are placed over left and right zones of the two facing memory cells, leaving open a central zone between the marks so that an ion beam, I, can deliver negative ions implanted in regions 58 and 59.
- the implant has been driven into the substrate such that the depth of N-well 61 extends at least to the depth of trench 53 and extends between trenches 52 and 54. At this depth, the N-well can be shared by two symmetric memory transistors, with one to be built on each side of isolation region 53.
- photomask portions 56 and 57 have been removed .
- Fig. 5 N-well photomask portions 56 and 57 are placed over left and right zones of the two facing memory cells, leaving open a central zone between the marks so that an ion beam, I, can deliver negative ions implanted in regions 58 and 59.
- the implant has been driven into the substrate such that the depth of N-well 61 extends at least to the depth of trench 53 and extends between trenches 52 and 54
- a photomask 63 is applied over the N-well and ion beams J and K deliver a concentration of negative ions into regions 65 and 67 for establishing word lines 24 and 22 in Fig. 3.
- the implanted regions are driven in so that word lines 24 and 22 are seen in the p-substrate 10.
- the word lines are linear, running across the width of the memory array, as seen in
- Fig. 2 Active regions of the substrate are covered with gate oxide 69 to a thickness of 50-80 Angstroms, as seen in Fig. 9.
- the gate oxide layer 69 will insulate the n- well 67 and its contents from a polysilicon layer 71, seen in Fig. 10, having a thickness of 1500-2000 Angstroms.
- the poly layer 71 behaves as one plate of a capacitor, as previously mentioned.
- the second plate of the capacitor is the associated word line. This is a T- top region of the poly.
- the poly region furthest from the word line is the T-base region, forming the floating gate of a transistor with nearby source and drain in the substrate. Later, the poly layer 71 is masked, as seen in Fig.
- a deposition of inter-layer dielectric material 79 is placed over poly 71 with a central opening 81. This opening will be used for a metal plug to make contact with the bit line.
- the metal filler is shown as contact 36 in Fig. 3.
- the polysilicon region 71 a floating gate, is the T-base 42 in Fig. 3.
- the floating gate is spaced between two p+ diffusions or implants 83 and 85 in the N-well 61. Recall that the T-base region is spaced from the substrate by gate oxide and is, therefore, electrically floating.
- the source and drain regions 83 and 85 extend laterally away from the T-base region toward the bit lines 10 and 20 seen in Fig. 3.
- the bit lines bias control conduction in the channel by setting the threshold voltage. Voltages on the source and drain can bias junctions to induce band-to-band tunneling relative to the floating gate. Charge accumulations trapped on the floating gate indicate a memory state.
- the bit line is used to sense the state of charge of the floating gate. Band-to-band tunneling occurs partly because of the small dimensions of the cell and appropriate concentration of dopants in regions 83, 85 and 61.
- the channel length is approximately 0.25-0.35 microns, while the distance between STI regions 54 are defined by minimum design rules of whatever processing technology is used. In this tight environment, holes in the source or drain become sufficiently energetic to cause electrons to be pulled from the floating gate. Alternatively, hot electrons can be placed on the floating gate with an opposite bias.
- the invention was described with reference to a p-substrate with an N-well. These polarities could have been reversed. In operation, relatively low voltages may be used to program the memory transistors, such as 2.5V.
- High voltages such as 5V may be used in the interior of the chip.
- the left and right bit lines are not held at the same voltage for program and erase, but are phase alternates relative to ground. Phase alternating allows the two mirror-image transistors to share the same source and drain. Examples of voltages are as follows:
- PROGRAM READ (ROW) BLOCK ⁇ R BL0 (L) +5V +2.5V -5V BL0 (R) Floating 0V -5V WL0 +5V OV +2.5V to +5V N-WELL +5V +3V to +5V 0V P-SUBS ov 0V OV BL1 (L) +5V -5V BL1 (R) Floating -5V WL1 OV +2.5V to +5V N-WELL +5V OV P-SUBS OV OV BLN (L) OV +2.5V -5V PROGRAM READ (ROW) BLOCK ERASE BLN (R) OV OV -5V WLN OV +2.5V to +5V N-WELL OV +3V to +5V 0V P-SUBS OV +3V OV OV
- block erase and erase are the same except that in block erase, the N-well and the p-substrate are held at ground.
- the block erase mode enables the array to operate similar to a flash EEPROM.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04752639A EP1636849A2 (en) | 2003-06-18 | 2004-05-18 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/465,718 US6888192B2 (en) | 2003-04-25 | 2003-06-18 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
US10/465,718 | 2003-06-18 |
Publications (2)
Publication Number | Publication Date |
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WO2005001840A2 true WO2005001840A2 (en) | 2005-01-06 |
WO2005001840A3 WO2005001840A3 (en) | 2005-11-24 |
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PCT/US2004/015651 WO2005001840A2 (en) | 2003-06-18 | 2004-05-18 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
Country Status (5)
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US (2) | US6888192B2 (en) |
EP (1) | EP1636849A2 (en) |
CN (1) | CN100454574C (en) |
TW (1) | TW200511319A (en) |
WO (1) | WO2005001840A2 (en) |
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US6888192B2 (en) * | 2003-04-25 | 2005-05-03 | Atmel Corporation | Mirror image non-volatile memory cell transistor pairs with single poly layer |
US6998670B2 (en) * | 2003-04-25 | 2006-02-14 | Atmel Corporation | Twin EEPROM memory transistors with subsurface stepped floating gates |
US20070247915A1 (en) * | 2006-04-21 | 2007-10-25 | Intersil Americas Inc. | Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide |
US7688627B2 (en) * | 2007-04-24 | 2010-03-30 | Intersil Americas Inc. | Flash memory array of floating gate-based non-volatile memory cells |
US7903465B2 (en) * | 2007-04-24 | 2011-03-08 | Intersil Americas Inc. | Memory array of floating gate-based non-volatile memory cells |
US7773423B1 (en) * | 2007-09-27 | 2010-08-10 | National Semiconductor Corporation | Low power, CMOS compatible non-volatile memory cell and related method and memory array |
KR101087830B1 (en) * | 2009-01-05 | 2011-11-30 | 주식회사 하이닉스반도체 | Layout of semiconductor device |
CN107293582B (en) * | 2017-07-10 | 2020-04-24 | 东南大学 | Silicon-based BJT device with thermoelectric conversion function and oriented to Internet of things |
KR102472339B1 (en) * | 2017-08-07 | 2022-12-01 | 에스케이하이닉스 주식회사 | Three dimensional semiconductor memory device |
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US6888192B2 (en) * | 2003-04-25 | 2005-05-03 | Atmel Corporation | Mirror image non-volatile memory cell transistor pairs with single poly layer |
US6998670B2 (en) * | 2003-04-25 | 2006-02-14 | Atmel Corporation | Twin EEPROM memory transistors with subsurface stepped floating gates |
US7098106B2 (en) * | 2004-07-01 | 2006-08-29 | Atmel Corporation | Method of making mirror image memory cell transistor pairs featuring poly floating spacers |
-
2003
- 2003-06-18 US US10/465,718 patent/US6888192B2/en not_active Expired - Fee Related
-
2004
- 2004-05-18 CN CNB2004800234634A patent/CN100454574C/en not_active Expired - Fee Related
- 2004-05-18 EP EP04752639A patent/EP1636849A2/en not_active Withdrawn
- 2004-05-18 WO PCT/US2004/015651 patent/WO2005001840A2/en active Search and Examination
- 2004-06-14 TW TW093117034A patent/TW200511319A/en unknown
-
2005
- 2005-03-21 US US11/085,387 patent/US20050164452A1/en not_active Abandoned
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US5406521A (en) * | 1992-10-30 | 1995-04-11 | Nec Corporation | Semiconductor memory device and data erase method for it |
US5487034A (en) * | 1993-09-27 | 1996-01-23 | Nec Corporation | Semiconductor memory device and method for writing data therein |
US5808338A (en) * | 1994-11-11 | 1998-09-15 | Nkk Corporation | Nonvolatile semiconductor memory |
US6343031B1 (en) * | 2000-07-14 | 2002-01-29 | Oki Electric Industry Co., Ltd. | Semiconductor memory device |
US20030199143A1 (en) * | 2002-04-16 | 2003-10-23 | Hung-Sui Lin | Method for fabricating non-volatile memory having P-type floating gate |
Also Published As
Publication number | Publication date |
---|---|
TW200511319A (en) | 2005-03-16 |
CN100454574C (en) | 2009-01-21 |
CN1836336A (en) | 2006-09-20 |
US6888192B2 (en) | 2005-05-03 |
WO2005001840A3 (en) | 2005-11-24 |
EP1636849A2 (en) | 2006-03-22 |
US20040212004A1 (en) | 2004-10-28 |
US20050164452A1 (en) | 2005-07-28 |
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