WO2005001937A3 - One transistor flash memory cell - Google Patents

One transistor flash memory cell Download PDF

Info

Publication number
WO2005001937A3
WO2005001937A3 PCT/EP2004/051254 EP2004051254W WO2005001937A3 WO 2005001937 A3 WO2005001937 A3 WO 2005001937A3 EP 2004051254 W EP2004051254 W EP 2004051254W WO 2005001937 A3 WO2005001937 A3 WO 2005001937A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cell
flash memory
memory
bit line
memory array
Prior art date
Application number
PCT/EP2004/051254
Other languages
French (fr)
Other versions
WO2005001937A2 (en
Inventor
Ronald Kakoschke
Georg Tempel
Danny Shum
Original Assignee
Infineon Technologies Ag
Ronald Kakoschke
Georg Tempel
Danny Shum
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Ronald Kakoschke, Georg Tempel, Danny Shum filed Critical Infineon Technologies Ag
Priority to DE112004001244T priority Critical patent/DE112004001244B4/en
Priority to EP04741900A priority patent/EP1639638B1/en
Publication of WO2005001937A2 publication Critical patent/WO2005001937A2/en
Publication of WO2005001937A3 publication Critical patent/WO2005001937A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

An integrated circuit has a high voltage area, a logie area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.
PCT/EP2004/051254 2003-06-27 2004-06-25 One transistor flash memory cell WO2005001937A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112004001244T DE112004001244B4 (en) 2003-06-27 2004-06-25 Semiconductor device with a field of flash memory cells and process
EP04741900A EP1639638B1 (en) 2003-06-27 2004-06-25 Flash memory cell array

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/607,610 2003-06-27
US10/607,610 US6909139B2 (en) 2003-06-27 2003-06-27 One transistor flash memory cell

Publications (2)

Publication Number Publication Date
WO2005001937A2 WO2005001937A2 (en) 2005-01-06
WO2005001937A3 true WO2005001937A3 (en) 2005-04-07

Family

ID=33540312

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/051254 WO2005001937A2 (en) 2003-06-27 2004-06-25 One transistor flash memory cell

Country Status (5)

Country Link
US (2) US6909139B2 (en)
EP (1) EP1639638B1 (en)
KR (1) KR100760755B1 (en)
DE (2) DE112004003060B4 (en)
WO (1) WO2005001937A2 (en)

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US8906764B2 (en) 2012-01-04 2014-12-09 Freescale Semiconductor, Inc. Non-volatile memory (NVM) and logic integration
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US9111865B2 (en) 2012-10-26 2015-08-18 Freescale Semiconductor, Inc. Method of making a logic transistor and a non-volatile memory (NVM) cell
US9006093B2 (en) 2013-06-27 2015-04-14 Freescale Semiconductor, Inc. Non-volatile memory (NVM) and high voltage transistor integration
US8877585B1 (en) * 2013-08-16 2014-11-04 Freescale Semiconductor, Inc. Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration
US9129996B2 (en) 2013-07-31 2015-09-08 Freescale Semiconductor, Inc. Non-volatile memory (NVM) cell and high-K and metal gate transistor integration
US8871598B1 (en) 2013-07-31 2014-10-28 Freescale Semiconductor, Inc. Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology
US9082837B2 (en) 2013-08-08 2015-07-14 Freescale Semiconductor, Inc. Nonvolatile memory bitcell with inlaid high k metal select gate
US9082650B2 (en) 2013-08-21 2015-07-14 Freescale Semiconductor, Inc. Integrated split gate non-volatile memory cell and logic structure
US9252246B2 (en) 2013-08-21 2016-02-02 Freescale Semiconductor, Inc. Integrated split gate non-volatile memory cell and logic device
US9275864B2 (en) 2013-08-22 2016-03-01 Freescale Semiconductor,Inc. Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates
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US9129855B2 (en) 2013-09-30 2015-09-08 Freescale Semiconductor, Inc. Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology
US9136129B2 (en) 2013-09-30 2015-09-15 Freescale Semiconductor, Inc. Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology
US8901632B1 (en) 2013-09-30 2014-12-02 Freescale Semiconductor, Inc. Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology
US9231077B2 (en) 2014-03-03 2016-01-05 Freescale Semiconductor, Inc. Method of making a logic transistor and non-volatile memory (NVM) cell
US9472418B2 (en) 2014-03-28 2016-10-18 Freescale Semiconductor, Inc. Method for forming a split-gate device
US9112056B1 (en) 2014-03-28 2015-08-18 Freescale Semiconductor, Inc. Method for forming a split-gate device
US9379222B2 (en) 2014-05-30 2016-06-28 Freescale Semiconductor, Inc. Method of making a split gate non-volatile memory (NVM) cell
US9343314B2 (en) 2014-05-30 2016-05-17 Freescale Semiconductor, Inc. Split gate nanocrystal memory integration
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Also Published As

Publication number Publication date
EP1639638A2 (en) 2006-03-29
KR20060029153A (en) 2006-04-04
EP1639638B1 (en) 2011-05-11
DE112004003060B4 (en) 2015-09-03
DE112004001244B4 (en) 2009-02-05
US20050180215A1 (en) 2005-08-18
US7190022B2 (en) 2007-03-13
WO2005001937A2 (en) 2005-01-06
KR100760755B1 (en) 2007-09-21
US6909139B2 (en) 2005-06-21
DE112004001244T5 (en) 2006-06-01
US20040262669A1 (en) 2004-12-30

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