WO2005004200A3 - Lead frame routed chip pads for semiconductor packages - Google Patents

Lead frame routed chip pads for semiconductor packages Download PDF

Info

Publication number
WO2005004200A3
WO2005004200A3 PCT/US2004/019523 US2004019523W WO2005004200A3 WO 2005004200 A3 WO2005004200 A3 WO 2005004200A3 US 2004019523 W US2004019523 W US 2004019523W WO 2005004200 A3 WO2005004200 A3 WO 2005004200A3
Authority
WO
WIPO (PCT)
Prior art keywords
array
chip
lead frame
sites
conductive substrate
Prior art date
Application number
PCT/US2004/019523
Other languages
French (fr)
Other versions
WO2005004200A2 (en
Inventor
Shafidul Islam
San Antonio Romarico Santos
Anang Subagio
Original Assignee
Advanced Interconnect Tech Ltd
Shafidul Islam
San Antonio Romarico Santos
Anang Subagio
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Interconnect Tech Ltd, Shafidul Islam, San Antonio Romarico Santos, Anang Subagio filed Critical Advanced Interconnect Tech Ltd
Priority to US10/561,381 priority Critical patent/US7795710B2/en
Priority to JP2006517395A priority patent/JP2007521656A/en
Priority to EP04755609A priority patent/EP1652227A2/en
Publication of WO2005004200A2 publication Critical patent/WO2005004200A2/en
Publication of WO2005004200A3 publication Critical patent/WO2005004200A3/en
Priority to US11/986,620 priority patent/US7820480B2/en
Priority to US12/843,183 priority patent/US8304864B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36). This process is particularly suited for the manufacture of chip scale packages and very thin packages.
PCT/US2004/019523 2003-06-25 2004-06-18 Lead frame routed chip pads for semiconductor packages WO2005004200A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/561,381 US7795710B2 (en) 2003-06-25 2004-06-18 Lead frame routed chip pads for semiconductor packages
JP2006517395A JP2007521656A (en) 2003-06-25 2004-06-18 Lead frame routed chip pads for semiconductor packages
EP04755609A EP1652227A2 (en) 2003-06-25 2004-06-18 Lead frame routed chip pads for semiconductor packages
US11/986,620 US7820480B2 (en) 2003-06-25 2007-11-21 Lead frame routed chip pads for semiconductor packages
US12/843,183 US8304864B2 (en) 2003-06-25 2010-07-26 Lead frame routed chip pads for semiconductor packages

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US48252703P 2003-06-25 2003-06-25
US60/482,527 2003-06-25

Related Child Applications (3)

Application Number Title Priority Date Filing Date
US10561381 A-371-Of-International 2004-06-18
US11/986,620 Division US7820480B2 (en) 2003-06-25 2007-11-21 Lead frame routed chip pads for semiconductor packages
US12/843,183 Continuation-In-Part US8304864B2 (en) 2003-06-25 2010-07-26 Lead frame routed chip pads for semiconductor packages

Publications (2)

Publication Number Publication Date
WO2005004200A2 WO2005004200A2 (en) 2005-01-13
WO2005004200A3 true WO2005004200A3 (en) 2006-02-16

Family

ID=33563865

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/019523 WO2005004200A2 (en) 2003-06-25 2004-06-18 Lead frame routed chip pads for semiconductor packages

Country Status (7)

Country Link
US (2) US7795710B2 (en)
EP (1) EP1652227A2 (en)
JP (1) JP2007521656A (en)
KR (1) KR20060079754A (en)
CN (1) CN100463125C (en)
TW (1) TWI334213B (en)
WO (1) WO2005004200A2 (en)

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US20070176271A1 (en) * 2006-02-01 2007-08-02 Stats Chippac Ltd. Integrated circuit package system having die-attach pad with elevated bondline thickness
US7405102B2 (en) 2006-06-09 2008-07-29 Freescale Semiconductor, Inc. Methods and apparatus for thermal management in a multi-layer embedded chip structure
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US7926173B2 (en) 2007-07-05 2011-04-19 Occam Portfolio Llc Method of making a circuit assembly
US8300425B2 (en) * 2007-07-31 2012-10-30 Occam Portfolio Llc Electronic assemblies without solder having overlapping components
US20090035454A1 (en) * 2007-07-31 2009-02-05 Occam Portfolio Llc Assembly of Encapsulated Electronic Components to a Printed Circuit Board
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US8110905B2 (en) * 2007-12-17 2012-02-07 Stats Chippac Ltd. Integrated circuit packaging system with leadframe interposer and method of manufacture thereof
WO2009129032A2 (en) * 2008-03-24 2009-10-22 Occam Portfolio Llc Electronic assemblies without solder and method for their design, prototyping, and manufacture
KR101257454B1 (en) * 2008-04-07 2013-04-23 삼성테크윈 주식회사 Semiconductor Package and method of manufacturing the same
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US9824958B2 (en) * 2013-03-05 2017-11-21 Infineon Technologies Austria Ag Chip carrier structure, chip package and method of manufacturing the same
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IT201700055942A1 (en) 2017-05-23 2018-11-23 St Microelectronics Srl PROCEDURE FOR MANUFACTURING SEMICONDUCTOR, EQUIPMENT AND CORRESPONDENT CIRCUIT DEVICES
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Also Published As

Publication number Publication date
US7795710B2 (en) 2010-09-14
CN1836319A (en) 2006-09-20
EP1652227A2 (en) 2006-05-03
TW200504984A (en) 2005-02-01
JP2007521656A (en) 2007-08-02
US20060151860A1 (en) 2006-07-13
US7820480B2 (en) 2010-10-26
WO2005004200A2 (en) 2005-01-13
KR20060079754A (en) 2006-07-06
US20080076206A1 (en) 2008-03-27
TWI334213B (en) 2010-12-01
CN100463125C (en) 2009-02-18

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