WO2005010638A3 - Method and system for optimizing reliability and performance of programming data in non-volatile memory devices - Google Patents

Method and system for optimizing reliability and performance of programming data in non-volatile memory devices Download PDF

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Publication number
WO2005010638A3
WO2005010638A3 PCT/IL2004/000679 IL2004000679W WO2005010638A3 WO 2005010638 A3 WO2005010638 A3 WO 2005010638A3 IL 2004000679 W IL2004000679 W IL 2004000679W WO 2005010638 A3 WO2005010638 A3 WO 2005010638A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory devices
cell
performance
volatile memory
programming data
Prior art date
Application number
PCT/IL2004/000679
Other languages
French (fr)
Other versions
WO2005010638A2 (en
Inventor
Amir Ronen
Original Assignee
Milsys Ltd
Amir Ronen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Milsys Ltd, Amir Ronen filed Critical Milsys Ltd
Priority to EP04745019A priority Critical patent/EP1654736B1/en
Priority to AT04745019T priority patent/ATE443330T1/en
Priority to DE602004023209T priority patent/DE602004023209D1/en
Publication of WO2005010638A2 publication Critical patent/WO2005010638A2/en
Publication of WO2005010638A3 publication Critical patent/WO2005010638A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Abstract

Methods of managing memory devices, and devices so managed. A value of a parameter (1011), that is used to program one or more memory cells (1001), is adapted to a monitored condition of the cell(s). Either the number of bits per cell is held fixed or the monitored condition is an intrinsic condition of the cell(s). The initial value of the parameter (1013) is optimized for those specific cells, relative to a pre-selected criterion, by programming the cell(s) in accordance with candidate values of the parameter.
PCT/IL2004/000679 2003-07-30 2004-07-25 Method and system for optimizing reliability and performance of programming data in non-volatile memory devices WO2005010638A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04745019A EP1654736B1 (en) 2003-07-30 2004-07-25 Method and system for optimizing reliability and performance of programming data in non-volatile memory devices
AT04745019T ATE443330T1 (en) 2003-07-30 2004-07-25 METHOD AND SYSTEM FOR OPTIMIZING RELIABILITY AND PERFORMANCE OF PROGRAMMING DATA IN NON-VOLATILE MEMORY COMPONENTS
DE602004023209T DE602004023209D1 (en) 2003-07-30 2004-07-25 METHOD AND SYSTEM FOR OPTIMIZING THE RELIABILITY AND EFFICIENCY OF PROGRAMMING DATA IN NON-VOLATILE MEMORY BLOCKS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US49220603P 2003-07-30 2003-07-30
US60/492,206 2003-07-30

Publications (2)

Publication Number Publication Date
WO2005010638A2 WO2005010638A2 (en) 2005-02-03
WO2005010638A3 true WO2005010638A3 (en) 2005-04-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2004/000679 WO2005010638A2 (en) 2003-07-30 2004-07-25 Method and system for optimizing reliability and performance of programming data in non-volatile memory devices

Country Status (6)

Country Link
US (2) US7437498B2 (en)
EP (2) EP1654736B1 (en)
KR (1) KR100963855B1 (en)
AT (1) ATE443330T1 (en)
DE (1) DE602004023209D1 (en)
WO (1) WO2005010638A2 (en)

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Also Published As

Publication number Publication date
KR20060054374A (en) 2006-05-22
EP1654736A4 (en) 2007-04-18
WO2005010638A2 (en) 2005-02-03
EP1654736B1 (en) 2009-09-16
US20090073769A1 (en) 2009-03-19
DE602004023209D1 (en) 2009-10-29
EP1654736A2 (en) 2006-05-10
US20050024978A1 (en) 2005-02-03
KR100963855B1 (en) 2010-06-16
US7437498B2 (en) 2008-10-14
ATE443330T1 (en) 2009-10-15
EP2113844A1 (en) 2009-11-04

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