WO2005020440A1 - Dc-free code design with increased distance between code words - Google Patents

Abstract

A method and apparatus are provided for encoding digital information. A sequence of successive data words are encoded into a sequence of successive code words according to a code, such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.

Description

DC-FREE CODE DESIGN WITH INCREASED DISTANCE BETWEEN CODE

WORDS

FIELD OF THE INVENTION The present invention relates to communicating digital data through a communication channel. In particular, the present invention relates to encoding and decoding techniques for DC-free codes.

BACKGROUND OF THE INVENTION In the field of digital communications, digital information is typically prepared for transmission through a channel by encoding it. The encoded data is then used to modulate a transmission to the channel. A transmission received from the channel is then typically demodulated and decoded to recover the original information.

The encoding of the digital data serves to improve communication performance so that the transmitted signals are less corrupted by noise, fading, or other interference associated with the channel. The term "channel" can include media such as transmission lines, wireless communication and information storage devices such as magnetic disc drives. In the case of information storage devices, the signal is stored in the channel for a period of time before it is accessed or received. Encoding can reduce the probability of noise being introduced into a recovered digital signal when the encoding is adapted to the known characteristics of the data and its interaction with known noise characteristics of a communication channel.

In typical encoding arrangements, data words of m data bits are encoded into larger code words of n code bits, and the ratio m/n is known as the code rate of the encoding arrangement. Decreasing the code rate reduces the complexity of the encoder/ decoder and can also improve error correction capability, however, a decreased code rate also increases energy consumption and slows communication. Further, it is often desirable for encoded channel sequences to have a spectral null at zero frequency. Such sequences are said to be DC-free and particularly found to enhance the performance in perpendicular magnetic recording. Given a sequence of binary digits, if each binary digit "1" is translated into a plus one (+1) and each binary digit "0" is translated mto a minus one (-1), the sequence will be DC-free if a running digital sum of the bipolar sequence is bounded. The rarining digital sum is the sum of all values (+1 and -1) in a bipolar sequence. When the variation of the rum-ring digital sum is kept to a small value, the sequence is known to have a tight bound. A tighter bound can improve the performance of the channel.

There is a need to provide improved-DC free coding techniques that reduce the probability of noise being introduced to the system and have optimal code rates. Various embodiments of the present invention address these problems, and offer other advantages over the prior art. SUMMARY OF THE INVENTION

One embodiment of the present invention is directed to a method of encoding digital information. According to the method, a sequence of successive data words are encoded into a sequence of successive code words according to a code, such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constramed to predetermined, non-adjacent values at boundaries between the code words.

Another embodiment of the present invention is directed to an encoder for encoding digital information. The encoder encodes a sequence of successive data words into a sequence of successive code words according to a code, such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.

Another embodiment of the present invention is directed to a method of encoding digital information, wherein a sequence of successive data words are encoded into a sequence of successive code words such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained at boundaries between the code words. At least some bits in each code word are interleaved with at least some bits in another, adjacent one of the code words in the sequence of successive code words.

Another embodiment of the present mvention is directed to a method of decoding digital information, wherein a sequence of successive code words are decoded into a sequence of successive data words according to a code in which a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.

Other features and benefits that characterize embodiments of the present invention will be apparent upon readmg the following detailed description and review of the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an isometric view of a disc drive in which one embodiment of the present invention is useful.

FIG. 2 is a flow diagram of a method of encoding information according to one embodiment of the present invention. FIG. 3 is a block diagram of an encoder for encoding information according to the method shown in FIG. 2.

FIG. 4 is a block diagram of an encoder input circuit of the encoder shown in FIG. 3.

FIG. 5 is a block diagram of a data fragment encoder circuit in the encoder shown in FIG. 3.

FIG. 6 is a block diagram of a "g" group encoder of the encoder shown in FIG. 3.

FIG. 7 is a block diagram of a "j" group encoder of the encoder shown in FIG. 3. FIG. 8 is a block diagram of an encoder output circuit of the encoder shown in FIG. 3.

FIG. 9 is a block diagram of a decoder according to one embodiment of the present invention. FIG. 10 is a block diagram of a decoder input circuit of the decoder shown in FIG. 9.

FIG. 10A is a waveform diagram illustrating an example operation of an input multiplexer in the decoder input circuit shown in FIG. 10.

FIG. 11 is a block diagram of a "g" group decoder in the decoder shown in FIG. 9.

FIG. 12 is a block diagram of a "gb" subgroup decoder in the "g" group decoder shown in FIG. 11.

FIG. 13 is a block diagram of a "gc" subgroup decoder in the "g" group decoder shown in FIG. 11. FIG. 14 is a block diagram of a "gd" subgroup decoder in the "g" group decoder shown in FIG. 11.

FIG. 15 is a block diagram of a "ge" subgroup decoder in the "g" group decoder shown hi FIG. 11.

FIG. 16 is a block diagram of a "gf" subgroup decoder in the "g" group decoder shown in FIG. 11.

FIG. 17 is a block diagram of a "j" group decoder in the decoder shown in FIG. 9.

FIG. 18 is a block diagram of a "j" group input circuit in the "j" group decoder shown in FIG. 17. FIG. 19 is a block diagram of a decoder output circuit in the decoder shown in FIG. 9.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS Embodiments of the present mvention relate to a DC-free code for use in encoding and decodmg digital data for transmission through communication channels. In one embodiment of the present invention, a method of encoding is provided, which encodes an unconstrained user data sequence into a DC- free code sequence in which the rurrning digital sum of the code sequence is bounded. In addition to the DC-free property, the encoder constrains the code words in the code sequence such that the cumulative running digital sum in the sequence is restricted to predetermined, non-adjacent values at boundaries between the code words. This kind of restriction increases the minimum Euclidean distance between the code words. In addition, bit streams of such codes words are interleaved with one another to further increase the distances between the code words, thereby allowing many error events that can occur in the channel to be detected.

FIG. 1 is a perspective view of a magnetic disc drive 100, which forms a communications channel in which one embodiment of the present invention is useful. Disc drive 100 communicates with a host system 101 and includes a housing with a base 102 and a top cover (not shown). Disc drive 100 further includes a disc pack 106, which is mounted on a spindle motor (not shown), by a disc clamp 108, Disc pack 106 includes a plurality of individual discs, which are mounted for co- rotation about central axis 109. Each disc surface has an associated head, which is mounted to disc drive 100 for corninunication with the disc surface, hi the example shown in FIG. 1, heads 110 are supported by suspensions 112 which are in turn attached to track accessing arms 114 of an actuator 116. The actuator shown in FIG. 1 is of the type known as a rotary moving coil actuator and includes a voice coil motor (VCM), shown generally at 118. Voice coil motor 118 rotates actuator 116 with its attached heads 110 about a pivot shaft 120 to position heads 110 over a desired data track along an arcuate patch 122 between a disc inner diameter 124 and a disc outer diameter 126. Voice coil motor 118 operates under control of internal circuitry 128. The heads 110 and rotating disc pack 106 define a communications channel that can receive digital data and reproduce the digital data at a later time. Write circuitry within internal circuitry 128 receives unconstrained user data, typically from a digital computer, and then encodes the data into successive code words according to a selected code. The encoded data is then used to modulate a write current provided to a write transducer in the head 110. The write transducer causes the modulated code words to be encoded on a magnetic layer in disc pack 106. At a later time, a read transducer in the head 110 recovers the successive modulated code words from the magnetic layer as a serial modulated read signal. Read circuitry within internal circuitry 128 demodulates the read signal mto successive parallel code words. The demodulated code words are then decoded by decoder circuitry within circuitry 128, which recovers the original user data for use by host system 101.

According to one embodiment of the present invention, each 18-bit word of the unconstrained user data is encoded into a 20-bit code word. This results in a code rate of 18/20. Other code rates can also be used in alternative embodiments of the present invention. In order to generate each 20-bit code word, the corresponding 18-bit user data word is broken down into smaller fragments. The fragments are rearranged and mapped into two 10-bit code word segments according to a lookup table and a mapping table. In one embodiment, the code selects the 10-bit code words such that the cumulative running digital sum of the resulting sequence of 20-bit code words is constramed to the values of 0 or 6 at the boundary of each 20-bit code word. The resulting 20-bit code words are then interleaved to various degrees to further increase the distance between the code words. As the modulated code words are read from the channel, the decoder applies the same coding rules as were used by the encoder, but in reverse order to render the original sequence of user data bits. FIG. 2 illustrates a flow diagram of a method 200 of encoding information according to one embodiment of the present invention. According to method 200, an 18-bit data word is received at step 202. At step 204, method 200 accesses a current state value that has been calculated after each preceding code word is generated. In one example, the current state corresponds to the current, cumulative rumτing digital sum of the sequence of code words as calculated at the end of the preceding code word in the sequence. For the first code word, the initial state is reset to zero. Depending on the current state, the 18-bit data word is broken up into three fragments according to a lookup table at step 206, which is discussed in more detail below. Next, at step 208, a 'g' group and a ']' group are selected based on the first fragment determined in step 206. These groups are chosen in order to maintain the running digital sum at the end of the current code word at either 0 or 6. Once the respective groups are obtained, the second fragment is mapped into a 'g' group 10-bit segment at step 210. The mapping is performed accordmg to a mapping table as discussed below. In step 212, the third fragment is mapped into a ']' group 10-bit segment accordmg to a mapping table. The 'g' group and 'j' group segments are then combined, at step 214, to form a 20- bit code word that constrains the running digital sum at the boundaries of the code words in the sequence at 0 or 6. At step 216, at least some of the bits in each 20-bit code word are interleaved with at least some of the bits in one or more adjacent 20-bit code words in the sequence. The code word is output, for example to a disc, at step 218.

The following description is divided into two sections. Section I is a general description of the design of a 18/20-rate DC-free code with RDS = 0 or 6 at the code word boundaries. The description includes a process of how to simplify the coding procedure and choose the code word mappings that are used in steps 210 and 212 in FIG. 2. An example of encoding a data word into a code word is illustrated at the end of this section. Section II provides a description of an implementation of an encoder and decoder. Block diagrams are included to illustrate the data flow in a hardware setting. The function of each block is described by logical equations. The block descriptions are similar to a VHDL format with input and output signals listed, However, the logical equations describing the signals are similar to a C language program. Hence, they should be applied in sequence as they are listed. I. Procedure of Code Construction

For user data words having 18 bits, there are 2¹⁸ possible data patterns to be encoded. Since 2¹⁸ is a large number exceeding a quarter of a million, it is very difficult to design an encoder by direct mapping. To simplify the design of a rate 18/20 DC-free code, the first step is to break the 20-bit code words into two segments of 10 bits each. A 10-bit pattern may have an RDS of -10, -8, -6, -4, -2, 0, 2, 4, 6, 8 or 10. Since the negative and positive RDS patterns are just the inverse of each other, the following description will focus on the positive RDS patterns, which can be selectively inverted as needed to obtain the negative RDS patterns. The 10-bit positive RDS patterns can be grouped together according to their respective running digital sums. Table 1 shows a plurality of "g" groups, labeled "gb" to "gg", wherein the patterns in each group have the same RDS. The patterns in each group are expressed in •hexadecimal form, with the most significant hexadecimal symbol representing only two binary bits.

Table 1

Group gb :

There are 252 10 -bit patterns with RDS= 3

01F 02F 037 03B 03D 03E 04F 057 05B 05D 05E 067 06B 06D 06E 073

075 076 079 07A 07C 08F 097 09B 09D 09E 0A7 0AB 0AD 0AE 0B3 0B5

0B6 0B9 0BA 0BC 0C7 0CB 0CD 0CE 0D3 0D5 0D6 0D9 ODA 0DC 0E3 0E5

0E6 0E9 0EA 0EC 0F1 0F2 0F4 0F8 10F 117 11B 11D HE 127 12B 12D

12E 133 135 136 139 13A 13C 147 14B 14D 14E 153 155 156 159 15A

ISC 163 165 166 169 16A 16C 171 172 174 178 187 18B 18D 18E 193

195 196 199 19A 19C 1A3 1A5 1A6 1A9 1AA 1AC 1B1 1B2 1B4 1B8 1C3

1C5 1C6 1C9 1CA ICC 1D1 1D2 1D4 1D8 1E1 1E2 1E4 1E8 1F0 20F 217

2IB 2ID 21E 227 22B 22D 22E 233 235 236 239 23A 23C 247 24B 24D

24E 253 255 256 259 25A 25C 263 265 266 269 26A 26C 271 272 274

278 287 28B 28D 28E 293 295 296 299 29A 29C 2A3 2A5 2A6 2A9 2AA

2AC 2B1 2B2 2B4 2B8 2C3 2C5 2C6 2C9 2CA 2CC 2D1 2D2 2D4 2D8 2E1

2E2 2E4 2E8 2F0 307 30B 30D 30E 313 315 316 319 31A 31C 323 325

326 329 32A 32C 331 332 334 338 343 345 346 349 34A 34C 351 352

354 358 361 362 364 368 370 383 385 386 389 38A 38C 391 392 394

398 3A1 3A2 3A4 3A8 3B0 3C1 3C2 3C4 3C8 3D0 3E0

Group gc : There are 210 10- -bit patterns with RDS= +2

03F 05F 06F 077 07B 07D 07E 09F OAF 0B7 0BB 0BD 0BE 0CF 0D7 0DB

ODD ODE 0E7 0EB 0ED 0EE 0F3 0F5 0F6 0F9 0FA 0FC 11F 12F 137 13B

13D 13E 14F 157 15B 15D 15E 167 16B 16D 16E 173 175 176 179 17A

17C 18F 197 19B 19D 19E 1A7 1AB IAD 1AE 1B3 1B5 1B6 1B9 1BA 1BC

1C7 1CB 1CD ICE 1D3 1D5 1D6 1D9 IDA IDC 1E3 1E5 1E6 1E9 1EA 1EC !

1F1 1F2 1F4 1F8 21F 22F 237 23B 23D 23E 24F 257 25B 25D 25E 267

26B 26D 26E 273 275 276 279 27A 27C 28F 297 29B 29D 29E 2A7 2AB ; 2AD 2AE 2B3 2B5 2B6 2B9 2BA 2BC 2C7 2CB 2CD 2CE 2D3 2D5 2D6 2D9

2DA 2DC 2E3 2E5 2E6 2E9 2EA 2EC 2F1 2F2 2F4 2F8 30F 317 31B 31D

31E 327 32B 32D 32E 333 335 336 339 33A 33C 347 34B 34D 34E 353

355 356 359 35A 35C 363 365 366 369 36A 36C 371 372 374 378 387

38B 38D 38E 393 395 396 399 39A 39C 3A3 3A5 3A6 3A9 3AA 3AC 3B1

3B2 3B4 3B8 3C3 3C5 3C6 3C9 3CA 3CC 3D1 3D2 3D4 3D8 3E1 3E2 3E4

3E8 3F0

Group gd:

There are 120 10-bit patterns with RDS= +4

07F OBF 0DF 0EF 0F7 0FB 0FD 0FE 13F 15F 16F 177 17B 17D 17E 19F

1AF 1B7 IBB 1BD 1BE 1CF 1D7 1DB 1DD IDE 1E7 1EB 1ED 1EE 1F3 1F5

1F6 1F9 1FA 1FC 23F 25F 26F 277 27B 27D 27E 29F 2AF 2B7 2BB 2BD

2BE 2CF 2D7 2DB 2DD 2DE 2E7 2EB 2ED 2EE 2F3 2F5 2F6 2F9 2 FA FC

31F 32F 337 33B 33D 33E 34F 357 35B 35D 35E 367 36B 36D 36E 373

375 376 379 37A 37C 38F 397 39B 39D 39E 3A7 3AB 3AD 3AE 3B3 3B5

3B6 3B9 3BA 3BC 3C7 3CB 3CD 3CE 3D3 3D5 3D6 3D9 3DA 3DC 3E3 3E5

3E6 3E9 3EA 3EC 3F1 3F2 3F4 3F8

Group ge : There are 45 10-bit patterns with RDS= +6

OFF 17F 1BF IDF 1EF 1F7 1FB 1FD 1FE 27F 2BF 2DF 2EF 2F7 2FB 2FD

2FE 33F 35F 36F 377 37B 37D 37E 39F 3AF 3B7 3BB 3BD 3BE 3CF 3D7

3DB 3DD 3DE 3E7 3EB 3ED 3EE 3F3 3F5 3F6 3F9 3 FA 3FC

Group gf : There are 10 10-bit patterns with RDS= +8

IFF 2FF 37F 3BF 3DF 3 EF 3F7 3FB 3 FD 3FE

Group gg : There is only 1 10-bi t pattern wi th RDS= + 10

3FF

Each of the groups in Table 1 is further divided mto subgroups, where the number of patterns in each subgroup (i.e., the subgroup size) is a power of two. This allows groups of -bit fragments of user data words to be mapped into code words from a subgroup of size 2^m. The sizes of the second and third fragments of the user data words are determmed by the first user data word fragment in step 206 according to look-up Table 4, which is discussed in more detail below.

Group gb is divided mto subgroups gb7, gb6, gb5 gb4 gb3 and gb2 with sizes of 128=2⁷,

_ancι

respectively. Group gc is divided into subgroups gc7, gc6, gc4 and gel with sizes of

128=2⁷, 64=2⁶, 16=2⁴ and 2=2L respectively.

Group gd is divided into subgroups gd6, gd5, gd4 and gd3 with sizes of 64=2⁶, 32=2⁵, 16=2⁴ and 8=2³, respectively.

Group ge is divided mto subgroups ge5, ge3, ge2 and geO with sizes of 32=2⁵ , 8=2³, 4=2² and 1=2°, respectively. Group gf is divided mto subgroups gf3 and gfl with sizes of 8=2^"* and 2=2', respectively.

Group gg has only one subgroup ggO with a size of 1=2°.

Table 2 lists the mapping of each subgroup. The format of the list is "xxx:yyy", which means that data word fragment "xxx" is to be mapped into 10- bit code word "yyy". Both "xxx" and "yyy" are expressed in hexadecimal form. Table two is used to map the second fragment of the user data word mto a corresponding 10-bit code word segment.

Table 2

Subgroup gb7 : (mappi ng of 7 -bit data word into 10 -bit code word

000:21B 001 233 002 235 003 236 004 :22B 005 239 006 23A 007 23C

008:24B 009 253 00A 255 00B 256 00C:28B 00D 259 00E 25A 00F 25C

010:21D 011 263 012 265 013 266 014:22D 015 269 016 26A 017 26C

018:24D 019 293 01A 295 01B 296 01C:28D 01D 299 0 IE 29A 01F 29C

020:21E 021 2A3 022 2A5 023 2A6 024:22E 025 2A9 026 2AA 027 2AC

028:24E 029 2C3 02A 2C5 02B 2C6 02C:28E 02D 2C9 02E 2CA 02F 2CC

030:271 031 2B1 032 2D1 033 2E1 034:272 035 2B2 036 2D2 037 2E2

038:274 039 2B4 03A 2D4 03B 2E4 03C:278 03D 2B8 03E 2D8 03F 2E8

040:11B 041 133 042 135 043 136 044 : 12B 045 139 046 13A 047 13C

048:14B 049 153 04A 155 04B 156 04C:18B 04D 159 04E 15A 04F 15C

050:11D 051 163 052 165 053 166 054 :12D 055 169 056 16A 057 16C

058:14D 059 193 05A 195 05B 196 05C: 18D 05D 199 05E 19A 05F 19C

060:11E 061 1A3 062 1A5 063 1A6 064 :12E 065 1A9 066 1AA 067 1AC ^'

068:14E 069 1C3 06A 1C5 06B 1C6 06C:18E 06D 1C9 06E 1CA 06F ICC

070:171 071 1B1 072 1D1 073 1E1 074:172 075 1B2 076 1D2 077 1E2

078:174 079 1B4 07A 1D4 07B 1E4 07C:178 07D 1B8 07E 1D8 07 F 1E8

Subgroup gb6 : (mappi ng of 6 -bit data word into 10- -bit code word

000:331 001 313 002 315 003 316 004 :332 005 319 006 31A 007 31C

008:334 009 323 00A 325 00B 326 00C:338 00D 329 00E 32A 00F: 32C

010:3C1 011 343 012 345 013 346 014:3C2 015 349 O 16 34A 017 34C

018:3C4 019 383 01A 385 01B 386 01C:3C8 01D 389 01E 38A 01F 38C

020:0CE 021 0EC 022 0EA 023 0E9 024 :0CD 025 0E6 026 0E5 027: 0E3

028:0CB 029 0DC 02A 0DA 02B 0D9 02C:0C7 02D 0D6 02E 0D5 02F: 0D3

030:03E 031 0BC 032 0BA 033 0B9 034:03D 035 0B6 036 0B5 037: 0B3

038:03B 039 07C 03A 07A 03B 079 03C:037 03D 076 03E 075 03F: 073

Subgroup gb5 : (mappi ng Of 5 -bit data word in to 10- -bit code word)

000:351 001 352 002 354 003 358 004 :361 005 362 006 364 007: 368

008:391 009 392 00A 394 00B 398 00C:3A1 00D 3A2 00E 3A4 00F: 3A8

010:OAE 011 0AD 012 0AB 013: 0A7 014:09E 015 09D 016 09B 017: 097

018:06E 019 06D 01A 06B 01B: 067 01C:05E 01D 05D 01E 05B 01F: 057

Subgroup gb4 : (mapping of 4 -bit data word in to 10- bit code word

000:307 001 30B 002 30D 003: 30E 004:370 005 3B0 006 3D0 007: 3E0

008:0F8 009 0F4 00A 0F2 00B: 0F1 00C:08F 0OD 04F 00E 02F 00F: 01F

Subgroup gb3 : (mappi ng of 3 -bit data word into 10- bit code word)

000:117 001 127 002 147 003 : 187 004 :217 005 227 006 247 007 : 287

Subgroup gb2 : (mappi ng of 2 -bit data word into 10- bit code word)

000:10F 001 20F 002 1F0 003 : 2F0 Subgroup gc7: (mappi ng of 7 -bit data word int O 10 -bit code word

000:257 001 :25B 002 :25D 003 25E 004 :267 005 :26B 006 :26D 007 26E

008 :297 009 :29B 00A :29D 00B 29E 00C:2A7 00D :2AB 0 OE :2AD 00F 2AE

010:237 011 :23B 012 :23D 013 23E 014 :2C7 015 :2CB 016 : 2 CD 017 2CE

018:273 019 :2B3 01A 2D3 01B 2E3 01C:27C 01D :2BC 0 IE :2DC 01F 2EC

020:275 021 :2B5 022 :2D5 023 2E5 024 :276 025 :2B6 026 :2D6 027 2E6

028:279 029 :2B9 02A :2D9 02B 2E9 02C:27A 02D :2BA 02E :2DA 02F 2EA

030:21F 031 :22F 032 24F 033 28F 034 :2F1 035 2F2 036 :2F4 037 2F8

038:077 039 :0B7 03A 0D7 03B 0E7 03C:07B 03D :0BB 03E :0DB 03F 0EB

040:157 041 :15B 042 :15D 043 15E 044:167 045 :16B 046 :16D 047 16E

048 :197 049 :19B 04A :19D 04B 19E 04C: 1A7 04D :1AB 04E : IAD 04F 1AE

050:137 051 :13B 052 :13D 053 13E 054 :1C7 055 :1CB 056 :1CD 057 ICE

058:173 059 1B3 05A 1D3 05B 1E3 05C: 17C 05D 1BC 05E : IDC 05 F 1EC

060:175 061 :1B5 062 1D5 063 1E5 064 : 176 065 1B6 066 :1D6 067 1E6

068:179 069 .1B9 06A 1D9 06B 1E9 06C:17A 06D 1BA 06E : IDA 06F 1EA

070:11F 071 :12F 072 14F 073 18F 074:1F1 075 1F2 076 :1F4 077 1F8

078:07D 079 :0BD 07A ODD 07B OED 07C:07E 07D 0BE 07E : ODE 07F 0EE

Subgroup gc6 : (mappi ng Of 6 -bit data word i t o 10 -bit code word

000:31B 001 333 002 335 003 336 004 :32B 005 339 006 :33A 007 33C

008:34B 009 353 00A 355 00B 356 00C:38B 00D 359 00E :35A 00F 35C

010:31D 011 363 012 365 013 366 014 :32D 015 369 016 :36A 017 36C

018:34D 019 393 01A 395 01B 396 01C:38D 01D 399 01E :39A 01F 39C

020:31E 021 3A3 022 3A5 023 3A6 024:32E 025 3A9 026 :3AA 027 3 AC

028:34E 029 3C3 02A 3C5 02B 3C6 02C:38E 02D 3C9 02E 3CA 02F 3CC

030:371 031 3B1 032 3D1 033 3E1 034 :372 035 3B2 036 :3D2 037 3E2

038:374 039 3B4 03A 3D4 03B 3E4 03C:378 03D 3B8 03E :3D8 03F 3E8

Subgroup gc4 : (mappi ng of 4 -bit data word int o 10 -bit code word)

000:317 001 03F 002 05F 003 06F 004:327 005 09F 006 :0AF 007 OCF

008:347 009 0F3 00A 0F5 00B 0F6 00C:387 00D 0F9 00E ^•OFA 00F OFC

Subgroup gel : (mappi ng of 1 -bit data word in t o 10- -bit code word)

000:30F 001 3F0

Subgroup gd6: (mappi ng of 6 -bit data word int o 10 -bit code word )

000:357 001 35B 002 35D 003 35E 004:367 005 36B 006 36D 007 36E

008:397 009 39B 00A 39D 00B 39E 00C:3A7 O0D 3 B 00E 3 AD 00F 3AE

010:337 011 33B 012 33D 013 33E 014 :3C7 015 3CB 016 3 CD 017 CE

018:373 019 3B3 01A 3D3 01B: 3E3 01C.-37C 01D 3BC 0 IE 3 DC 01F. 3 EC

020:375 021 3B5 022 3D5 023 : 3E5 024 :376 025 3B6 026 3D6 027: 3E6

028:379 029 3B9 02A 3D9 02B: 3E9 02C:37A 02D 3BA 02E 3 DA 02F: 3EA

030:31F 031 32F 032 34F 033 38F 034:3F1 035 3F2 036 3F4 037: 3F8

038:07F 039 0BF 03A 0DF 03B: OEF 03C:0F7 03D 0FB 03E 0FD 03F: OFE

Subgroup gd5 : (mappi ng of 5 -bit data word into 10- bit code word)

000:277 001 2B7 002 2D7 003 : 2E7 004 :27B 005 2BB 006 2DB 007: 2EB

008:27D 009 2BD 00A 2DD 00B: 2ED O0C:27E 00D 2BE 00E 2DE 00F: 2EE

010:177 011 1B7 012 1D7 013 : 1E7 014.-17B 015 IBB 016 1DB 017: 1EB

018:17D 019 1BD 01A 1DD 01B: 1ED 01C:17E 01D 1BE 0 IE IDE 01F: 1EE

Subgroup gd4 : (mapping of 4 -bit data word int D 10- bit code word)

000:15F 001 16F 002 19F 003 : 1AF 004:25F 005 26F 006 29F 007 2AF

008:1F5 009 1F6 00A 1F9 00B: 1FA O0C:2F5 00D 2F6 00E 2F9 00F: 2 FA

Subgroup gd3 : (mappi ng of 3 -bit data word int D 10- bit code word)

000:13F 001 1CF 002 23F 003: 2CF 004 :1F3 005 1FC 006 2F3 007: 2FC

Subgroup ge5 : (mappi ng of 5 -bit data word into 10- bit co e word)

000:377 001: 37B 002: 37D 003 : 37E 004:3B7 005: 3BB 006 3BD 007: 3BE

008:3D7 009: 3DB 00A: 3DD 00B: 3DE 00C:3E7 00D: 3EB 00E 3 ED 00F: 3EE

010:17F 011 1BF 012: IDF 013: 1EF 014 :27F 015 2BF 016 2DF 017: 2EF

018:1F7 019: 1FB 01A: 1FD 01B: 1FE 01C:2F7 01D: 2FB 0 IE 2FD 01F: 2FE Subgroup ge3 : (mappi ng of 3 -bit data word into 10 -bit code word)

000:35F 001 36F 002 39F 003 3AF 004:3F5 005 3F6 006 3F9 00 : FA

Subgroup ge2 : (mappi ng of 2 -bit data word into 10 -bit code word)

000:33F 001 3CF 002 3F3 003 3FC

Subgroup geO: (mapping of 0 -bit data word into 10 -bit code word)

000: OFF

Subgroup gf3 : (mappi ng of 3 -bit data word into 10 -bit code word)

000:37F 001 3BF 002 3DF 003 3EF 004:3F7 005 3FB 006 3FD 007: 3FE

Subgroup gfl: (map i ng of 1 -bit data word into 10 -bit code word)

000:1FF 001 2FF

Subgroup ggO : (mappi ng of 0 -bit data word into 10 -bit co e word)

000:3FF

The third data fragment is then mapped mto a "j" group code word segment to maintain the rumiing digital sum at the boundaries of the 20-bit code words at 0 or 6. This mapping takes into account the current rumiing digital sum of the 20bit code word sequence and the running digital stun of the current 'g' group 10-bit code word segment.

Since the goal is to limit the total or cumulative RDS to 0 or 6 at the end of every 20-bit code word, the encoder keeps track of the total digital sum value of the sequence at the end of each 20-bit code word. In order to ensure that the RDS satisfies the desired constraints, the encoder operates in a plurality of states, wherein the current state corresponds to the cumulative RDS at the end of the previous code word. Depending on the current state, the encoder encodes the next user data word accordingly so that the cumulative RDS stays at 0 or 6.

The coding strategy can be described in two parts, Part 1 for the mapping of data word fragments into code word segments and Part 2 for determmmg the 20-bit code word output and the next state.

1. Part 1

The following possible comb iations of two 10-bit segments exist such that the cumulative RDS at the end of a 20-bit code word stays at 0 or 6. i) If RDS of the first 10-bit segment is 0, the RDS of the second 10-bit must be either 0 or 6 in order to make the RDS at the end of the 20-bit code word to be 0, or 6. ii) If RDS of the first segment is +2, RDS of the second segment must be -2 or +4. iii) If RDS of the first segment is +4, RDS of the second segment must be -4 or +2. iv) If RDS of the first segment is +6, RDS of the second segment must be -6 or O. v) If RDS of the first segment is +8, RDS of the second segment must be -8 or -2. vi) If RDS of the first segment is -2, RDS of the second segment must be +2 or +8. vii) If RDS of the first segment is -4, RDS of the second segment must be +4 or +10. viii) If RDS of the first segment is -6, RDS of the second segment must bo +6. ix) If RDS of the first segment is -8, RDS of the second segment must be +8.

According to the observations in (i) to (ix), the following "j" groups can be defined for mapping the second segment such that the cumulative RDS of the 20- bit code word stays at of 0 or 6.

Table 3

Let Group "jb" be the second segment for case (i) and constitute of he following subgroups : Subgroup jb8 includes 256 patterns and they are from gb7, gb6 , gb5 , gb4, gb3 , and gb2, which h ave RDS=0, and ge5, ge3, ge2 and geO , which have RDS=6. S ince 2⁸ = 256, these code word segments are exactly enough for the encod ing of 8-bit data words. Mappings of 8 -bit data word to these 10-bit code words are

Data 00 to 7F gb 7(128 patterns, RDS= 0)

Data 80 to BF g 6(64 patterns, RDS= 0)

Data CO to DF gb 5(32 patterns, RDS= 0)

Data E0 to EF gb 4(16 patterns, RDS= 0)

Data F0 to F7 gb 3(8 patterns, RDS= 0)

Data F8 to FF ge 3 (8 patterns, RDS=+6)

Subgroup jb5 includes 32 patterns and they are the same as ge5. Mappi ngs of 5-bit data word to these 10-bit code words are: Data 00 to 3F : ge 5(32 patterns, RDS=+6) Subgroup jb3 includes 32 patterns and they are from gb2 and ge2 Mappings of 3-bit dat a word to these 10-bit code words are: Data 00 to 03 : gb 2(4 patterns, RDS= 0) Data 04 to 07 : ge2(4 pattern s , RDS=+6 ) Subgroup jbO includes 1 pattern a nd the mappi ng of 0 - bι t da ta word t o the 10-bι t code word is: Data 00 ge0(l pattern , RDS=+6 ) All "3 b" patterns have RDS of 0 o r +6 satisfying the requirement of c; ( i ) above

* * * *

Group "jc is the sec ond segment for case (ii ) and consti tute of the following subgroups . Subgroup ]c8 includes 256 patterns and they are from -gc7 , -gc6 and g d6 Mappings of 8-bit dat a word to these 10-bit code words are Data 00 to 7F : -gc 7(128 patterns, RDS= -2) Data 80 to BF -gc 6(64 patterns, RDS= -2) Data CO to FF • gd 6(64 patterns, RDS= +4) Subgroup 3c6 includes 64 patterns and they are from gd5 , -gc4 and gd4 Mappings of 6-bit dat a word to these 10-bit code words are Data 00 to IF . gd 5(32 patterns, RDS= +4) Data 20 to 2F : -gc 4(16 patterns, RDS= -2) Data 30 to 3F : gd 4(16 patterns, RDS= +4) Subgroup 3c3 includes 8 patterns and they are from gd3. Mappings of 3 bit data word to thes e 10-bit code words are: Data 00 to 07 : gd3(8 patterns, RDS= +4) Subgroup 3d includes 2 patterns and they are from -gel Mappings of b t data word to thes e 10-bit code words are Data 00 to 01 . -gc 1(2 patterns, RDS= -2) All ":c" patterns hav e RDS of -2 or +4 satisfying the requirement of case (ii) above Note that "-gcx" represents the group wi th patterns equivalen t to the inv erse of the patterns in group "gcx"

Group " d " is the second segment for case (ill) and constitute of the following subgroups : Subgroup d8 includes 256 pattern s and they are equivalent to the inverse o f c8. Mappings of 8 -bit data word to these 10-bit code word i are :

Data 00 to FF : -]c 8 (256 patter ns, RDS= +2, -4) Subgroup 3d6 includes 64 patterns and they are equivalent to the mve: of 306. Mappmgs of 6 -bit data wo rd to these 10-bit code words are Data 00 to 3F ^• -3c 6(64 patter ns, RDS= +2, -4) Subgroup d3 includes 8 patterns and they are equivalent to the mveπ of ]C3. Mappmgs of 3 -bit data wo rd to these 10-bit code words are Data 00 to 07 : -]c 3 (8 pattern s, RDS= -4) Subgroup dl includes 2 patterns and they are equivalent to the ver i of d Mappmgs of 1 -bit data wo rd to these 10-bit code words are Data 00 to 01 : - C 1(2 pattern s, RDS= +2) All ":d" patterns hav e RDS of -4 or +2 satisfying the requirement of case (m ) above .

* * *

Group "3 e " is the second segment for case (iv) and consti ute of the following subgroups : Subgroup e8 includes 256 pattern s and they are equivalent to the inverse o f 3b8. Mappi ngs of 8-bit data word to these 10-bit code word' are:

Data 00 to FF : -3 b8 (256 patte rns, RDS= -6,0) Subgroup e5 includes 32 patterns and they are equivalent to the mve: of 3b5. Mappmgs of 5 -bit data wo rd to these 10-bit code words are Data 00 to IF : -3 b5 (32 patte rns, RDS= -6 ) Subgroup 3e3 includes 8 patterns and they are equivalent to the mver: of b3 Mappings of 3 -bit data word to these 10-bit code words are

Data 00 to 07 . -3b3(8 patterns, RDS= -6,0)

Subgroup 3e0 includes 1 pattern and it is equivalent to the inverse cf

3b0. Mappings of 0-bιt data word to the 10-bit code word is

Data 00 : -3b0(l pattern, RDS= -6)

All "3e" patterns have RDS of -6, or 0 satisfying the requirement of case (iv) above.

* * * * *

Group " f" is the second segment for case (v) and constitute ot the following subgroups:

Subgroup 3f7 includes 128 patterns and they are equivalent to the inverse of gc7. Mappings of 7-bit data word to these 10-bit code words are :

Data 00 to 7F : -gc7(128 patterns, RDS= -2)

Subgroup 3f6 includes 64 patterns and they are equivalent to the inverse of gc6. Mappings of 6 -bit data word to these 10-bit code words are

Data 00 to 3F : -gc6(64 patterns, RDS= -2)

Subgroup 3f4 includes 16 patterns and they are equivalent to the inverse of gc4. Mappings of 4 -bit data word to these 10-bit code words are

Data 00 to OF : -gc4(16 patterns, RDS= -2)

Subgroup 3f3 includes 8 patterns and they are equivalent to the inverse of gf3. Mappings of 3 -bit data word to these 10-bit code words are

Data 00 to 07 : -gf3(8 patterns, RDS= -8)

Subgroup 3 f2 includes 4 pattern and they are from -gel and -gfl

Mappings of 2-bit data word to these 10-bit code words are

Data 00 to 01 : -gel (2 patterns, RDS= -2)

Data 02 to 03 : -gfl (2 patterns, RDS= -8)

All "3f" patterns have RDS of -8, or -2 satisfying the requirement of case (v) above

* * * * *

Group "33" is the second segment for case (vi ) and constitute of the following subgroups:

Subgroup 337 includes 128 patterns and they are equivalent to the inverse of 3f7. Mappings of 7-bit data word to these 10-bit code words are :

Data 00 to 7F : -3 f7 (128 patterns, RDS= +2)

Subgroup 336 includes 64 patterns and they are equivalent to the inverse of 3f6. Mappings of 6 -bit data word to these 10-bit code words are

Data 00 to 3F : -3 f6 (64 patterns, RDS= +2)

Subgroup 334 includes 16 patterns and they are equivalent to the inverse of 3f4. Mappings of 4 -b t data word to these 10-bit code words are

Data 00 to OF : -3 f4 (16 patterns, RDS= +2)

Subgroup 333 includes 8 patterns and they are equivalent to the inverse of 3 f3. Mappings of 3 -bit data word to these 10-bit code words are

Data 00 to 07 : -jf3(8 patterns, RDS= +8)

Subgroup 332 includes 4 patterns and they are equivalent to the inverse of jf2. Mappings of 2 -bit data word to these 10-bit code words are.

Data 00 to 03 : -3 f2 (4 patterns, RDS= +2, +8)

All "33" patterns have RDS of +8, or +2 satisfying the requirement of case (vi) above.

* * * * *

Group "3k" is the second segment for case (vii) and constitute of the following subgroups.

Subgroup k6 includes 64 patterns and they are equivalent to gdβ

Mappings of 6-bit data word to these 10-bit code words are

Data 00 to 3F : gd6(64 patterns, RDS= +4)

Subgroup 3k5 includes 32 patterns and they are equivalent to gd5 Mappings of 5-bit data word to these 10-bit code words are

Data 00 to IF : gd5(32 patterns, RDS= +4)

Subgroup k4 includes 16 patterns and they are equivalent to gd4

Mappings of 4-bit data word to these 10-bit code words are

Data 00 to OF : gd4(16 patterns, RDS= +4)

Subgroup k3 includes 8 patterns and they are equivalent to gd3

Mappings of 3-bit data word to these 10-bit code words are

Data 00 to 07 : gd3(8 patterns, RDS= +4)

Subgroup 3 0 includes 1 pattern and it is equivalent to ggO Mappings of

0-bιt data word to the 10-bit code word is

Data 00 • gg0(l pattern, RDS= +10)

All "3k" patterns have RDS of +4, or +10 satisfying the requirement of case (v i ) above.

* * * * *

Group "3I" is the second segment for case (vin) and constitute of the following subgroups •

Subgroup 315 includes 32 patterns and they are equivalent to ge5 Mappings of 5-bit data word to these 10-bit code words are Data 00 to IF : ge5(32 patterns, RDS= +6)

Subgroup 313 includes 8 patterns and they are equivalent to ge3 Mappings of 3-bit data word to these 10-bit code words are Data 00 to 07 • ge3(8 patterns, RDS= +6)

Subgroup 312 includes 4 patterns and they are equivalent to ge2 Mappings of 2-bit data word to these 10-bit code words are Data 00 to 03 : ge2(4 patterns, RDS= +6)

Subgroup 310 includes 1 pattern and it is equivalent to geO Mappings of 0-b t data word to the 10-bit code word is. Data 00 • ge0(l pattern, RDS= +6)

All "3I" patterns have RDS of +6 satisfying the requirement of case (vm) above.

* * * * *

Group "3m" is the second segment for case (ix) and consti ute of the following subgroups:

Subgroup 3m3 includes 8 patterns and they are equivalent to gf3

Mappings of 3 -bit data word to these 10-bit code words are

Data 00 to 07 : gf3(8 patterns, RDS= +8)

Subgroup 3ml includes 2 patterns and they are equivalent to gfl

Mappings of 2-bit data word to these 10-bit code words are

Data 00 to 01 : gfl (2 patterns, RDS= +8)

All "3m" patterns have RDS of +8 satisfying the requirement of case ( ix) above .

2. Part 2 Determimng 20-bit Code Word Output and Next State From Part I, all the 20-bit code words have RDS of 0 or 6. Dependmg on the current state of the encoder (cumulative RDS), the code word may have to be inverted so that the cumulative RDS stays at 0 or 6. The 20-bit code word output and the next state of the encoder can be determmed according to the following rules: i) If current state is 0 and RDS of code word is 0, next state stays at 0 ii) If current state is 0 and RDS of code word is 6, next state will be 6. iii) If current state is 6 and RDS of code word is 0, next state stays at 6. ix) If current state is 6 and RDS of code word is 6, invert code word and let next state be 0.

For cases (i) to (iii), next state is just equal to current state plus the RDS of the current 20-bit code word. For case (iv), the code word must be inverted so that its RDS becomes -6. The next state is therefore eqttal to current state plus RDS of the modified code word, or Next State= -6 + 6 = 0. Table 4 indicates how the 18-bit user data words are divided into three fragments and mapped into two 10-bit code word segments, with one segment selected from the "g" group and one segment selected from the "j" group. Concatenating the two segments accordingly forms the 20-bit code word. The columns in Table 4 that are labeled "17:0" represent the 18 bit positions in the user data word that is to be mapped. The first fragment is a bit pattern formed by the most significant bits of the data word. The first fragment can have various numbers of bits. The second and third fragments are mapped mto the 'g' and 'j' segments, respectively. Those group names that are underlined in Table 4 represent patterns that are to be inverted. In the lookup table, "Pn" stands for the particular pattern number of the mapping performed. The values "G type" and "J type" correspond to which "g" and "j" subgroup is in the particular pattern.

Table 4

3. Example

As an example, assume the 18-bit user data word is 0x2A3EC = 101010 0011 1110 1100, where "Ox" indicates a hexadecimal value. Assuming the leading bit is dl7, then the bit values from most significant to least significant are: dl7=l, dl6=0, dl5=l, dl4=0, dl3=l, dl2=0, dll=0, dl0=0, d9=l, d8=l, d7=l, d6=l, d5=l, d4=0, d3=l, d2=l, dl=0, and d0=0.

According to Table 4, when the first fragment d(17:13) = 10101 (pattern number Pn = 12) the second fragment d(12:7) is mapped according to subgroup "gc6" to obtain the first 10-bit code segment and the third fragment d(6:0) is mapped according to subgroup "ψ" to obtain the second 10-bit code segment of the 20-bit code word. The bits of the second fragment d(12:7) are 000111=0x07 and, according to mapping for subgroup "gc6", shown in Table 2, the 10-bit segment should be mapped to 0x33C =1100111100. The underline "gc6" means the segment needs to be inverted. The first 10-bit code segment is therefore equal to 0x0C3 = 0011000011.

The bits of the third fragment d(6:0) = 1101100 = 0x6C. According to the mapping for subgroup "jj7", shown in Table 3, the patterns from "gc7" should be used. According to mapping for subgroup "gc7" in Table 2, 0x6C maps into

0xl7A = 0101111010. The first 10-bit code segment is therefore equal to 0xl7A = 0101111010.

Now, combining the first and second 10-bit code segments to obtain the 20- bit code word results in, 0011000011 0101111010 = 0x30D7A. Notice that the running digital sum of this code word is 0, the next state is therefore unchanged.

In order to avoid the unrestrained sequence of 101010..., code words that can cause this error can be elirrύnated. Therefore, code words OxAAAAA and 0x55555 are replaced by 0xC03F3 and 0xC03FC, respectively. These two substitutions are not used for any other mappings and have the same RDS as the replaced patterns.

4. Interleaving

To detect more error event types, the code words can be interleaved to higher degrees. Usually, the higher the degree, the more types of event can be detected. However, higher degrees increase the complexity of the encoder/ decoder and can have other undesirable effects such as long run of a single polarity without transition. Therefore, an interleave of degree two to four can be applied, for example. There are many different ways to interleave the code words but a bit-wise interleave is the simplest choice and can be implemented easily. Any method of interleaving can be used with embodiments of the present invention that use interleaving.

In a bit-wise interleave of degree two, two adjacent 20-bit code words in a code word sequence can be interleaved into a single code word of 40 bits, as shown below: Code word 1 = A19A18A17 A16A15AMA13A1₂AH AιoA9A8A₇A₆ A₅A₄A₃ A₂Aι A₀ Code Word 2 ⁼ B19 B-js B17 B-iβ B15 B-| B-13 B12 Bn B10 B9 Bs B₇ Be B₅ B B3 B2 B-i B₀

The interleaved 40-bit word is therefore: A-19 B19A18 Biβ -17 B17A16 B16A15 B15A14 B A13 B-13 A12 B12 11 B-11 A10 B10 A9 B9A8 B₈ A₇ B₇ A₆ B₆ A₅ B₅ A4 B₄ A₃ B₃ A₂ B₂ A B . A₀ B₀. In other words, the code rate will be 36/40 when the code words are interleaved to degree two. Likewise, the code rate will be 54/60 and 72/80 when interleaved to degree three and four respectively. Notice that the code rate stays unchanged at 0.9 while the code word length increases accordingly when the degree of interleave is increased. II. Descriptions of Encoder and Decoder

The following section provides example of an encoder and a decoder that can be used to implement the code discussed above. The details of the circuits and operations described below are examples only and can be performed in hardware, software, firmware and/ or combinations thereof. Table 5 provides definitions for the symbols and logic operations used below to describe the functions of the encoder and decoder.

Table 7

Symbol definition:

" I " Bitwise OR "&" Bitwise AND

\\^A// Bitwise XOR

» 1 x" Inverse of bit x

" ! C (n 0)" Inverse of all bits of word C

1. Encoder

FIG. 3 is a block diagram of an encoder 250 for encoding an 18-bit user data word into a 20-bit code word for transmission through a communication channel 252, according to the method shown in FIG. 2. Encoder 250 has an initialization input INIT, an 18-bit user data input Ii7_:o, a word clock input WORD CLOCK, and a 20-bit code word output Wι_9:o. Encoder 250 further includes encoder input circuit 254, data fragment encoder 256, "g" group encoder 258, "j" group encoder 260, and encoder output circuit 262. Encoder input circuit 254 receives each successive 18-bit user data word on input Ii7:0 and latches each data word on data output Di7:0 on the rising edge of Word Clock. Encoder input circuit 254 also latches a next state value NEXT STATE received from encoder output circuit 262 as a current state on state output STATE with each received user data word. With the first user data word in a sequence, or on power up, initialization input INIT resets the current state value to zero. As mentioned in the above-example, the current state value can have one of two values, representing a zero or six cumulative running digital sum on code word output Wi9:o, at the boundary of each code word.

Data fragment circuit 256 performs the function of the look-up table shown in Table 4 above. For each latched 18-bit user data word received from encoder input circuit 254, data fragment circuit 256 looks at the pattern formed by the most significant bits of the word (such as the "first fragment" discussed above) to determine which "g-" subgroup and "j-" subgroup should be used for encoding the data word and generates a corresponding g-group select signal gsi9:0 and j- group select signal js36:0. Circuit 256 also routes the bits of the user data word to be encoded into a g-group code word to g-group data output gd_6:o and routes the bits to be encoded into a j-group code word to j-group data output jd7:o. Circuit 256 also generates a g-group invert signal g_inv, which is used to selectively invert the g-group code word according to Table 4.

G-group encoder 258 encodes the g-group data bits into a corresponding 10-bit code word segment gW9:o as a function of the select signal gsι_9:o , the invert signal g_inv, and the current state STATE. Similarly, j-group encoder 260 encodes the j-group data bits jd7:o into a 10-bit code word segment jw9_:0 based on select signal js36:0 and the current state STATE. Encoder output circuit 262 receives the two 10-bit code word segments and forms the 20-bit code word on code word output Wi9:0. Encoder output circuit 262 also generates the next state value based on the current state STATE and the running digital sum of the current 20-bit code word.

FIGS. 4-8 illustrates circuits 254, 256, 258, 260 and 262 in greater detail. FIG. 4 shows the details of encoder input circuit 254. Encoder input circuit 254 includes 18-bit data word latch 300 and state latch 302. Data word latch 300 latches each data word received on input Ii7:oto data output Di&o on the rising edge of WORD CLOCK. Similarly, state latch 302 latches the next state received on the next state input as the current state on state output STATE on the rising edge of WORD CLOCK. Initialization input INIT is coupled to the reset input of state latch 302 for resetting state output STATE upon initialization. Before the first user data word is clocked mto latch 300, the INIT signal initializes STATE to zero. In one embodiment, STATE is a one-bit value representing the current state ("0" for state zero and "1" for state six).

FIG. 5 is a block diagram iuustrating data fragment circuit 256 in greater detail. Circuit 256 includes a pattern select circuit 310 and a fragment multiplexer 312. Pattern select circuit 310 receives the latched 18-bit data word Di7:0 and, based on the first fragment of the data word (the most significant bits shown in Table 4), identifies which of the 138 g-group and j-group pattern combinations in Table 4 shall be used. Pattern select circuit 310 generates a logic high value on a one of the 138 select outputs Si38:i, which corresponds to that pattern combination. Using the example discussed above, if D[17:13] equals "10101", then the pattern combination of gc6 and jj7 (Pn=12) is selected. Therefore S[12] would be active at the output of pattern select circuit 310 and the remaining bits would be inactive.

Based on the pattern formed by Si38:i, fragment multiplexer 312 routes the appropriate user data bits to g-group data output gd&o and j-group data output jd7:0 and generates the appropriate g-group select pattern gsi9:0 and j-group select pattern JS36:0. One of the g-group select bits gsi9:₀ will be active, and all other bits will be inactive. Sirrularly, one of the j-group select bits js36:0 will be active and all other bits will be inactive. Multiplexer 312 also generates the appropriate value on g-group invert output g_inv.

In one embodiment, data fragment encoder circuit 256 operates according to the logic definitions shown in Table 8. The logic operators used in Table 8 are defined in Table 7.

Table 8 enc rds

Input: dl7,dl6 ,dl5 ,dl4,dl3 dl2 dll,dlO , d9 , d8 , d7 , d6 , d5 , d4 ,d3,d2 ,dl,d0

(18 -bit Dataword)

Output : gd ( 6 : 0 ) , jd (7 :0) gs (19: 0) , js(36:0)

Pattern Select of enc rds

TA0= !dl7&!dl6 TA1 = !dl7& dl6 TA2 = dl7&!dl6 TA3 = dl7& dl6

TB07 = !dl5 TB8f= dl5

TB03 = TB07&!dl4 TB47= TB07& dl4 TB8b= TB8f&!dl4 TBcf= TB8f& dl4

TB01= TB03&!dl3 TB23 = TB03& dl3 TB45 = TB47&!dl3 TB67= TB 7& dl3

TB89 = TB8b&!dl3 TBab= TB8b& dl3 TBcd= TBcf&!dl3 TBef= TBcfS: dl3

TB0 = TB01&!dl2 TB1 = TB01& dl2 TB2 = TB23&!dl2 TB3 = TB23& dl2

TB4 = TB45&!dl2 TB5 = TB 5& dl2 TB6 = TB67&!dl2 TB7 = TB67& dl2

TB8 = TB89&!dl2 TB9 = TB89& dl2 TBa = TBab&!dl2 TBb = TBab& dl2

TBc = TBcd&!dl2 TBd = TBcd& dl2 TBe = TBef&!dl2 TBf = TBef& dl2

TC07 = !dll TC8f= dll

TC03 = TC07&!dlO TC47 = TC07& dlO TC8b= TC8f&!dlO TCcf= TC8f£i dlO

TC01 = TC03&!d9 TC23 = TC03& d9 TC45= TC47&!d9 TC67= TC 7& d9

TC89 = TC8b&!d9 TCab= TC8b& d9 TCcd= TCcf£i!d9 TCef= TCcf& d9

TCO = TC01&!d8 TCI = TC01& d8 TC2 = TC23&!d8 TC3 = TC23& d8

TC4 = TC45&!d8 TC5 = TC45& d8 TC6 = TC67&!d8 TC7 = TC67& d8

TC8 = TC89&!d8 TC9 = TC89& d8 TCa = TCab&!d8 TCb = TCab& d8

TCc = TCcd&!d8 TCd = TCcd& d8 TCe = TCef&!d8 TCf = TCef& d8

TD07 = !d7 TD8f= d7

TD03 = TD07&!d6 TD47= TD07& d6 TD8b= TD8f&!d6 TDcf= TD8f& d6

if (S5|S9| S18|S24) js8 =l,all other js=0} if (S17|S23|S35|S51) js9 =l,all other js=0} if (S50|S62|S82|S95) jsl0=l,all other js=0} if (S8l|S94|S106|S120) jsll=l,all other js=θ} if (S10|S25|S37|S65) jsl2=l,all other js=0} if (S36|S64|S83 |S109) jsl3=l,all other js=0} if (S63|S96|S108lS129) jsl4=l,all other js=θ} if (S107|S128|S137) jsl5=l,all other js=0} if (S38|S66) jsl6=l,all other js=0} if (S52|S85) jsl7=l,all other js=θ} if (S84|S111) jsl8=l,all other js=0} if (S97|S121) jsl9=l,all other js=0} if (Sllθ|S130) js20=l,all other js=0} if (S6|S12 |S27|S69) js21=l,all other js=0} if (Sll|S19|S4l|S87) js22=l,all other js=0} if (S26|S40|S68|S112) js23=l,all other js=0} if (S39|S54|S86|S122) js24=l,all other js=0} if (S53|S67|S98|S131) js25=l,all other js= 0} if (S20|S29|S44|S58) j s26=l, all other js= 0} if (S28|S43|S57|S72) js27=l,all other j s= 0} if (S42|S56|S7l|S89) js28=l,all other js= 0} if (S55|S70|S88|S100) js29=l,all other js=0} if (S99|S113|S123|S132 ) js30=l,all other js=0} if (S45|S74|S9l|S117) js31=l,all other js=0} if (S73|S10l|S116|S134 ) js32=l,all other js=0} if (S90|S115|S124) js33=l,all other js=0} if (S114|S133|S138) js34=l,all other j s= 0} if (S102 |S126) js35=l,all other js=θj if (S125) js36=l,all other js=0}

FIG.6 is a block diagram inustrating g-group encoder 258 in greater detail. The g-group data bits gd_6:o are coupled to the inputs of g-subgroup encoders 320. There is one g-subgroup encoder group 320 for each of the g-subgroups defined in Table 2 above. Each g-subgroup encoder 320 receives the corresponding bits from gd_6:o and encodes the bits into a respective 10-bit code word segment according to the mapping in Table 2. The respective g-subgroup code word segments are applied to the inputs of a g-subgroup encoder output multiplexer 322. Output multiplexer 322 has a select input, which is coupled to subgroup select pattern gsi9:0. Based on which g-subgroup is selected by pattern gsi9_:0, multiplexer 322 passes the corresponding g-subgroup code word segment to output gW9:₀ as the g-group 10-bit group code word segment. This code word segment is selectively inverted as a function of g_inv. In one embodiment, g-group encoder 258 operates according to the logic operations shown in Table 9.

Table 9

enc gb7

Input : A6,A5,A4,A3 ,A2,A1,A0

Output: CS } , C8 , C7 , C6 , C 5 , C4 , C3 , C2 , C 1 , CO gb7a = (!A5| !A4)&(Al|A0) ; gb7a9= gb7a&!A6; gb7a8= gb7a& A6 ; gb7a7= gb7a& ( A5 | ( A4 & A3 ) ) ; gb7a6= gb7a &( A4 ^A A3 ) ; gb7a5= gb7a & !A3 ; gb7a4= gb7a&(!A5 &( A3 | !A4 ) ); gb7a3= gb7a & A2 ; gb7a2= gb7a&( Al & ( A0 | IA2 ) ) ; gb7al= gb7a &( A2 ^A AO ) ; gb7a0= gb7a&(!Al | ( !A2 & !A0 ) ) ; gb7b = (!A5| !A4)&( 1A1&1A0) ; gb7b9= gb7b &!A6; gb7b8= gb7b & A6; gb7b7= gb7b &( A3 & A2 ) gb7b6= gb7b &( A3 & !A2 ) gb7b5= gb7b &( A2 & !A3 ) gb7b4= gb7b &( !A3 & !A2 ) gb7b3= gb7b; gb7b2= gb7b &( A5 | A4 ) ; gb7bl= gb7b & !A4 ; gb7b0= gb7b & !A5 ; gb7c = A5&A4; gb7c9= gb7c &!A6; gb7c8= gb7c & A6; gb7c7= gb7c &( Al | A0 ) gb7c6= gb7c &( Al j !A0 ) gb7c5= gb7c &( A0 j !A1 ) gb7c4= gb7c &( !A1 j !A0 ) gb7c3= gb7c &( A3 & A2 ) gb7c2= gb7c &( A3 & !A2 ) gb7cl= gb7c &( A2 & !A3 )

enc gb6

Input : A5 , A4 , A3 ,A2 ,Al , AO

Outpu : C 9 , C8 , C7 , C6 , C 5 , C4 , C3 , C2 , C 1 , CO gb6a = ( 1A1&1A0) ; gb6a9= gb6a; gb6a8= gb6a; gb6a7= gb6a & ' 1 ; gb6a6= gb6a & A' 1 ; gb6a5= gb6a & !A' 1 ; gb6a4= gb6a & !A< 1 ; gb6a3= gb6a & ( A3 & A2 ) gb6a2= gb6a & ( A3 & !A2 ) gb6al= gb6a & ( A2 & !A3 ) gb6a0= gb6a &( !A3 & !A2 ) gb6b = (A1|A0) ; gb6b9= gb6b; gb6b8= gb6b; gb6b7= gb6b & ( 4 & A3 ) gb6b6= gb6b &( A4 & !A3 ) gb6b5= gb6b &( A3 & !A4 ) gb6b4= gb6b & ( !A4 & !A3 ) gb6b3= gb6b & A: 2; gb6b2= gb6b&( Al &( AO | !A2) ) ; gb6bl= gb6b & ( A2 ^Λ AO ) ; gb6b0= gb6b&(!Al | ( !A2 & !A0) ) ;

C9 = gb6a9 | gb6b9

C8 = gb6a8 |gb6b8

C7 = gb6a7 j gb6b7

C6 = gb6a6 j gb6b6

C5 = gb6a5 j gb6b5

C4 = gb6a4 j gb6b4

C3 = gb6a3 j gb6b3

C2 = gb6a2 j gb6b2

Cl = gb6al j gb6bl

CO = gbδaO j gb6b0 if(A5) { C9=!C9 ^• C8=!C8; C7= ! C7 ; C6= !C6; C5= !C5;

C4=!C4 ^• C3=!C3; C2=!C2; Cl= !C1; C0= !C0; }

enc gb5

Input : A4 , A3 , A2 , A] L ,A0

Output: C9,C8,C7,C6,( 5,C4,C3,C2,C1,C0

C9= 1 ;

C8= 1 ;

C7= A3

C6= ! A3

C5= A2

C4= ! A2

C3= ( Al & AO ) ,

C2= ( Al & !A0 )

Cl= ( AO & IA1 )

C0= ( !A1 & !A0 ) if(A4) { C9=!C9 C8=!C8; C7= !C7; C6= !C6; C5= !C5;

C4=!C4 C3=!C3; C2= !C2; Cl= "Cl; C0= ICO; } enc gb4

Input : A3,A2,A1,A0

Output : C 9 , C8 , C7 , C6 , C 5 , C4 , C3 , C2 , C 1 , CO

C9= 1 ;

C8= 1 ;

C7= ( A2 &( Al | A0) )

C6= ( A2 &( Al j !A0) )

C5= ( A2 &( A0 j !A1) )

C4= ( A2 &( !A1 j !A0) )

C3= ( !A2 &( Al j A0) )

C2= ( !A2 &( Al j !A0) )

Cl= ( !A2 &( A0 j !A1) )

C0= ( !A2 &( !A1 j !A0) ) if (A3 { C9=!C9; C8=!C8 C7= !C7; C6= !C6; C5= !C5;

C4=!C4; C3=!C3 C2= 1C2; Cl= !C1; C0= !C0; }

enc gb3

Inpu : A2,A1,A0

Outpu : C 9 , C8 , C7 , C6 , C 5 , C4 , C3 , C2 , C 1 , CO

C9= A2;

C8= A2;

C7= ( Al & AO )

C6= ( Al & !A0 )

C5= ( AO & !A1 )

C4= ( !A1 & !A0 )

C3= 0

C2= 1

Cl= 1

C0= 1

enc gb2

Input : A1,A0

Output : C 9 , C8 , C7 , C6 , C 5 , C4 , C3 , C2 , C 1 , CO

C9= AC ) ;

C8=!AC ) ;

C7= A] L ;

C6= A] L ;

C5= A] L ;

C4= A] L;

C3=!A] L ;

C2=!A] L;

C1=!A3 L ;

C0=!A3 .

enc gc7

Input : A6,A5,A4,A3, A2,A1,A0 Output : C 9,C8,C7,C6,C 5,C4,C3,C2,C1,C0 gc7a = (!A5)&( (!A4) I (A4&1A3) ) ; gc7a9= gc7a&!A6; gc7a8= gc7a& A6; gc7a7= gc7a& ( A3 I ( A4 & A2 ) ) ; gc7a6= gc7a&( !A3 &( A2 I !A4) ); gc7a5= gc7a &( A4 ^λ A2 ) ; gc7a4= gc7a & !A2 gc7a3= gc7a &( A 1 I AO ) gc7a2= gc7a &( A1 I !A0 ) gc7al= gc7a &( A 0 j !A1 ) gc7a0= gc7a &( !A 1 I !A0 ) gc7b = (1A5&A4&A3) I (A5&1A4) gc7b9= gc7b&!A6; gc7b8= gc7b& A6; gc7b7= gc7b &( Ai I AO ) gc7b6= gc7b &( Al I !A0 ) gc7b5= gc7b &( Ao I !A1 ) gc7b4= gc7b &( !Ai I !A0 ) gc7b3= gc7b&( A3 &( A5 I A2 ) gc7b2= gc7b&(!A3 A4 & A2 ) ); gc7bl= gc7b &( A !A2 ) ; gc7b0= gc7b & !A2 gc7cd = A5&A4&I 3; gc7cd9 = gc7cd&!A6 gc7cd8 = gc7cd& A6 gc7cd7 = gc7cd& ( A Al AO) gc7cd6 = gc7cd& ( A Al ! AO) gc7cd5 = gc7cd& ( A AO ! Al) gc7cd4 = gc7cd& ( A !A1 ! AO) gc7cd3 = gc7cd&(!A Al AO) gc7cd2 = gc7cd&(!A Al ! AO) gc7cdl = gc7cd&(!A AO & ! Al) gc7cd0 = gc7cd&(!A !A1 & ! AO) gc7e = A5&A4&A3; gc7e9= 0; gc7e8= 0; gc7e7= gc7e &( AO gc7e6= gc7e &( !A0 gc7e5= gc7e &( !A1 gc7e4= gc7e &( !A0 gc7e3= gc7e &( A2 gc7e2= gc7e &( !A2 gc7el= gc7e &( !A6 gc7e0= gc7e &( S j !A2 C9 = gc7a9 |gc7b9 |gc7cd9 |gc7e9; C8 = gc7a8 j gc7b8 |gc7cd8 j gc7 e8 ; C7 = gc7a7 jgc7b7 |gc7cd7 jgc7e7; C6 = gc7a6 j gc7b6 |gc7cd6 |gc7e6; C5 = gc7a5 I gc7b5 |gc7cd5 j gc7 e5 ; C4 = gc7a4 |gc7b4 |gc7cd4 j gc7 e4 ; C3 = gc7a3 I gc7b3 |gc7cd3 I gc7 e3 ; C2 = gc7a2 j gc7b2 |gc7cd2 j gc7 e2 ; Cl = gc7al |gc7bl |gc7cdl |gc7el; CO = gc7a0 |gc7bO |gc7cd0 |gc7e0; enc gc6

Input : A5,A4,A3,A2 ,A1,A0

Output : C 9 , C8 , C7 , C6 , C 5 , C4 , C3 , C2 , C 1 , CO gc6a = (!A5| !A4)& (Al|AO) ; gc6a9= gc6a; gc6a8= gc6a,- gc6a7= gc6a& ( A5 | ( A4 & A3 ) ) ; gc6a6= gc6a &( A4 ^Λ A3 ) ; gc6a5= gc6a & !A3 ; gc6a4= gc6a&(!A5 & ( A3 | !A4 ) ) ; gc6a3= gc6a & A2 ; gc6a2= gc6a&( Al &( AO | !A2 ) ) ; gc6al= gc6a &( A2 ^Λ AO ) ; gc6a0= gc6a&(!Al | ( !A2 & !A0) ) ; gc6b = (!A5| !A4)&( 1A1&1A0) ; gc6b9= gc6b; gc6b8= gc6b; gc6b7= gc6b &( A3 & A2 ) ; gc6b6= gc6b &( A3 & !A2 ) ; gc6b5= gc6b &( A2 & !A3 ) ; gc6b4= gcδb &( !A3 & !A2 ) ; gc6b3= gc6b; gc6b2= gc6b &( A5 | A4 ) ; gc6bl= gc6b & !A4 ; gc6b0= gc6b & !A5 ; gc6c = (A5&A4) ; gc6c9= gc6c; gc6c8= gc6c; gc6c7= gc6c &( Al | AO ) gc6c6= gc6c &{ Al | !A0 ) gc6c5= gc6c &( AO | !A1 ) gc6c4= gcδc &( 1A1 | !A0 ) gc6c3= gc6c &( A3 & A2 ) gc6c2= gc6c &( A3 & !A2 ) gc6cl= gc6c &( A2 & !A3 ) gc6c0= gc6c &( !A3 & !A2 )

C9 = gc 36a9 |gc6b9 |gc6c9;

C8 = gc :6a8 j gc6b8 |gc6c8;

C7 = gc6a7 | gc6b7 |gc6c7;

C6 = gc ^6a6 |gc6b6 |gc6c6;

C5 = g< _6a5 ]gc6b5 |gc6c5;

C4 = gcr6a4 |gc6b4 |gc6c4;

C3 = gc :6a3 |gc6b3 |gc6c3;

C2 = gc ^6a2 |gc6b2 |gc6c2;

Cl = gc _6al jgc6bl |gc6cl;

CO = gc6a0 | gc6b0 |gc6c0;

enc gc4

Inpu : A3,A2,A1,A0

Output : C 9 , C8 , C7 , C6 , C 5 , C4 , C3 , C2 , C 1 , CO

gd6a7= gdδa&( A3 I ( A4 & A2 ) ) ; gd6a6= gd6a&(!A3 &( A2 I !A4) ) ; gd6a5= gd6a & ( A4 ^Λ A2 ) ; gd6a4= gd6a & !A2 gd6a3= gd6a &( A 1 I AO ) gd6a2= gd6a &( A1 j !A0 ) gd6al= gd6a &( A 0 j !A1 ) gd6a0= gd6a &( !A 1 j !A0 ) gd6b = (1A5&A4&A3 I (A5&IA4)

A2 ) ); A2 ) );

gd6b0= gd6b & !A2 gd6cd A5&A4&1A3; gd6cd9 gd6cd; gd6cd8 gd6cd; gd6cd7 gdδcd& ( Al & AO) gd6cd6 gdδcd&( Al & ! AO) gd6cd5 gd6cd&( AO ! Al) gd6cd4 gd6cd&( !A1 ! AO) gd6cd3 gd6cd&(!A Al AO) gd6cd2 gd6cd&( !A Al ! AO) gd6cdl gd6cd&(!A AO ! Al) gdδcdO gd6cd&( !A !A1 ! AO) gd6ef A5&A4&A3; gd6ef9 0; gd6ef8 0; gd6ef7 gd6ef &( A2 gd6ef6 gd6ef &( A2 gd6ef5 gdδef &( A2 gd6ef4 gd6ef &( A2 gd6ef3 gd6ef &( Al gd6ef2 gd6ef &( Al gdδefl gdδef &( AO gd6ef0 gdδef &( !A2

C9 = gd6a9 I gd6b9 |gd6cd9 gd6 ef9

C8 = gd6a8 j gd6b8 |gd6cd8 gd6 ef8

C7 = gd6a7 j gd6b7 |gd6cd7 gd6 ef7

C6 = gd6a6 j gd6b6 |gd6cd6 gdδ ef6

C5 = gd6a5 j gd6b5 |gd6cd5 gdδ ef5

C4 = gd6a4 j gd6b4 I gd6cd4 gdδ ef4

C3 = gd6a3 j gd6b3 I gd6cd3 gd6 ef3

C2 = gd6a2 j gd6b2 I gd6cd2 gdδ ef2

Cl = gd6al j gdδbl |gd6cdl gdδ ef1

CO = gd6a0 I gd6bO I gd6cd0 gd6 ef0

enc gd5 Input : A4 , A3 , A2 , Al , AO

ge5a3= ge5a &( Al A0 ) ge5a2= ge5a &( Al j !A0 ) ge5al= ge5a & ( AO j !A1 ) ge5a0= ge5a & ( !A1 j 1A0 ) ge5bc = A4; ge5bc9 = ge5bc & ιa.2; ge5bc8 = ge5bc & ! j \2 ; ge5bc7 = ge5bc &( A3 ge5bc6 = ge5bc & ( A3 ge5bc5 ge5bc & ( A3 ge5bc4 = ge5bc &( A3 ge5bc3 = ge5bc & ( Al ge5bc2 = ge5bc & ( Al ge5bcl = ge5bc & ( A0 ge5bc0 = ge5bc &( !A3

C9 = ge5a9 |ge5bc9

C8 = ge5a8 |ge5bc8

C7 = ge5a7 j ge5bc7

Cδ = ge5aδ |ge5bcδ

C5 = ge5a5 | ge5bc5

C4 = ge5a4 | ge5bc4

C3 = ge5a3 j ge5bc3

C2 = ge5a2 j ge5bc2

Cl = ge5al jge5bcl

CO = ge5a0 |ge5bc0

enc ge3

Inpu : A2,A1,A0 Output : C 9 , C8 , C7 , Cδ , C 5 , C4 , C3 , C2 , C 1 , CO C9= 1; C8= 1; C7= C6= C5= C4= C3= C2= Cl= C0=

enc ge2

Input : Al,AO Outpu : C 9 , C8 , C7 , Cδ , C 5 , C4 , C3 , C2 , C 1 , CO C9= 1; C8= i C7= C6= C5= C4= C3= C2=

C6= 1

C5= 1

C4= 1

C3= 1

C2= 1

Cl= 1

C0= 1

Note: ggO is only used in JX Encoder but not in GX Encoder

GX Encoder Output Mux

Input: gb7(9:0), gbδ(9:0), gb5 (9:0), gb4(9:0), gb3(9:0), gb2(9:0), gc7(9:0), gcδ(9:0), gc4(9:0), gel (9:0), gdδ (9:0) , gd5(9 0), gd4(9: 0) , gd3(9:0), ge5(9:0), ge3(9: 0), ge2(9:0) , ge0(9:0), gf3(9:0), gfl(9:0), g_sel{19:0)

Output : gw ( 9 : 0 )

If (g_sel0) {gw (9 0) = gb7(9 0)}

If (g_sell) {gw(9 0) = gb6(9 0)}

If (g_sel2) {gw(9 0) = gb5(9 0)}

If (g_sel3) {gw(9 0) = gb4(9 o)}

If (g_sel4) {gw(9 0) = gb3(9 o)}

If (g_sel5 ) {gw (9 0) = gb2(9 0)}

If (g_selδ ) {gw (9 0) = gc7(9 0)}

If (g_sel7 ) {gw (9 0) = gc6 (9 0)}

If (g_sel8) {g (9 0) = gc4 (9 0)}

If (g_sel9 ) {g (9 0) = gel (9 o)}

If (g_sell0) (gw(9 0) = gd6(9 0)}

If (g_selll) {g (9 0) = gd5(9 o)}

If (g_sell2) {gw (9 0) = gd4(9 0)}

If (g_sell3) {gw (9 0) = gd3(9 o)}

If (g_sell4) {gw (9 0) = ge5(9 o)}

If (g_sell5) {gw (9 0) = ge3(9 0)}

If (g__sellδ) {gw (9 0) = ge2(9 o)}

If (g^sell7) {gw (9 0) = ge0(9 0)}

If (g_sell8) {gw(9 0) = gf3(9 o⁾}

If(g sell9) {gw (9 0) = gfl (9 0)}

J-group encoder 260 (shown in FIG. 3) operates in a similar fashion as g- group encoder 258. FIG. 7 is a block diagram illustrating j-group encoder 260 in greater detail. J-group encoder 260 includes a plurality of j-subgroup encoders 330 and a j-group encoder output multiplexer 332. All of the j-subgroup encoders 330 are identical to the g-subgroup encoders 320 shown in FIG. 6. Each subgroup encoder 330 receives the respective bits of jd7:o and encodes those bits into a corresponding j-group 10-bit code word segment for selection by multiplexer 322. Multiplexer 332 selects the appropriate code word segment based on the j-group select pattern JS36 o. The selected code word segment is applied to j-group code word output JW9 o.

Table 10 illustrates the logical operations performed by j-group encoder 260 according to one embodiment of the present invention.

Table 10

JX Encoder Output Mux

Input : gb7(9:0) , gb6(9:0) , gb5(9: 0) , gb4(9:0) , gb3(9:0) gb2(9:0) , gc7(9. 0) , gc6(9:0) , gc4(9-0) , gel (9:0) , gd6(9 :0) , gd5(9 0) , gd4(9:0) , gd3 (9: 0) , ge5(9:0) , ge3(9-0) , ge2 (9:0) , ge0(9 :0) , gf3 (9 0) , gfl(9:0) , ggo(9: 0) , A(7:0) , S (36:0)

Output : 3W(9:0) ub7 = (3S0 | 3S12) & IA7 ubδ = (3S0 j 3S12) & A7 & IA6 ub5 = ( s0 j 3S12) & A7 & A6 & 'A5 ub4 = (3 SO j :sl2) & A7 & A6 & A5 & 'A4 ub3 = ( SO 3S12) & A7 & A6 & A5 & A4 & 'A3 ub2 = ( s2 j 3S14) & 1A2 uc7 = (3S8 & Α7) 1 3 s21 uc6 = (3S8 & A7 & ^IA6 ) | S22 uc4 = (3S9 & A5 & 'A4 ) j S23 ucl = 3sll | (3S25 & "Al) ud6 = (3S4 & A7 & A6) | 3S26 ud5 = (3S5 & Α5) 1 3 s27 ud4 = ( S5 & A5 & A4) | 3S28 ud3 = s6 | 3S29 ue5 = 3Sl j S31 ue3 = (3Sθ & A7 & A6 & A5 & A4 & A3) | 3S32 ue2 = (3S2 & A2) | 3S33 ueO = S3 | 3S34 uf3 = 3S24 | S35 ufl = (3S25 & Al) | 3 s36 ugO = 3S30 vc7 = (3S4 & iA7) | slδ cδ = (3S4 & A7 & Α6) 1 3S17 vc4 = ( S5 & A5 & IA4 ) j 3S18 vcl = 3S7 | (3S20 & >A1) vdδ = (3S8 & A7 & A6) vd5 = (3S9 & >A5) vd4 = (3 s 9 & A5 & A4) vd3 = 3S10 ve5 = S13 ve3 = (3s 12 & A7 & A6 & A5 & A4 & A3) ve2 = (3S14 & A2) veO = 3S15 vf3 = 3S19 vfl = (3S20 & Al) if (ud7 ) 3w(9:0)= gb7(9-0) if (ud6 ) 3w(9:0)= gbδ(9:0) if (ud5 ) 3w(9:0)= gb5(9:0)

FIG. 8 is a block diagram, which illustrates encoder output circuit 262 (shown in FIG. 3) in greater detail. Encoder output circuit 262 includes code word generator 350 and RDS calculator 352. In one embodiment, code word generator 350 concatenates the g-group 10-bit code word segment gw_9:o with the j-group 10- bit code word segment jw_9:o to form a 20-bit code word on output Yι_9:o.

RDW calculator 352 calculates the next state based on the current state and the running digital sum of the current 20-bit code word provided on code word output Yi9:0. However if the current state is "1" (current RDS equals six) and the RDS of Yi9:o is six, then RDS calculator 352 inverts the 20-bit code word such that the cumulative RDS and the next state become "0". The resulting 20-bit code word is output to code word output Wi9_:0. An interleave circuit 354 can be used if desired, to interleave adjacent 20-bit code words as discussed above. Table 11 illustrates the logical operations performed by encoder output circuit 262 according to one embodiment of the present invention.

Table 11

Form Code Word

Y(19:10) = gw(9:0) ;

Y( 9: 0) = jw(9:0) ; if( Y(19: 0)==0xAAAAA ) Y(19 0) = 0xC03F3; if ( Y(19: 0)==0x55555 ) Y(19 0) = 0XC03FC;

RDS Calculator

HW=Y19+Y18+Y17+Y16+Y15+Y14+Y13+Y12+Y11+Y10+Y9 +Y8+Y7+Y6+Y5 +Y4+Y3+Y2+Y1 +Y0 RDS = (2*HW) -20

Note that Hamming weight (HW) of the code word Y(19:0) is the sum of the 20 code bits. The running digital sum (RDS) of the code word is calculated by subtracting the number of "0" by the number of "1" in the code word. For example, if there are 13 "1" (HW=13) and number of "0" is

(20-HW) , the RDS is HW-(20-HW)= (2*HW)-20.

In a sequence of code words, the cumulative RDS is the RDS of all bits from the beginning of the first code word to the end of the current code word. Note that the cumulative RDS in this design must be equal to either 0, or 6. This number determines the state of the encoder (state=0 when cumulative RDS is 0, state=l when cumulative RDS is 6. if(state==0 && RDS==0 ) { next state=0 W(19 0) = Y (19 0) } if(state==0 && RDS==6 ) next s tate=l W(19 0) = Y (19 0) } if(state==l && RDS==0 ) next state=l W(19 0) = Y (19 0) } if(state==l && RDS==6 ) next s tate=0 W(19 0) = !Y (19 0) }

2. Decoder

Fig. 9 is a block diagram of a decoder 400 for decoding 20-bit code words Wi9:ointo corresponding 18-bit user data words Ii7:0 with each cycle of WORD CLOCK. Decoder 400 includes decoder input circuit 402, g-group decoder 404, j- group decoder 406 and decoder output circuit 408, which are shown in more detail in FIGS. 10-19.

Decoder input circuit 402 receives a 20-bit code word Wι₉:0 with each rising edge of WORD CLOCK. Decoder input circuit 402 generates a corresponding g- group 10-bit code segment gc 9:0 and a corresponding j-group 10-bit code segment jcp_9:o. The g-group code segments are selectively inverted, based on the rurining digital sum of the code word Wι_9:o. G-group decoder 404 decodes the g-group 10-bit segment gcp_9:0 mto a corresponding g-group data word gdw_6;o and a corresponding G-type according to Tables 2 and 4 above. The G-type corresponds to the pattern listed in the G- type column of Table 4. Similarly, j-group decoder 406 decodes the j-group 10-bit code segment jcp9:o mto a corresponding j-group data word jdw7:0 and a corresponding J-lype. Again, the J-type pattern corresponds to the pattern provided in the corresponding J-type column in Table 4.

Decoder output circuit 408 regenerates the first, second and third user data word fragments from the g-group and j-group data words and the correspondmg G- and J-types and outputs the resulting 18-bit user data Λvord onto output Ii

FIG. 10 is a block diagram, which illustrates decoder input circuit 402 in greater detail. Decoder input circuit 402 includes 20-bit code word register 410, RDS evaluator 412 and input multiplexer 414. The rising edge of WORD CLOCK is used to clock the 20-bit code word Wi9:0 mto register 410. RDS evaluator 412 calculates the running digital sum of the latched code word WMi9:0 and generates a selective inversion signal SI if the running digital sum is less than zero. The RDS of code word wmi9_:0 is :

RDS = (2*HW) - 20, where HW is the Hamming weight of wmι_9:ϋ. If (RDS<0), then SI = l; else,.SI = 0.

Input multiplexer 414 selectively inverts the code word wmι_9;o as a function of signal SI, and separates the bits into the g-group code segment gcp_9:o and the j- group code segment jcp_9:o. Input multiplexer 414 also substitutes the pattern Ox AA A AA for 0xC03F3 and the pattern 0x55555 for the pattern 0xC03FC, which where clirrunated during encoding to avoid undesirable strings of code words. _ An example of the input multiplexer operation is shown in FIG. 10A.

Table 12 illustrates the logical operations performed by input multiplexer 414, accordmg to one embodiment of the present invention. Table 12

INPUT MUX if( wm(19 :0) ==0xC03F3 ) wm(19:0) = OxAAAAA; if( wm(19 :0)==0xC03FC) . wm(19:0) = 0x55555; if(SI=0) { gcp(9:0)= wm(19:10) ; jcp(9:0)= wm(9:0) ; } else { gcp(9:0) = !wm(19:10) ; jcp (9 : 0) = !wm(9 : 0) ; }

FIG.11 is a block diagram, which illustrates g-group decoder 404 in greater detail. G-group decoder 404 includes a digital sum circuit 420, which generates a five-bit signed value gds_4:o representing the digital sum of gcp9:0. The possible values of gds_4:o are 8, 6, 4, 2, 0, -2, -4, -6 and -8. If the digital sum is less than 0, inverter circuit 422 inverts gcp_9:o to generate gw_9:o.

Pattern generator 424 generates a 36-bit pattern that identifies one of the 36 possible g-subgroups with which gw_9:o can belong, as defined by Table 2 above. G-subgroup decoders 426 receive g-group code segment gw_9:0 and decodes the segment according to the 36-bit subgroup select pattern and generates a corresponding g-subgroup data word fragment and G-type for output multiplexer 428. Output multiplexer 428 selects the data word fragment and the G-type from the appropriate g-subgroup decoder 426 based on the g-subgroup select signal gds_4:o.

Table 13 illustrates the logical operation performed by some of the elements in g-group decoder 404, according to one embodiment of the present invention.

Table 13 GX Decoder

Input : gcp(9:0)

Output : gdw(6:0) , Gtype(7:0), gm (3:0)

get ds

Input : gcp(9:0)

Output : gds(4:0) gds(4:0) is a 5-bit signed value representing the digital sum of gcp(9:0) The possible values of gds(4:0) are 8, 6, 4, 2 0, -2, -4, -

6, and -£ .

Let HW be ; the Hamming weight of gcp(9:0), then gds (4:0) = (2*HW) -10

Inverter

Input : gcp(9:0) , gds(4:0)

Outpu : gw ( 9 : 0 )

If (gds>= = 0) {gw(9:0) = gcp( 9 :0) } else {gw(9:0) = !gcp(9:0) }

gen plO

Input : A(9:0)

Output : x(3:0) , y(15:0) , z(15:0) x[3]=A9&A8; x [2] =A9&! A8; x[l]=! A9&A8; x[0] =!A9&!A8; y[15]= A7& A6& A5& A4 z[15] = A3& A2& A1& A0 y[14]= A7& A6& A5&1A4 z[14] = A3& A2& Al&lAO y[13]= A7& A6&1 5& A4 z[13] = A3& A2&1A1& A0 y[12]= A7& A6&! A5&IA4 z[12] = A3& A2&1A1&1A0 y[ll]= A7&!A6& A5& A4 z[ll] = A3&IA2& A1& A0 y[10]= A7&1A6S: A5&1A4 z[10] = A3&IA2& A1&1A0 y[ 9]= A7&1A6&! A5& A4 z[ 9] = A3&IA2&1A1& A0 y[ 8]= A7&1A6&:! A5&1A4 z[ 8] = A3&!A2&!Al£i!A0 y[ 7]=!A7& A6& A5& A4 z[ 7] = !A3& A2& A1& A0 y[ 6] =!A7& A6& A5&1A4 z[ 6] = !A3& A2& A1&1A0 y[ 5]=!A7& A6&! A5& A4 z [ 5] = !A3& A2&IA1& A0 y[ 4]=!A7& A6&! A5&1A4 z [ 4] = !A3& A2&IA1&1A0 y[ 3] =!A7&!A6& A5& A4 z[ 3] = 1 3&IA2& A1& A0 y[ 2]=!A7&!A6S: A5&1A4 z[ 2] = 1A3&1A2& A1&1A0 y[ l]=!A7&!A6-i! A5& A4 z[ 1] = !A3&!A2&!A1& A0 y[ 0] =!A7&!A6&:! A5&1A4 z [ 0] = !A3&!A2S:!A1&!A0

FIG.12 is a block diagram, which illustrates "gb-" subgroup decoder 426 in greater detail. The gb-subgroup decoder 426 includes pattern decode circuit 440, gb-subgroup decoders 442 and multiplexer 444. Pattern decode circuit 440 generates a 6-bit select signal gb, which identifies the gb-subgroup (e.g., gbό) to which the g-group code segment gw_9:o belongs. Pattern decode circuit 440 also generates a three-bit signal gρ₂:0, which helps decode subgroups gb6 and gb7. The gb-subgroup decoders 442 decode gw_9:o into corresponding data word fragments according to Table 2. Multiplexer 444 selects the appropriate data word fragment from the appropriate gb-subgroup based on the select signal gb provided by pattern decode circuit 440. Multiplexer 444 also generates a gb-type output GBGT7_:o, which identifies the corresponding G-type that is selected by multiplexer 428 in FIG.11.

Table 14 illustrates the logical operations performed by gb-subgroup decoder 426.

Table 14

dec gb

Input: gw(9:0), x(3:0), y(15 :0), z(15:0)

Output : gbdw (6:0) , gbgt (7:0)

Pattern Decode

Input : X (3:0), y (15:0) , z (15 : 0)

Output gb7 gb6 , gb5 , gb4 , gb3 ,gb2 , gp(2 0) gb7= = (x[2] x[l])& ! (yto] |y [15] | z[7]) ' gb5= = (x[3] x[0])& (ytio] |y [9] |y [6] |y [5] ) ; gb4= = (x[3] x[0])& (yds] jy [0] j z [15] |; ![0]) gb6= = (x[3] x[0])& ! (gb5|gb4) ; gb3 = = (x[2] x[l])& (z[7]) _; gb2 = = (x[2] x[l])& (y[i5] |y [0] ) ; if ( gb7 )

{ gp [l] = y[i] |y[2] |y[4] 1 y[8] ; gp [2] = z[l] jz[2] |z[4] j z[8] ; gp to] = ! (gp[il |gp[2]) ;

} if( gb6 )

{ gp [0]= z[l] |z[2] |z[4] |z[8] gp [1]= z[14] |z [13] | z [11] |z [7] }

gbδa4= gbδa & A7; gbδa3= gb6a & ( A3 | A2 ) ; gbδa2= gbδa &( A3 j Al ) ; gb6al= 0; gbδa0= 0; gbδb4= gb6b &( A7 | A6 ) ; gb6b3= gb6b &( A7 j A5 ) ; gb6b2= gbδb & A3 ; gb6bl= gbδb &( A2 | !A0 ) ; gb6b0= gb6b &( A3 ^A Al ) ;

D5 = ! A9 ;

D4 = gbδa4 | gb6b4

D3 = gbδa3 j gb6b3

D2 = gbδa2 | gb6b2

Dl = gb6al j gbδbl

DO = gbδaO j gbδbO

dec gb5 Input : A9,A8,A7 ,A6,A5,A4,A3 ,A2,A1,A0 Output : D4,D3,D2 ,D1,D0 if (!A9) { A7=!A7; A5=!A5; A3=!A3; A2=!A2; A1=!A1; }

D4= !A9;

D3= A7;

D2= A5;

Dl= ( A3 A2 ) ;

D0= ( A3 Al ) ;

dec gb4 Input : A9,A8,A7 ,A6,A5,A4,A3 ,A2,A1,A0 Output D3,D2,D1 ,D0

if (1A8) { A9=!A9; A7=!A7; A6=!A6; A5=!A5; A4=!A4; A2=!A2; A1=!A1; A0=!A0; }

D3= !A8;

D2= ( A7 I A6 ) ;

Dl= ( A9 & ( (A5 ^Λ A4) (Al AO)) );

D0= ( A9 & ( (A6 ^Λ A4) (A2 AO)) ); dec qb3

Inpu : A9,A8,A7 ,A6,A5,A4,A3 ,A2,A1,A0

Output : D2,D1,D0

D2= A9;

Dl= ( A7 | A6 ) ;

D0= ( A7 j A5 ) ;

dec gb2

Input : A9,A8,A7 ,A6,A5,A4,A3 ,A2,A1,A0

Output : D1,D0

Dl= A7 '

D0= A9 '

Mux gb

Input : gb7D(6:0) ,gb6D(5:0) ,gb5D(4:0) ,gb4D(3:0) ,gb3D(2:0) ,gb2D(l: 0) gb7 , gb6 , gb5 , gb4 , gb3 , gb2

Output gbdw(6:0) , gbgt (7:0) if (gb7) {gbdw(6:0)= gb7D(6:0) , gbgt(7:0) = [0, 0,0, 0,0, 1,1,1] } if (gbδ) {gbdw(5:0)= gb6D(5:0) , gbdw(6)= 0, gbgt(7:0)=[0, 0,0, 0,0 ,1,1,0] } if (gb5) {gbdw(4:0)= gb5D(4:0) , gbdw (6 :5) = [0, 0] , gbgt (7:0 )=[0, 0,0, 0,0 ,1,0,1] } if (gb4) {gbdw(3:0)= gb4D{3:0) , gbdw (6 :4) = [0, 0, 0] , gbgt(7:0)=[0, 0,0, 0,0 ,1,0,0] } if (gb3) {gbdw(2:0)= gb3D(2:0) , gbdw (6:3) =[0,0,0,0] , gbgt (7:0 )=[0, 0,0, 0,0, 0,1,1] } if (gb2) {gbdw(l:0)= gb2D(l:0) , gbdw (6: 2) =[0,0,0,0,0] , gbgt(7:0)=[0, 0,0, 0,0 ,0,1,0] }

Note : In gbgt (7:0) = [ 0, 0, 0, 0, 0,1, 1,1] , the leading bit or leftmost bit is bit 7 and the trailing bit or rightmost bit is bit 0.

FIGS. 13-16 illustrate gc-, gd-, ge-, and gf-subgroup decoders 426, respectively, in greater detail. These subgroup decoders operate similar to the gb- subgroup decoder shown and described with respect to FIG. 12. The logical operations performed by the gc-, gd-, ge-, and gf-subgroup decoders shown in FIGS. 13-16 are illustrated in Tables 15-18, respectively.

Table 15

dec gc

Input: gw(9:0), x(3:0), y(15:0), z(15:0) Output : gcd (6:0), gcgt (7:0) Pattern Decode

Input : x(3:0) , y (15:0) , z (15 :0)

Outpu : gc7,gcδ,gc4 ,gcl, gp(5:0) gc7= x[2] |x[l] | (x[0]&(!y[15]&! z [15] ) ) ; gcδ= K [3]&(!z[0]&! z[7]&!z [15] ) ; gc4 = (x[0]&(y[15] | z[15])) | (x [3] &z [7] ) ; gcl= x [3]&(z[0] |z[15]) ; if( gc7 )

{ gp [0]= (x[2] |x[l])&(z[14] |z [13] | z [11] |z [7] ) ; gp [1]= (x[2] |x[l])&(y[14] |y [13] jyr.ll] jy [7] ) ; gp [2]= (x[2] |x[l])&z[15] ; gp [3]= x[0]&(!y [15] | !z[15]) ; gp [4]= (x[0]&(z [13] |z[14])) ; } if( g C6 )

{ gp [0]= x[3]&(z[3] |z[5] |z[6] |z[9] | z [10] | z [12] ) ; gp [1]= x[3]&(z[ll] |z[13] |z[14]) ; gp [2]= x[3]&(z[l] |z[2] |z[4] |z[8] ) ; } if( g = 4 )

{ gp [0]= x[0]&z[15] ; gp [1]= x[3]&z[7] ; }

dec gc7

Input : A9,A8,A7,A6,A5,A4,A3,A2,A1,A0, gp(4:0)

Output : D6 , D5 , D4 , D3 , D2 , Dl , DO gc7a = gp[o] ; gc7b = gp[i] gc7cd= = gp[2] gc7e = = gp[3] gc7a5= = 0; gc7a4= = gc7a &( A7 ^A !A6 ) ; gc7a3= gc7a &( A 7 & !A6 ) ; gc7a2= gc7a & !A4 ; gc7al= = gc7a &( !A1 | !A0 ) ; gc7a0= = gc7a &( !A2 j !A0 ) ,- gc7b5= = gc7b &( A3 ^A A2 ) ; gc7b4= = gc7b &( A3 ^A !A2 ) ; gc7b3= = gc7b &( A3 | !A2 ) ; gc7b2= = gc7b & !A0 ; gc7bl= = gc7b &( !A5 | !A4 ) ; gc7b0= = gc7b &( !A6 | !A4 ) ; gc7cd5 = gc7cd; gc7cd4 = gc7cd; gc7cd3 = 0; gc7cd2 = gc7cd &( !A3 | !A2 ) ; gc7cdl = gc7cd&((!A7 & (A7 ^A A6) | ( A7 & (Al ^A!A0)) ) ; gc7cd0 = gc7cd&(( A7 & (A7 ^A A6) j ( A5 & (A2 ^A!A0)) ) ; gc7e5= gc7e; gc7e4= gc7e; gc7e3= gc7e; gc7e2= gc7e &( !A2 | !A0 ) gc7el= gc7e &( !A5 j !A4 ) gc7e0= gc7e &( !A6 j !A4 )

D6 = A8|gp[4] ;

D5 = gc _-7a5 |gc7b5 |gc7cd5 |gc7e5

D4 = gc7a4 )gc7b4 |gc7cd4 |gc7e4

D3 = gc :7a3 |gc7b3 ]gc7cd3 |gc7e3

D2 = gc ^7a2 |gc7b2 |gc7cd2 |gc7e2

Dl = gcr7al |gc7bl j gc7cdl |gc7el

DO = gc ^7 0 jgc7b0 |gc7cd0 jgc7e0

dec gcδ

Input : A9,A8,A7,A6,A5,A4,A3,A2,A1,A0, gp(4:0)

Output : D5,D4,D3,D2 ,D1,D0 gcδa = gp[0] ; gcδb = gp [l] ; gcδc = gp[2] ; gc6a5= gc6a &( A7 & !A4 ) ; gcδa4= gc6a &( A7 ^A !A4 ) ; gcδa3= gcδa & !A5 ; gc6a2= gcδa & A3 ; gc6al= gc6a &( A2 | !A0 ) ; gcδaO= gcδa &( A3 ^A Al ) ; gcδb5= gc6b & !A0 ; gcδb4= gcδb & !A1 ; gcδb3= gcδb & ( A 7 | A6 ) ; gc6b2= gc6b &( A7 j A5 ) ; gcδbl= 0; gcδbO= 0; gcδc5= gcδc; gc6c4= gcδC; gc6c3= gcδc &( A3 1 A2 ) gc6c2= gc6c &( A3 j Al ) gc6cl= gcδc &( !A5 j !A4 ) gcδcO= gc6c &( !A6 j !A4 )

D5 = gcδa5 | gcδb5 |gc6c5; D4 = gc6a4 gc6b4 |gc6c4 D3 = gc6a3 gcδb3 |gcδc3 D2 = gcδa2 gcδb2 |gc6c2 Dl = gcδal gc6bl jgcδcl DO = gcδaO gc6b0 |gcδcO

dec gc4

Input : A9,A8,A7,A6,A5,A4,A3,A2,A1,A0, gp(4:0) Output : D3,D2,D1,D0 gc4ab= gp[0] ; gc4c = gp[i]; gc4ab3 = gc4ab &( !A3 I !A2 | !A1 ) ; gc4ab2 = gc4ab & ( A7 & A3 ) ; gc4abl = gc4ab&(!A4 | (!A0 | ( A6 & A2) ) ) ; gc4ab0= gc4ab&(!A9 & ( (A7 ^A A5) | (A3 ^A Al)) ); gc4c3= gc4c & ( A7 A6 ) ; gc4c2= gc4c &( A7 A5 ) ; gc4cl= 0; gc4c0= 0;

D3 = gc4ab3 |gc4c3

D2 = gc4ab2 |gc4c2

Dl = gc4abl |gc4cl

DO = gc4ab0 |gc4c0

dec gel

Input: A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 Output : DO

D0= A7 ;

Mux gc Input : gc7D(6:0) ,gc6D(5:0), gc4D (3 : 0) , gc ID (0) gc7,gc6,gc4,gcl

Output gcdw(6:0) , gcg (7:0) if (gc7) {gcdw(6 = gc7D(6:0) , gcgt (7 =[0,0,0,1,0,1,1,1] if (gcδ) {gcdw(5 = gc6D(5:0) , gcdw(6) = 0, gcgt (7 =[0,0,0,1,0,1,1,0] if (gc4) {gcdw(3 = gc4D(3:0) , gcdw(6:4) = [0,0,0] gcgt (7 = [0,0,0,1,0 ,1,0,0] if (gel) {gcdw(0)= gclD(O) gcdw(6:l) = [0,0,0,0,0, 0] gcgt (7:0) =[0,0, 0,1,0 ,0,0,1]

Table 16

dec gd

Input : gw(9:0) , x(3:0) , y{15 :0) , z(15:0)

Output : gddw(6:0), gdgt(7:0)

Pattern Decode

Input : x(3:0) , y (15:0) , z (15 :0)

Output : gd6,gd5,gd4 ,gd3, gp(3:0) gd6= x [3] |x[0] ; gd5= ( x[2] |x[l]) & (!y[15]&!z[15]) ; gd4= ( x[2] |x[l]) & ( (y[15]&(!z [3] & z[12])) ] (z[15]&(!y[3]&!y[12])) ) ; gd3= ( x[2] |x[l]) &( (y[15]&( z [3] | z[12])) j (z[15]&( y[3] | y[12])) ) ; if( gd 6 )

{ gp[0] = z[7] |z[ll] |z[13] |z[14] ; gp[l] = y[7] |y[ll] |y[13] |y[14] ; gp[2] = x[3]&(y [15] |z[15]) ; gp[3] = x[0]&(y [15] |z[15]) ; }

dec gdδ

Input : A9,A8,A7,A6,A5,A4,A3,A2,A1, AO, gp(3:0)

Output : D5,D4,D3,D2 ,D1,D0 gdδa = gp[o] ; gdδb = gp[il gd6cd= gp[2] gd6ef= gp[3] gdδa5= 0; gd6a4= gdδa &( A7 ^A !A6 ) ; gd6a3= gd6a & ( A7 & !A6 ) ; gdδa2= gdδa & !A4 ; gdδal= gdδa &( !A1 | !A0 ) ; gd6a0= gdδa &( !A2 j !A0 ) ; gdδb5= gdδb &( A3 ^A A2 ) ; gd6b4= gdδb &( A3 ^A !A2 ) ; gd6b3= gdδb &( A3 | !A2 ) ; gd6b2= gd6b & !A0 ; gdδbl= gdδb &( !A5 | !A4 ) ; gdδb0= gdδb &( !A6 j !A4 ) ; gdδcd5= gdδcd; gd6cd4= gdδcd; gdδcd3 = 0 ; gdδcd2= gdδcd &( !A3 | !A2 ); gd6cdl= gdδcdδ:( A9 & ( (A7 ^A Aδ) (A3 ^A A2)) ); gd6cd0= gd6cd&( A 9 & ( (A7 ^A A5) (A3 ^A Al)) ) ; gdδef5= gd6ef; gdδef4= gdδef; gdδef3= gdδef; gdδef2= gdδef & ( !A3 | !A2 | !A1 I !A0 ) ; gdδef1= gd6ef &( !A5 j !A4 j !A1 I !A0 ) ; gd6ef0= gdδef &( !A6 j !A4 j !A2 ! !A0 ) ;

D5 = gdδa5 | gd6b5 |gd6cd5 | gdδ ef5 D4 = gd6a4 j gd6b4 |gd6cd4 | gdδ ef4 D3 = gdδa3 jgdδb3 |gd6cd3 jgd6ef3 D2 = gd6a2 j gdδb2 jgdδcd2 j gdδef2 Dl = gd6al jgdδbl jgdδcdl j gdδ ef1 DO = gdδaO jgdδbO jgdδcdO jgdδεfO

dec gd5

Input : A ,A8 , A7 , A 6 , A5 , A4 , A3 , A2 , A] L,A0

Output: D4,D3,D2,D1 ,D0

D4= !A9;

D3= ( !A1 | 1A0 )

D2= ( !A2 j !A0 )

Dl= ( !A5 | !A4 )

D0= ( :A6 1 !A4 )

dec gd4

Input : A9 , A8 ,A7 , A 6 , A5 , A4 , A3 , A2 , A] .,A0

Output: D3,D2,D1,D0

D3= ( !A3 | !A2 ) ;

^• D2= A9;

Dl= ( !A6 | !A2 ) ;

D0= ( !A4 j !A0 ) ;

dec gd3

Input: A9,A8,A7,A6,A5,A4,A3,A2,A_ .,A0 Output : D2 , Dl , DO

D2 = ( !A3 I !A1 ) ;

Dl = A9;

DO = ( !A5 I !A1 ) ;

Mux gd

Input : gd6D(5:0) ,gd5D(4:0) ,gd4D(3:0) ,gd3D(2:0) gd6 , gd5 , g d4 , gd3

Output : gddw(6:0) , gdgt (7:0) if (gdδ) { gddw ( 5 0)= gd6D(5:0) , gddw(6)= 0, gdgt (7 0) = [0, 0,1,0, 0 ,1,1,0] if (gd5) {gddw (4 0)= gd5D(4:0-) , gcdw (6 : 5) = [0, 0] , gdgt (7 0 )=[0,0,1,0,0 ,1,0,1] if (gd4) {gdd (3 0)= gd4D(3:0) , gcdw(6 : 4) = [0, 0, 0] , gdgt (7 0) = [0,0, 1,0,0 ,1,0,0] if (gd3) {gddw (2 0)= gd3D(2:0) , gcd (6 : 3) = [0, 0, 0, 0] gdgt (7 0) = [0, 0,1, 0,0, 0,1,1]

Table 17

dec ge

Input : gw(9:0) , ■ x(3:0) , y(15 :0), z(15:0) Output : gedw(6:0) , gegt (7:0)

Pattern Decode

Input : x(3:0) , y (15:0) , z(15 :0) Output : ge5,ge3, gp (1:0) ge5= x [2] |x[l] I (x[ 3] &( !y [15] &! z [15] )) ; ge3= x[3]&(y[15] |z [15])&(! (y[3] |y[12] |z[3] | z [12] ) ) ge2= x[3]&(y[15] jz [15] ) &( (y [3] |y[12] |z[3] | z [12] ) ) ; ge0= x [0] ; if( ge5 ) { gp[0] = x[3] ; gp[i] = y[15] I z[15] ;

}

dec ge5

Input : A9 , A8 , A7 , A 6 , A5 , A4 , A3 , A 2 , Al , A0 , gp(l:0) Output : D4,D3,D2,D1, DO ge5a = gp[0] ; ge5bc= gp[l] ; ge5a4= 0; ge5a3= ge5a &( !A5 | !A4 ) ge5a2= ge5a & ( !A6 j !A4 ) ge5al= ge5a &( !A1 j !A0 ) ge5a0= ge5a &( !A2 | !A0 ) ge5bc4 = ge5bc ; ge5bc3 = ge5bc &( !A3 !A2 !A1 I !A0 ) ; ge5bc2 = ge5bc & A9; ge5bcl= ge5bc & ( !A5 !A4 !A1 !A0 ) ; ge5bc0: ge5bc &( !A6 !A4 !A2 !A0 ) ;

dec ge3

Input: A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 Output: D2,D1,D0

D2= ( !A3 I !A2 ) Dl= ( !A6 I !A2 ) D0= ( !A4 !A0 )

dec ge2

Inpu : A9 , A8 , A7 , A 6 , A5 ,A4 ,A3 , A2 , Al , AO Output: D1,D0

Dl= ( !A3 !A1 ) ; D0= ( !A5 !A1 ) ;

Mux ge Input : ge5D(4:0) ,ge3D(2:0) ,ge2D(l:0) ge5,ge3 ,ge2,ge0

Output : gedw(6:0) , gegt(7:0) if (ge5) {gedw(4:0)= ge5D(4:0) , gedw(6:5) =[0,0] , gegt (7:0) = [0,0, 1,1,0, 1,0,1] if (ge3) {gedw(2 0)= ge3D(2:0) , gedw(6 :3) = [0, 0, 0, 0] , gegt(7 0)=[0,0,1,1,0 ,0,1,1] } if (ge2) {gedw(l 0)= ge2D(l:0) , gedw(6:2) =[0,0,0,0,0] , gegt(7 0 )=[0,0,1,1,0 ,0,1,0] } if (geO) {gedw(6 0) = [0,0,0,0,0 ,0,0] , gegt (7:0 ) = [0,0, 1,1, 0,0, 0,0] }

Table 18

dec gf

Inpu .- gw{9:0), x(3:0) , y(15 :0), z(15:0) Output : gfdw(6:0), gfgt(7:0)

Pattern Decode

Input: x(3:0), y(15:0) , z(15 :0)

Output : gp ( 1 : 0 ) gf3= x [3] ; gfl= !x[3] ;

dec gf3

Input : A9,A8,A7,A6,A5,A4,A3,A2,A1,A0, gp(l:0) Outpu : D2,D1,D0

D2= ( !A3 !A2 !A1 I !A0 ) Dl= ( !A5 !A4 !A1 I !A0 ) D0= ( !A6 !A4 !A2 I !A0 )

dec gfl

Inpu : A3 , A8 , A7 ,A 6 ,A5 , A4 , A3 , A ,Al , A0 Output : DO

D0= A9;

Mux gf Input : gf3D(2:0) , gflD(0) gf3,gfl

Output gfdw(6:0) , gfg (7:0)

FIG. 17 is a block diagram, which illustrates j-group decoder 406 (shown in FIG. 9) in greater detail. J-group decoder 406 includes input circuit 500, j- subgroup decoders 502 and output multiplexer 504. Input circuit 500 receives the j-group 10-bit code segment jcp9:0 and the most significant four bits grri3:o of the G- type from g-group decoder 404 (shown in FIG. 9). Input circuit 500 generates a 10-bit j-group word segment jW9:0, which is selectively inverted, and generates a five-bit digital sum value jds_4:o for the segment and a 36-bit subgroup select signal XYZ. J-subgroup decoders 502 decode the j-group code segment j ^o based on the XYZ select signal and the definitions provided in Table 2. J-subgroup decoders 502 are identical to g-subgroup decoders 426 shown in FIG. 11. Output circuit 504 selects the appropriate output from j-subgroup decoders 502 to form the j-group user data word fragment jdw7:o and the corresponding J-type7:0. FIG. 18 is a block diagram, which illustrates input circuit 500 in greater detail. Input circuit 500 includes inverters 510 and 512, digital sum calculator 514 and pattern generator 516. Inverter 500 selectively inverts the j-group code segment jcp₉-.o as a function of the G-type bits gm3:0 and produces a selectively inverted output juwo. Digital sum calculator 514 calculates the digital sum, jds_4:o, of ju9:0, wherein the possible values of jds_4:o are 10, 8, 6, , 2, 0, -2, -4, -6 and -8. If jds_4:0 is less than zero, ju_9:o must be inverted again, and invert select signal nj is activated. Inverter 512 selectively inverts ju_9:o as a function of the signal nj and produces the j-group code segment jw_9:o for decoding. Pattern generator 516 generates a 36-bit select pattern XYZ based o o o on the pattern formed by jw9:o.

Table 19 illustrates the logical operation_{I II I II}s performed by input circuit 500, according to one embodiment of the present invention.

Table 19

INV A

Input: jcp(9:0), gm(3 0) Output: ju(9:0) ju(9:0) = jcp(9 :0) ; if (gm(3:0) == 0x2) { ju(9 jcp(9 0) if (gm(3:0) == 0x3) { ju(9 jcp(9 0) if (gm(3:0) == 0x9) { ju(9 jcp(9 0)

get jds

Input: ju (9:0) Output: nj, jds (5,0) get_jds calculates the digital sum of ju(9:0)

Let HW be the Hamming weight of ju(9:0), then its digital sum, jds = (2*HW) -10

The possible values of jds(4:0) are 10, 8, 6, 4, 2, 0, -2, -4, -6, and 8. if ( jds < 0 ) nj=l; else nj=0;

INV B

Input : ju(9:0), nj Output : jw(9:0) if (nj 1) { jw(9:0) = !ju(9:0) ; } else { jw (9 0) = ju (9 = 0); }

gen plO is the same as that in GX Decoder.

_{II II II II II II II 1!} o o o o X X X X

Table 20 illustrat _to _{C t t}oOoe _to _{C t} OOπs the logical operations performed by j-group output circuit 504 shown in FIG.17.

Table 20

JX Output

Input: gbdw (6:0), gcd (6:0), gddw (6:0), gedw(6:0), gfdw(6:0) , gbgt (7:0), gcgt (7:0), gdgt (7:0), gegt (7:0), gfgt(7:0) gm(3:0), jds(4:0) Output: jdw(7:0), jt(7,0) if (gm(3:0) = 0x0) or (gm(3:0) = 0x3) { if (jds= 0)

{ if (gbgt == 0x07) { jdw(7 : 0 ) = (gbdw (6 : 0) &0x7F) ; if (gbgt == 0x06) { jdw(7 : 0 ) = (gbdw(6 : 0) &0x3F) | 0x80 if (gbgt == 0x05) { jdw(7 : 0 ) = (gbdw(6 : 0) &0xlF) j OxCO if (gbgt == 0x04) { jdw(7 : 0 ) = (gbdw(6 : 0) &0x0F) j OxEO if (gbgt == 0x03) { jdw(7 : 0 ) = (gbdw(6 : 0) &0x07) j OxFO if (gbgt == 0x02) { jdw(7 : 0 ) = (gbdw(6 : 0) &0x03) ; L^JJJ _C L L_J L ^{l lJ lJ} L^J _{J lJJ}........._.____ \ tttt^ttttt r r r r r _r r r r

1 ^{II IIII I} _III ^{I I III} _{II I II} if (jds= 6) o o o o o o o o o o X X X X X X X X X X

{ if (gegt { jdw(7:0 )=(gedw(6:0) &0xlF) ; o o o o o o o o o o to o _to ^t oo oa oo o o _CDπoo if (gegt { jdw(7:0 )=(gedw(6:0) &0x07) | 0xF8 if (gegt { jdw(7:0 )=(gedw(6:0) &0x03) j 0x04 if (gegt 1 { jdw(7:0) = (0x00) ; j if (gm(3:0) = 0x3) { jt = (jt&0x0F) | 0x30; }

} if (gm(3:0) = 0x1) or (gm (3:0) = 0x2) if (jds= -2) { if (gcgt == 0x17) { jdw(7 0 )= (gcdw (6:0) &0x7F) jt=0xl8 if (gcgt == 0x16) { jdw(7 0)=(gcdw(6:0) &0x3F) 0x80 ; jt=0xl8 if (gcgt == 0x14) { jdw(7 0 )= (gcdw (6:0) &0x0F) 0x20 ; jt=0xl6 if (gcgt == 0x11) { jdw(7 0)=(gcdw{6:0) &0x01) jt=0xll

} if (jds= 4)

{ if (gdgt = === 00xx2266)) {{ jjddww((77 0)=(gddw(6:0) &0x3F) | OxCO ; jt=0xl8 if (gdgt = === 00xx2255)) {{ jjddww((77 0)=(gddw(6:0) &0xlF) ; jt=0xlδ if (gdgt = === 00xx2244)) {{ jjddww((77 0)=(gddw(6:0) &0x0F) |θ0xx3300;; jt=0xlδ if (gdgt = === 00xx2233)) {{ jjddww((77 0)=(gddw(6:0) &0x07) ; jt=0xl3

} if (gm(3:0) = 0x2) { jt = (jt&OxOF) I 0x20; } if (gm(3 : 0) == 0x4) or (gm(3:0) = 0x9) { if (jds= -2)

{ if (gcgt == 0x17) { jdw(7:0 )=(gcdw(6:0) &0x7F) jt=0x47 ^■ } if (gcgt == 0x16) { jdw(7:0 )=(gcdw(6:0) &0x3F) jt=0x46 - } if (gcgt == 0x14) { jdw(7:0 )=(gcdw(6:0) &OxOF) j =0x44 ^• } if (gcgt == 0x11) { jdw(7:0 )=(gcdw(6:0) &0x01) jt=0x42 ^• }

} if (jds= -8) { if (gfgt == 0x43) { jdw(7:0 ) = (gfdw(6:0) &0x07) ; jt=0x43 ^• } if (gfgt == 0x41) { jdw(7:0) = (gfdw(6:0) &0x01) |θx02; jt=0x42 ^• }

1 if (gm(3:0) = 0x9) { jt = (jt&OxOF) | 0x90; }

} if (gm(3: 0) = OxA) { if (jds= 4) { if (gdgt = 0x26 ) { jdw(7:0) = (gddw(6:0) &0x3F) ; jt=0xA6; } if (gdgt = 0x25 ) { jdw(7:0) = (gddw(6:0)&0xlF) ; jt=0xA5; } if (gdgt = 0x24 ) { jdw(7:0) = (gddw(6:0)&0x0F) ; jt=0xA4; } if (gdgt = 0x23 ) { jdw(7:0) = (gddw(6:0)&0x07) ; jt=0xA3; }

} if (jds= 10)

{ jdw(7:0)=(0x00 ) ; jt=0xA0;

}

} if (gm(3: 0) = OxB) { if (gegt = 0x35) { jdw(7:0)=(gedw(6:0) &OxlF) , jt=0xB5 } if (gegt = 0x33) { jdw(7:0)=(gedw(6:0) &0x07) , jt=0xB3 } if (gegt = 0x32) { jdw(7:0) = (gedw(6:0) &0x03) , jt=0xB2, } if (gegt = 0x30) { jdw(7:0)=(0x00) ; jt=OxBO, }

} if (gm(3: 0) = OxC) { if (gfgt = 0x43) { jdw(7:0)=(gfdw(6:0) &0x07) ; jt=0xC3, } if (gfgt = 0x41) { jdw(7:0)=(gfdw(6:0) &0x01) ; jt=OxCl, }

}

FIG. 19 is a block diagram, which illustrates decoder output circuit 408

(shown in FIG. 9) in greater detail. Decoder output circuit 408 combines the appropriate bits of g-group data word fragment dgW6:0 and j-group data wprd fragment jdw7_:0 according to Table 4 and the values of the G-type7:0 and J-type7:₀ to produce the original 18-bit user data word Ii7:0. Table 21 illustrates the logical operations performed by decoder output circuit 408, according to one embodiment of the present invention.

Table 21

Decoder Output

Input : gd (6:0), jdw(7:0) , Gtype(7:0), Jtype(7:0)

Output: 1(18:0)

if ( (gt==0x07)&&(jt==0x08) ) { 1(17:15)= [0,0,0] ;

I(14:8)=gdw(6:0) ; I(7:0)=jdw(7:0) ; } if ( (gt==0xl7)&&(jt==0xl8) ) { 1(17:15)= [0,0,1] ;

I(14:8)=gdw(6:0) ; I(7:0)=jdw(7:0) ; } if ( (gt== 0x06) &&(jt== 0x08) ) { 1(17:14)= [0,1,0,0] ;

I(13:8)=gdw(5:0) ; I(7:0)=jdw(7:0) ; } if ( (gt== 0x16) &&(jt== 0x18) ) { 1(17:14)= [0,1,0,1] ;

I(13:8)=gdw(5:0) ; I(7:0)=jdw(7:0) ; } if [ (gt== 0x26) &&(jt== 0x28) ) { 1(17:14)= [0,1,1,0] ;

I(13:8)=gdw(5:0) ; I(7:0)=jdw(7:0) ; } if (gt==0x97)&&(jt==0x97) ) { 1(17:14)= [0,1,1,1] ;

I(13:7)=gdw(6:0) ; I(6:0)=jdw(6:0) ; } if (gt==0x05)&&(jt==0x08) ) { 1(17:13)= [1,0,0,0,0] ;

I(12:8)=gdw(4:0) ; I(7:0)=jdw(7:0) ; } if (gt== 0x17) &&(jt== 0x16) ) { 1(17:13)= [1,0,0,0,1] ;

I(12:6)=gdw(6:0) ; I(5:0)=jdw(5:0) ; } if (gt== 0x25) &&(jt== 0x28) ) { 1(17:13)= [1,0,0,1,0] ;

I(12:8)=gdw(4:0) ; I(7:0)=jdw(7:0) ; } if (gt== 0x35) &&(jt== 0x38) ) { 1(17:13)= [1,0,0,1,1] ;

I(12:8)=gdw(4:0) ; I(7:0)=jdw(7:0) ; } if (gt== 0x97) &&(jt== 0x96) ) { 1(17:13)= [1,0,1,0,0] ;

I(12:6)=gdw(6:0) ; I(5:0)=jdw(5:0) ; } if (gt== 0x96) &&(jt== 0x97) ) { 1(17:13)= [1,0,1,0,1] ;

I(12:7)=gdw(5:0) ; I(6:0)=jdw(6:0) ; } if (gt==0x07)&&(jt==0x05) ) { 1(17:12)= [1,0,1,1,0,0] ;

I(ll:5)=gdw(6:0) ; I(4:0)=jdw(4:0) ; } if (gt==0x04)&&(jt==0x08) ) { 1(17:12)= [1,0,1,1,0,1] ;

I(ll:8)=gdw(3:0 ) ; I(7:0)=jdw(7:0) ; } if (gt== 0x16) &&(jt== 0x16) ) { 1(17:12)= [1,0,1,1,1,0] ;

I(ll:6)=gdw(5:0) ; I(5:0)=jdw(5:0) ; } if (gt==0xl4)&&(jt==0xl8) ) { 1(17:12)= [1,0,1,1,1,1] ;

I (11:8) =gdw (3:0) ; I(7:0)=jdw(7:0) ; } if (gt==0x26)&&(jt==0x26) ) { 1(17:12)= [1,1,0,0,0,0] ;

I(ll:6)=gdw(5:0 ) ; I(5:0)=jdw(5:0) ; } if ( (gt== 0x24) &&(jt== 0x28) ) { 1(17:12)= [1,1,0,0,0,1] ;

1(11 :8)=gdw (3:0) ; I(7:0)=jdw(7:0) ; } if ( (gt== 0x96) &&(jt== 0x96) ) { 1(17:12)= [1,1,0,0,1,0] ;

I(ll:6)=gdw(5:0) ; I(5:0)=jdw(5:0) ; } if ( (gt==0xA6)S:&(jt==0xA6) ) { 1(17:12)= [1,1,0,0,-1,1] ;

I(ll:6)=gdw(5:0) ; I(5:0)=jdw(5:0) ; } if ( (gt==0x06)&S:(jt==0x05) ) { 1(17:11)= [1,1,0,1,0,0 ,0] ;

I(10:5)=gdw(5:0 ) ; I(4:0)=jdw(4:0) ; } if ( (gt== 0x03 )&&(jt== 0x08) ) { 1(17:11)= [1,1,0,1,0,0 ,1];

I(10:8)=gdw(2:0) ; I(7:0)=jdw(7:0) ; } if ( (gt== 0x25) &&(jt== 0x26) ) { 1(17:11)= [1,1,0,1,0,1 ,0] ;

I(10:6)=gdw(4:0) ; I(5:0)=jdw(5:0) ; } if ( (gt==0x23) &&(jt==0x28) ) { 1(17:11)= [1,1,0,1,0,1 ,1] ;

I(10:8)=gdw(2:0) ; I(7:0)=jdw(7:0) ; } if ( (gt== 0x33 )&&(jt== 0x38) ) { 1(17:11)= [1,1,0,1,1,0 ,0];

I(10:8)=gdw(2:0) ; I(7:0)=jdw(7:0) ; } if ( (gt== 0x97) &&(jt== 0x94) ) { 1(17:11)= [1,1,0,1,1,0 ,1];

I(10:4)=gdw(6:0) ; I(3:0)=jdw(3:0) ; } if (gt== 0x94) &&(jt== 0x97) ) { 1(17:11)= [1,1,0,1,1,1 ,0] ;

I(10:7)=gdw(3:0) ; I(6:0)=jdw(6:0) ; } if ( (gt==0xA6)&&(jt==0xA5) ) { 1(17:11)= [1,1,0,1,1,1 ,1];

I(10:5)=gdw(5:0) ; I(4:0)=jdw(4:0) ; } if ( (gt==0XA5)&&(jt==0XA6) ) { 1(17:11)= [1,1,1,0,0,0 ,0];

I(10:6)=gdw(4:0) ; I(5:0)=jdw(5:0) ; } if ( (gt==0X07)&&(jt==0X03) ) { 1(17:10)= [1,1,1,0,0,0 ,1,0] ;

I(9:3)=gdw(6:0) ; I(2:0)=jdw(2:0) ; } if (gt== 0X05) &&(jt== 0X05) ) { 1(17:10)= [1,1,1,0,0,0 ,1,1] ;

I(9:5)=gdw(4:0) ; I(4:0)=jdw(4:0) ; } if (gt==0X02)&&(jt==0X08) ) { 1(17:10)= [1,1,1,0,0,1 ,0,0] ;

I(9:8)=gdw(3:0) ; I(7:0)=jdw(7:0) ; } if (gt==0X17)&&(jt==0X13) ) { 1(17:10)= [1,1,1,0,0,1 ,0,1] ;

I(9:3)=gdw(6:0) ; I(2:0)=jdw(2:0) ; } if (gt==OX14)&&(jt==0X16) ) { 1(17:10)= [1,1,1,0,0,1 ,1,0] ;

I(9:6)=gdw(3:0) ; I(5:0)=jdw(5:0) ; } if (gt== 0X24) &&(jt== 0X26) ) { 1(17:10)= [1,1,1,0,0,1 ,1,1] ;

I(9:6)=gdw(3:0) ; I(5:0)=jdw(5:0) ; } if (gt==0X35)&&(jt==0X35) ) { 1(17:10)= [1,1,1,0,1,0 ,0,0] ;

I(9:5)=gdw(4:0) ; I(4:0)=jdw(4:0) ; } if (gt==0X32)&&(jt==0X38) ) { 1(17:10)= [1,1,1,0,1,0 ,0,1];

I(9:8)=gdw(l:0) ; I(7:0)=jdw(7:0) ; } if (gt==0X43)&&(jt==0X47) ) { 1(17:10)= [1,1,1,0,1,0 ,1,0] ;

I(9:7)=gdw(2:0) ; I(6:0)=jdw(6:0) ; } if (gt== 0X97) &&(jt== 0X93) ) { 1(17:10)= [1,1,1,0,1,0 ,1,1] ;

I(9:3)=gdw(6:0) ; I(2:0)=jdw(2:0) ; } if (gt== 0X96) &&(jt== 0X94) ) { 1(17:10)= [1,1,1,0,1,1 ,0,0] ;

I(9:4)=gdw(5:0) ; I(3:0)=jdw(3:0) ; } if (gt== 0X94) &&:(jt== 0X96) ) { 1(17:10)= [1,1,1,0,1,1 ,0,1] ;

I(9:6)=gdw(3:0) ; I(5:0)=jdw(5:0) ; } if (gt==0XA6)&&(jt==0XA4) ) { 1(17:10)= [1,1,1,0,1,1 ,1,0] ;

I(9:4)=gdw(5:0) ; I(3:0)=jdw(3:0) ; } if (gt==0XA5)&&(jt==0XA5) ) { 1(17:10)= [1,1,1,0,1,1 ,1,1] ;

I(9:5)=gdw(4:0) ; I(4:0)=jdw(4:0) ; } if (gt==0XA4)£:&:(jt==0XA6) ) { 1(17:10)= [1,1,1,1,0,0 0,0] ;

I(9:6)=gdw(3:0) ; I(5:0)=jdw(5:0) ; } if ( (gt==0XB5)&&(jt==0XB5) ) { 1(17:10)= [1,1,1,1,0,0 0,1] ;

I(9:5)=gdw(4:0) ; I(4:0)=jdw(4:0) ; } if ( (gt==0X06)&&(jt==0X03) ) { 1(17: 9)= [1,1,1,1,0,0 1,0,0] ;

I(8:3)=gdw(5:0) ; I(2:0)=jdw(2:0) ; } if (gt== 0X04) &&(3t== 0X05) ) { 1(17: 9)= [1,1,1,1,0,0 1,0,1] ;

I(8:5)=gdw(3:0) ; I(4:0)=jdw(4:0) ; } if (gt==0X16)&&(jt==0X13) ) { 1(17: 9)= [1,1,1,1,0,0 1,1,0] ;

1(8 :3)=gdw(5:0) ; I(2:0)=jdw(2:0) ; } if ( (gt==0Xll)&&(jt==0X18) ) { 1(17: 9)= [1,1,1,1,0,0 1,1,1] ; I(8)=gdw(0) ; I(7:0)=jdw(7:0) ; } if ( (gt==0X26) &&(j ==0X23) ) { 1(17: 9)= [1,1,1,1,0,1 ,0,0,0] ;

I(8:3)=gdw(5:0) ; I(2:0)=jdw(2:0) ; } if ( (gt==0X23)&&(jt==0X26) ) { 1(17: 9)= [1,1,1,1,0,1 ,0,0,1] ;

1(8 :6)=gdw(2:0) ; I(5:0)=jdw(5:0) ; } if ( (gt==0X43) &&(jt==0X46) ) { 1(17: 9)= [1,1,1,1,0,1 ,0,1,0] ;

I(8:6)=gdw(2:0) ; I(5:0)=jdw(5:0) ; } if (gt== 0X97) &&(jt== 0X92) ) { 1(17: 9)= [1,1,1,1,0,1 ,0,1,1] ;

I(8:2)=gdw(6:0) ; l(l:0)=jdw(l:0) ; } if (gt==0X96)&&(jt==0X93) ) { 1(17: 9)= [1,1,1,1,0,1 ,1,0,0] ;

I(8:3)=gdw(5:0) ; I(2:0)=jdw(2:0) ; } if (gt==0XA6)&&(jt==0XA3) ) { 1(17: 9)= [1,1,1,1,0,1 ,1,0,1] ;

I(8:3)=gdw(5:0) ; I(2:0)=jdw(2:0) ; } if (gt==0XA5) &&(jt==0XA4) ) { 1(17: 9)= [1,1,1,1,0,1 ,1,1,0] ;

I(8:4)=gdw(4:0) ; I(3:0)=jdw(3:0) ; } if (gt==0XA4)&&(jt==0XA5) ) { 1(17: 9)= [1,1,1,1,0,1 ,1,1,1] ;

1(8 :5)=gdw(3:0) ; I(4:0)=jdw(4:0) ; } if (gt==0XA3) &&(jt==0XA6) ) { 1(17: 9)= [1,1,1,1,1,0 ,0,0,0] ;

I(8:6)=gdw(2:0) ; I(5:0)=jdw(5:0) ; } if (gt== 0X05 )&&(jt== 0X03) ) { 1(17: 8)= [1,1,1,1,1,0 ,0,0,1,0] ,•

I(7:3)=gdw(4:0) ; I(2:0)=jdw(2:0) ; } if (gt==0X03) &&(jt==0X05) ) { 1(17: 8)= [1,1,1,1,1,0 ,0,0,1,1] ;

I(7:5)=gdw(2:0) ; I(4:0)=jdw(4:0) ; } if (gt== 0X17) &&(jt== 0X11) ) { 1(17: 8)= [1,1,1,1,1,0 ,0,1,0,0] ;

I(7:l)=gdw(6:0) ; l(0)=jdw(0); } if (gt==0X25)&&(jt==0X23) ) { 1(17: 8)= [1,1,1,1,1,0 ,0,1,0,1] ;

I(7:3)=gdw(4:0) ; I(2:0)=jdw(2:0) ; } if (gt== 0X35) &&(jt== 0X33) ) { 1(17: 8)= [1,1,1,1,1,0 0,1,1,0] ;

I(7:3)=gdw(4:0) ; I(2:0)=jdw(2:0) ; } if (gt== 0X33) &&(jt== 0X35) ) { 1(17: 8)= [1,1,1,1,1,0 ,0,1,1,1] ;

I(7:5)=gdw(2:0) ; I(4:0)=jdw(4:0) ; } if (gt== 0X30) &&(jt== 0X38) ) { 1(17: 8)= [1,1,1,1,1,0 1,0,0,0] ; I(7:0)=jdw(7:0) ; } if (gt==0X41)&&(jt==0X47) ) { 1(17: 8)= [1,1,1,1,1,0 ,1,0,0,1] ;

I(7)=gdw(0) ; I(6:0)=jdw(6:0) ; } if (gt== 0X96) &&(jt== 0X92) ) { 1(17: 8)= [1,1,1,1,1,0 ,1,0,1,0] ;

I(7:2)=gdw(5:0) ; l(l:0)=jdw(l:0) ; } if (gt== 0X94) &&(jt== 0X94) ) { 1(17: 8)= [1,1,1,1,1,0 1,0,1,1] ;

I(7:4)=gdw(3:0) ; I(3:0)=jdw(3:0) ; } if (gt== 0X91) &&(jt== 0X97) ) { 1(17: 8)= [1,1,1,1,1,0 1,1,0,0] ;

I(7)=gdw(0) ; I(6:0)=jdw(6:0) ; } if (gt==0XA5)&S:(jt==0XA3) ) { 1(17: 8)= [1,1,1,1,1,0 1,1,0,1] ;

I(7:3)=gdw(4:0) ; I(2:0)=jdw(2:0) ; } if (gt==0XA4)&S:(jt==0XA4) ) { 1(17: 8)= [1,1,1,1,1,0 1,1,1,0] ;

I(7:4)=gdw(3:0) ; I(3:0)=jdw(3:0) ; } if (gt==0XA3)&&(jt==0XA5) ) { 1(17: 8)= [1,1,1,1,1,0 1,1,1,1] ;

I(7:5)=gdw(2:0) ; I(4:0)=jdw(4:0) ; } if (gt==0XB5)&&(jt==0XB3) ) { 1(17: 8)= [1,1,1,1,1,1 0,0,0,0] ;

I(7:3)=gdw(4:0) ; I(2:0)=jdw(2:0) ; } if (gt==0XB3)&&(jt==0XB5) ) { 1(17: 8)= [1,1,1,1,1,1 0,0,0,1] ;

I(7:5)=gdw(2:0) ; I (4:0) =jdw(4:0) ; } if (gt== 0X07) &&(jt== 0X00) ) { 1(17: 7)= [1,1,1,1,1,1 0,0,1,0,0] ,^•

I(6:0)=gdw(6:0) ; } if (gt==0X04)&&(jt==0X03) ) { 1(17: 7)= [1,1,1,1,1,1 0,0,1,0,1] ;

I(6:3)=gdw(3:0) ; I(2:0)=jdw(2:0) ; }

if ( (gt==0X02)&&(jt==0X03) )

1(17: 5)=[1, 1,1 ,1,1,1,1,1,0 ,1,0,1,1] ;

I(4:3)=gdw(l:0) ; I(2:0)=jdw(2 = 0); } if ( (gt==0X14)&&(jt==0Xll) )

1(17: 5)=[1, 1,1 ,1,1,1,1,1,0 ,1,1,0,0] ;

I(4:l)=gdw(3:0) ; l(0)=jdw(0) ; if ( (gt==0X24)&&(jt==0X21) )

1(17: 5)=[1, 1,1 ,1,1,1,1,1,0 ,1,1,0,1] ;

I(4:l)=gdw(3:0) ; l(0)=jdw(0) ; if ( (gt==0X35)&&(jt==0X30) )

1(17: 5)=[1,1,1 ,1,1,1,1,1,0 ,1,1,1,0] ;

I(4:0)=gdw(4:0) ; if ( (gt==0X32)&&(jt==0X33) )

[ 1(17: 5) = [1, 1,1,1, 1,1, 1,1,0 ,1,1,1,1] ;

I(4:3)=gdw(l:0) ; I(2:0)=jdw(2 0); } if ( (gt==0X30)&&(jt==0X35) )

( 1(17: 5)=[1,1,1,1,1,1,1,1,1 ,0,0,0,0] ;

I(4:0)=jdw(4 :0); } if ( (gt== 0X43 )&&(jt== 0X42) )

[ 1(17: 5)=[1,1,1,1,1,1,1,1,1 ,0,0,0,1] ;

I (4 :2)=gdw(2:0) ; l(l:0)=jdw(l 0); } if ( (gt== 0X41) &&(jt== 0X44) )

[ 1(17: 5)=[1,1,1,1,1,1,1,1,1 ,0,0,1,0] ;

I(4)=gdw(0) ; I(3:0)=jdw(3 0); } if ( (gt==0X91)&&(jt==0X94) )

1(17: 5)=[1, 1,1 ,1,1,1,1,1,1 ,0,0,1,1] ;

I(4)=gdw(0) ; I(3:0)=jdw(3 0); } if ( (gt==0XA5)&&(jt==0XA0) )

[ 1(17: 5)=[1, 1,1,1, 1,1, 1,1,1 ,0,1,0,0] ;

1(4 :0)=gdw(4:0) ; if ( (gt==0XB5)&&(jt==0XB0) )

1(17: 5)=[1,1,1,1,1,1,1,1,1 ,0,1,0,1] ;

1(4 :0)=gdw(4:0) ; if ( (gt==0XB3) &&(jt==0XB2) )

1(17: 5)=[1,1,1,1,1,1,1,1,1 ,0,1,1,0] ;

I(4:2)=gdw(2:0) ; l(l:0)=jdw(l 0); } if ( (gt==0XB2)&&(jt==0XB3) )

1(17: 5)=[1,1,1,1,1,1,1,1,1 0,1,1,1] ;

I(4:3)=gdw(l:0) ; I(2:0)=jdw(2 0); } if ( (gt==0XB0)&&(jt==0XB5) )

1(17: 5) = [1, 1,1 ,1,1,1,1,1,1 ,1,0,0,0] ;

I(4:0)=jdw(4 0); } if ( (gt==0X04)&S:(jt==0X00) )

1(17: 4) = [1, 1,1 ,1,1,1,1,1,1 1,0,0,1,0] ;

I(3:0)=gdw(3:0) ; if ( (gt==0Xll)&&(jt==0X13) )

1(17: 4) = [1, 1,1 ,1,1,1,1,1,1 1,0,0,1,1] ;

I(3)=gdw(0) ; I(2:0)=jdw(2 0); } if ( (gt== 0X23 )&&(jt== 0X21) )

1(17: 4)=[1,1,1,1,1,1,1,1,1 1,0,1,0,0] ;

I(3:l)=gdw(2:0) ; l(0)=jdw(0) ; if ( (gt==0X41)&&(jt==0X43) )

1(17: 4) = [1, 1,1, 1,1,1, 1,1,1 1,0,1,0,1] ;

I(3)=gdw(0) ; I(2:0)=jdw(2 0); } if ( (gt== 0X91) &S:(jt== 0X93) )

1(17: 4) = [1,1, 1,1, 1,1, 1,1,1 1,0,1,1,0] ; l(3)=gdw(0); I(2:0)=jdw(2 0); } if ( (gt==0XA4)&&(jt==0XA0) )

1(17: 4) = [1, 1,1, 1,1, 1,1, 1,1, 1,0, 1,1,1] ; I(3:0)=gdw(3:0) ; if ( (gt==0XB2)&&(jt==0XB2) ) [ 1(17: 4) = [1, 1,1 ,1,1,1,1,1,1,1,1,0,0,0] ;

1(3 :2)=gdw(l:0) ; l(l:0)=jdw(l 0); } if ( (gt==0XC3)&-i(jt==0XCl) )

1(17: 4) = [1, 1,1, 1,1, 1,1, 1,1, 1,1, 0,0,1] ; 1(3 :l)=gdw(2:0) ; I (0) =jd ( 0) ; if ( (gt==0XCl)&&(jt==0XC3) ) [ 1(17: 4) = [1, 1,1, 1,1, 1,1, 1,1, 1,1, 0,1,0] ;

I(3)=gdw(0); I(2:0)=jdw(2 0); } if ( (gt== 0X03) &&(jt== 0X00) )

1(17: 3)=[1, 1,1 ,1,1,1,1,1,1 ,1,1,0,1,1,0] ; I(2:0)=gdw(2:0) ; if ( (gt==0X33)&S:(jt==0X30) )

1(17: 3)=[1, 1,1, 1,1, 1,1, 1,1, 1,1, 0,1, 1,1] ; 1(2 :0)=gdw(2:0) ; if ( (gt==0X30)&&(jt==0X33) ) r 1(17: 3)=[1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,0, 0,0] ;

I(2:0)=jdw(2 0); } if ( (gt==0X41)&&(jt==0X42) )

1(17: 3) =[1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 0,0,1] ;

I(2)=gdw(0) ; l(l:0)=jdw(l 0); } if ( (gt== 0X91) &&(jt== 0X92) ) ' 1(17: 3)=[1, 1,1 ,1,1,1,1,1,1 ,1,1,1,0,1,0] ;

I(2)=gdw(0) ,- l(l:0)=jdw(l 0); } if ( (gt==0XA3)&&(jt==0XA0) )

1(17: 3) = [1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 0,1,1],^• 1(2 :0)=gdw(2:0) ; if ( (gt==0XB3)S:&(jt==0XB0) )

1(17: 3)= [1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,0,0],^• I(2:0)=gdw(2:0) ; if ( (gt==0XB0)&&(jt==0XB3) )

1(17: 3) =[1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,0,1],^•

I(2:0)=jdw(2 0); } if ( (gt== 0X02) &&(jt== 0X00) )

1(17: 2) = [1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 0,0], l(l:0)=gdw(l:0) ; if ( (gt== 0X11) &&:(jt== 0X11) )

1(17: 2)= [1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 0,1], l(l)=gdw(0) ; l(0)=jdw(0) ; if ( (gt==0X32)&&(jt==0X30) )

1(17: 2) =[1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,0], l(l:0)=gdw(l:0) ; if ( (gt==0XB2)&&(jt==0XB0) )

1(17: 2) = [1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1], l(l:0)=gdw(l:0) ; It is to be understood that even though numerous characteristics and advantages of various embodiments of the invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this disclosure is illustrative only, and changes may be made in detail, especially in matters of structure and arrangement of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed. For example, the particular elements may vary depending on the particular application for the comrnunication system while mamtaining substantially the same functionality without departing from the scope and spirit of the present invention. In addition, although the embodiments described herein are directed to a coding system for a disc drive, it will be appreciated by those skilled in the art that the teachings of the present invention can be applied to system such as sateUite communications and cellular phones, without departing from the scope and spirit of the present invention. Also, a digital "word" can have any number of bits in alternative embodiments of the present invention.

Claims

WHAT IS CLAIMED IS:

1. A method of encoding digital information in a system, the method comprising:

(a) receiving a sequence of successive data words; and

(b) encoding the sequence of successive data words into a sequence of successive code words such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.

2. The method of claim 1 wherein each code word comprises a plurality of bits and (b) comprises interleaving at least some of the bits in each code word with at least some of the bits in another, adjacent one of the code words in the sequence of successive code words.

3. The method of claim 1 wherein one of the predetermined, non-adjacent values is zero.

4. The method of claim 3 wherein the running digital sum is constrained to the values of zero and six at the boundaries between the code words.

5. The method of claim 1 wherein each data word has 18 bits and each code word has 20 bits such that the method has a code rate of 18/20.

6. The method of claim 1 wherein (b) comprises, for each user data word: (b)(1) generating a first segment of the code word based on a corresponding one of the user data words and the running digital sum of the sequence at the boundary between that code word and a previous one of the code words in the sequence, wherein the first segment also has a running digital sum; and

(b)(2) generating a second segment of the code word based on the corresponding user data word, the running digital sum of the sequence at the boundary between the code word and the previous code word in the sequence, and the running digital sum of the first segment.

7. The method of claim 1 wherein (b) comprises, for each user data word: (b)(1) separating the user data word into a first fragment, a second fragment and a third fragment; (b)(2) mapping the second fragment to a first segment of a corresponding one of the code words; (b)(3) mapping the third fragment to a second segment of the corresponding code word; and (b)(4) combining the first segment and the second segment to form the corresponding code word.

8. The method of claim 7 wherein (b)(1) comprises separating the user data word into the first, second and third fragments based on a pattern formed by the first fragment.

9. An encoder for encoding digital information, the encoder comprising: an input for receiving a sequence of successive data words; and encoding means for encoding the sequence of successive data words into a sequence of successive code words such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.

10. The encoder of claim 9 wherein each code word comprises a plurality of bits and the encoding means comprises means for interleaving at least some of the bits in each code word with at least some of the bits in another, adjacent one of the code words in the sequence of successive code words.

11. The encoder of claim 9 wherein one of the predetermined, non-adjacent values is zero.

12. The encoder of claim 11 wherein the running digital sum is constrained to the values of zero and six at the boundaries between the code words.

13. The encoder of claim 9 wherein each data word has 18 bits and each code word has 20 bits such that the method has a code rate of 18/20.

14. The encoder of claim 9 wherein the encoding means comprises, for each user data word: means for generating a first segment of the code word based on a corresponding one of the user data words and the running digital sum of the sequence at the boundary between that code word and a previous one of the code words in the sequence, wherein the first segment also has a running digital sum; and means for generating a second segment of the code word based on the corresponding user data word, the running digital sum of the sequence at the boundary between the code word and the previous code word in the sequence, and the running digital sum of the first segment.

15. The encoder of claim 9 wherein the encoding means comprises, for each user data word: means for separating the user data word into a first fragment, a second fragment and a third fragment, mapping the second fragment to a first segment of a corresponding one of the code words, mapping the third fragment to a second segment of the corresponding code word, and combining the first segment and the second segment to form the corresponding code word.

16. The encoder of claim 15 wherein the encoding means further comprises means for separating the user data word into the first, second and third fragments based on a pattern formed by the first fragment.

17. A method of encoding digital information in a system, the method comprising:

(a) receiving a sequence of successive data words; (b) encoding the sequence of successive data words into a sequence of successive code words such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained at boundaries between the code words; and

(c) interleaving at least some bits in each code word with at least some bits in another, adjacent one of the code words in the sequence of successive code words.

18. The method of claim 17 wherein the running digital sum of the sequence of successive code words is constrained at boundaries between the code words to zero and another predetermined value that is non-adjacent to zero in a series of otherwise possible values for the running digital sum.

19. The method of claim 18 wherein the running digital sum is constrained to the values of zero and six at the boundaries between the code words.

20. The method of claim 17 wherein each data word has 18 bits and each code word has 20 bits such that the method has a code rate of 18/20.

21. The method of claim 17 wherein (b) comprises, for each user data word: (b)(1) generating a first segment of the code word based on a corresponding one of the user data words and the running digital sum of the sequence at the boundary between that code word and a previous one of the code words in the sequence, wherein the first segment also has a running digital sum; and (b)(2) generating a second segment of the code word based on the corresponding user data word, the running digital sum of the sequence at the boundary between the code word and the previous code word in the sequence, and the running digital sum of the first segment.

22. The method of claim 17 wherein (b) comprises, for each user data word: (b)(1) separating the user data word into a first fragment, a second fragment and a third fragment; (b)(2) mapping the second fragment to a first segment of a corresponding one of the code words; (b)(3) mapping the third fragment to a second segment of the corresponding code word; and (b)(4) combining the first segment and the second segment to form the corresponding code word.

23. The method of claim 22 wherein (b)(1) comprises separating the user data word into the first, second and third fragments based on a pattern formed by the first fragment.

24. A method of decoding digital information in a system, the method comprising:

(a) receiving a sequence of successive code words; and

(b) decoding the sequence of successive code words into a sequence of successive data words according to a code in which a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.