WO2005027192A3 - Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions - Google Patents

Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions Download PDF

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Publication number
WO2005027192A3
WO2005027192A3 PCT/US2004/028163 US2004028163W WO2005027192A3 WO 2005027192 A3 WO2005027192 A3 WO 2005027192A3 US 2004028163 W US2004028163 W US 2004028163W WO 2005027192 A3 WO2005027192 A3 WO 2005027192A3
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Prior art keywords
source
drain regions
lattice
nfet
cmos transistors
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PCT/US2004/028163
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French (fr)
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WO2005027192A2 (en
Inventor
Omer Dokumaci
Huajie Chen
Dureseti Chidambarrao
Haining S Yang
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Ibm
Omer Dokumaci
Huajie Chen
Dureseti Chidambarrao
Haining S Yang
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Application filed by Ibm, Omer Dokumaci, Huajie Chen, Dureseti Chidambarrao, Haining S Yang filed Critical Ibm
Priority to EP04782603A priority Critical patent/EP1668672A4/en
Priority to JP2006526140A priority patent/JP4808622B2/en
Priority to CN2004800259557A priority patent/CN1985375B/en
Publication of WO2005027192A2 publication Critical patent/WO2005027192A2/en
Publication of WO2005027192A3 publication Critical patent/WO2005027192A3/en

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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Abstract

A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.
PCT/US2004/028163 2003-09-10 2004-08-30 Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions WO2005027192A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04782603A EP1668672A4 (en) 2003-09-10 2004-08-30 Structure and method of making strained channel cmos transistors having lattice-mismatched epitaxial extension and source and drain regions
JP2006526140A JP4808622B2 (en) 2003-09-10 2004-08-30 Strain channel CMOS transistor structure having lattice-mismatched epitaxial extension region and source and drain regions and method of manufacturing the same
CN2004800259557A CN1985375B (en) 2003-09-10 2004-08-30 Structure and method of making strained channel CMOS transistors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/605,134 US6906360B2 (en) 2003-09-10 2003-09-10 Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US10/605,134 2003-09-10

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WO2005027192A2 WO2005027192A2 (en) 2005-03-24
WO2005027192A3 true WO2005027192A3 (en) 2006-12-21

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US (2) US6906360B2 (en)
EP (1) EP1668672A4 (en)
JP (1) JP4808622B2 (en)
KR (1) KR100810012B1 (en)
CN (1) CN1985375B (en)
TW (1) TWI318435B (en)
WO (1) WO2005027192A2 (en)

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498475B1 (en) * 2003-01-07 2005-07-01 삼성전자주식회사 Mosfet structure and method of fabricating the same
JP2004311903A (en) * 2003-04-10 2004-11-04 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method
US6949443B2 (en) * 2003-10-10 2005-09-27 Taiwan Semiconductor Manufacturing Company High performance semiconductor devices fabricated with strain-induced processes and methods for making same
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
JP4866609B2 (en) * 2003-10-23 2012-02-01 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
DE10351008B4 (en) * 2003-10-31 2008-07-10 Advanced Micro Devices, Inc., Sunnyvale A method of fabricating transistors having elevated drain and source regions of different height and a semiconductor device
US7064027B2 (en) * 2003-11-13 2006-06-20 International Business Machines Corporation Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
US7018891B2 (en) * 2003-12-16 2006-03-28 International Business Machines Corporation Ultra-thin Si channel CMOS with improved series resistance
US7202145B2 (en) * 2004-06-03 2007-04-10 Taiwan Semiconductor Manufacturing Company Strained Si formed by anneal
US7244958B2 (en) * 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
US7279430B2 (en) * 2004-08-17 2007-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Process for fabricating a strained channel MOSFET device
US7161199B2 (en) * 2004-08-24 2007-01-09 Freescale Semiconductor, Inc. Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof
JP4116990B2 (en) * 2004-09-28 2008-07-09 富士通株式会社 Field effect transistor and manufacturing method thereof
US7135724B2 (en) 2004-09-29 2006-11-14 International Business Machines Corporation Structure and method for making strained channel field effect transistor using sacrificial spacer
JP4945900B2 (en) * 2005-01-06 2012-06-06 ソニー株式会社 Insulated gate field effect transistor and manufacturing method thereof
US7176481B2 (en) * 2005-01-12 2007-02-13 International Business Machines Corporation In situ doped embedded sige extension and source/drain for enhanced PFET performance
US7696537B2 (en) * 2005-04-18 2010-04-13 Toshiba America Electronic Components, Inc. Step-embedded SiGe structure for PFET mobility enhancement
US7446350B2 (en) * 2005-05-10 2008-11-04 International Business Machine Corporation Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer
DE102005030583B4 (en) * 2005-06-30 2010-09-30 Advanced Micro Devices, Inc., Sunnyvale Method for producing contact insulation layers and silicide regions having different properties of a semiconductor device and semiconductor device
EP1744351A3 (en) * 2005-07-11 2008-11-26 Interuniversitair Microelektronica Centrum ( Imec) Method for forming a fully silicided gate MOSFET and devices obtained thereof
US7569888B2 (en) * 2005-08-10 2009-08-04 Toshiba America Electronic Components, Inc. Semiconductor device with close stress liner film and method of manufacturing the same
DE102005052054B4 (en) * 2005-10-31 2010-08-19 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device with shaped channel region transistors and method of making the same
US20070099360A1 (en) * 2005-11-03 2007-05-03 International Business Machines Corporation Integrated circuits having strained channel field effect transistors and methods of making
US7566609B2 (en) * 2005-11-29 2009-07-28 International Business Machines Corporation Method of manufacturing a semiconductor structure
CN100411146C (en) * 2005-12-06 2008-08-13 联华电子股份有限公司 Method for fabricating strained-silicon CMOS transistors
US7718500B2 (en) * 2005-12-16 2010-05-18 Chartered Semiconductor Manufacturing, Ltd Formation of raised source/drain structures in NFET with embedded SiGe in PFET
US7279758B1 (en) * 2006-05-24 2007-10-09 International Business Machines Corporation N-channel MOSFETs comprising dual stressors, and methods for forming the same
US8211761B2 (en) * 2006-08-16 2012-07-03 Globalfoundries Singapore Pte. Ltd. Semiconductor system using germanium condensation
US7632729B2 (en) * 2006-09-27 2009-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method for semiconductor device performance enhancement
US7550351B2 (en) * 2006-10-05 2009-06-23 International Business Machines Corporation Structure and method for creation of a transistor
JP5040286B2 (en) 2006-12-13 2012-10-03 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method of semiconductor device
WO2008102448A1 (en) * 2007-02-22 2008-08-28 Fujitsu Microelectronics Limited Semiconductor device, and semiconductor device manufacturing method
WO2008102451A1 (en) * 2007-02-22 2008-08-28 Fujitsu Microelectronics Limited Semiconductor device and process for producing the same
JP4994139B2 (en) 2007-07-18 2012-08-08 パナソニック株式会社 Semiconductor device and manufacturing method thereof
US7659583B2 (en) * 2007-08-15 2010-02-09 International Business Machines Corporation Ultrathin SOI CMOS devices employing differential STI liners
US7572689B2 (en) * 2007-11-09 2009-08-11 International Business Machines Corporation Method and structure for reducing induced mechanical stresses
JP2009170523A (en) * 2008-01-11 2009-07-30 Rohm Co Ltd Semiconductor device and method for manufacturing the same
US7678634B2 (en) * 2008-01-28 2010-03-16 International Business Machines Corporation Local stress engineering for CMOS devices
US7892932B2 (en) * 2008-03-25 2011-02-22 International Business Machines Corporation Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
US20100109044A1 (en) * 2008-10-30 2010-05-06 Tekleab Daniel G Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer
KR101561059B1 (en) * 2008-11-20 2015-10-16 삼성전자주식회사 Semiconductor device and method of forming the same
DE102008064671B4 (en) * 2008-11-28 2011-03-10 Advanced Micro Devices, Inc., Sunnyvale A method of fabricating a semiconductor device having a gate structure and increasing the integrity of a high-k gate stack by protecting a coating on the gate bottom during exposure of the gate top
KR101606930B1 (en) * 2008-12-30 2016-03-28 주식회사 동부하이텍 Semiconductor and Method for Manufacturing the same
US7935593B2 (en) * 2009-02-05 2011-05-03 Samsung Electronics Co., Ltd. Stress optimization in dual embedded epitaxially grown semiconductor processing
DE102009015715B4 (en) * 2009-03-31 2011-03-17 Globalfoundries Dresden Module One Llc & Co. Kg A method of fabricating a transistor device while maintaining the integrity of a high-k gate stack through an offset spacer used to determine a spacing of a strain-inducing semiconductor alloy and transistor device
US8436404B2 (en) 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
US8198194B2 (en) 2010-03-23 2012-06-12 Samsung Electronics Co., Ltd. Methods of forming p-channel field effect transistors having SiGe source/drain regions
US8546228B2 (en) 2010-06-16 2013-10-01 International Business Machines Corporation Strained thin body CMOS device having vertically raised source/drain stressors with single spacer
JP5856827B2 (en) * 2010-12-09 2016-02-10 株式会社半導体エネルギー研究所 Semiconductor device
US9001564B2 (en) 2011-06-29 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method for driving the same
US9087741B2 (en) 2011-07-11 2015-07-21 International Business Machines Corporation CMOS with dual raised source and drain for NMOS and PMOS
US9076817B2 (en) 2011-08-04 2015-07-07 International Business Machines Corporation Epitaxial extension CMOS transistor
US8828831B2 (en) * 2012-01-23 2014-09-09 International Business Machines Corporation Epitaxial replacement of a raised source/drain
US8912608B2 (en) * 2012-08-17 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabrication method thereof
US10438856B2 (en) * 2013-04-03 2019-10-08 Stmicroelectronics, Inc. Methods and devices for enhancing mobility of charge carriers
KR102089682B1 (en) 2013-07-15 2020-03-16 삼성전자 주식회사 Semiconductor device and method for fabricating the same
US9614053B2 (en) * 2013-12-05 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Spacers with rectangular profile and methods of forming the same
US9831341B2 (en) 2014-06-16 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for integrated circuit
US10026837B2 (en) * 2015-09-03 2018-07-17 Texas Instruments Incorporated Embedded SiGe process for multi-threshold PMOS transistors
KR102532497B1 (en) 2016-09-19 2023-05-17 삼성전자주식회사 Semiconductor device and method for manufacturing the same
CN109300789B (en) * 2017-07-25 2021-07-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
JP2021192396A (en) * 2018-09-14 2021-12-16 キオクシア株式会社 Integrated circuit device and manufacturing method for integrated circuit device
US10756184B2 (en) * 2018-11-05 2020-08-25 Globalfoundries Inc. Faceted epitaxial source/drain regions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268324A (en) * 1992-05-27 1993-12-07 International Business Machines Corporation Modified silicon CMOS process having selectively deposited Si/SiGe FETS
US5583059A (en) * 1994-06-01 1996-12-10 International Business Machines Corporation Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI
US6358806B1 (en) * 2001-06-29 2002-03-19 Lsi Logic Corporation Silicon carbide CMOS channel
US20040175872A1 (en) * 2003-03-07 2004-09-09 Taiwan Semiconductor Manufacturing Company Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US6159815A (en) * 1996-09-27 2000-12-12 Siemens Aktiengesellschaft Method of producing a MOS transistor
EP0838858B1 (en) * 1996-09-27 2002-05-15 Infineon Technologies AG CMOS integrated circuit and method of manufacturing the same
JPH10270685A (en) * 1997-03-27 1998-10-09 Sony Corp Field-effect transistor and manufacture thereof, semiconductor device and manufacture thereof and logic circuit containing semiconductor device thereof and semiconductor substrate
US5846857A (en) * 1997-09-05 1998-12-08 Advanced Micro Devices, Inc. CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
JPH11163343A (en) * 1997-11-28 1999-06-18 Nec Corp Semiconductor device and its manufacture
US5989965A (en) * 1998-02-13 1999-11-23 Sharp Laboratories Of America, Inc. Nitride overhang structures for the silicidation of transistor electrodes with shallow junction
JP2000124327A (en) * 1998-10-14 2000-04-28 Toshiba Corp Semiconductor device and manufacture thereof
JP2000223703A (en) * 1999-01-29 2000-08-11 Toshiba Corp Semiconductor device and its manufacture
US7391087B2 (en) * 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
JP2002043567A (en) * 2000-07-27 2002-02-08 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
JP5000057B2 (en) * 2001-07-17 2012-08-15 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP2003188274A (en) * 2001-12-19 2003-07-04 Toshiba Corp Semiconductor device and its manufacturing method
FR2834575B1 (en) * 2002-01-09 2004-07-09 St Microelectronics Sa METHOD FOR MODELING AND PRODUCING AN INTEGRATED CIRCUIT COMPRISING AT LEAST ONE ISOLATED GRID FIELD EFFECT TRANSISTOR, AND CORRESPONDING INTEGRATED CIRCUIT
US20030166323A1 (en) * 2002-03-01 2003-09-04 Infineon Technologies North America Corp. Raised extension structure for high performance cmos
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268324A (en) * 1992-05-27 1993-12-07 International Business Machines Corporation Modified silicon CMOS process having selectively deposited Si/SiGe FETS
US5583059A (en) * 1994-06-01 1996-12-10 International Business Machines Corporation Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI
US6358806B1 (en) * 2001-06-29 2002-03-19 Lsi Logic Corporation Silicon carbide CMOS channel
US20040175872A1 (en) * 2003-03-07 2004-09-09 Taiwan Semiconductor Manufacturing Company Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1668672A4 *

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