WO2005029753A3 - Method and apparatus for efficient preamble detection in digital data receivers - Google Patents

Method and apparatus for efficient preamble detection in digital data receivers Download PDF

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Publication number
WO2005029753A3
WO2005029753A3 PCT/US2004/030679 US2004030679W WO2005029753A3 WO 2005029753 A3 WO2005029753 A3 WO 2005029753A3 US 2004030679 W US2004030679 W US 2004030679W WO 2005029753 A3 WO2005029753 A3 WO 2005029753A3
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WO
WIPO (PCT)
Prior art keywords
preamble
preamble detection
digital data
data receivers
receivers
Prior art date
Application number
PCT/US2004/030679
Other languages
French (fr)
Other versions
WO2005029753A2 (en
Inventor
Mark J Foster
Original Assignee
Agile Tv Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agile Tv Corp filed Critical Agile Tv Corp
Publication of WO2005029753A2 publication Critical patent/WO2005029753A2/en
Publication of WO2005029753A3 publication Critical patent/WO2005029753A3/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/227Demodulator circuits; Receiver circuits using coherent demodulation

Abstract

A method and apparatus is disclosed that significantly reduces preamble detection complexity, while maintaining superior signaling performance. This simplification can lead to higher data throughput within processing-limited receivers, and/or a greater degree of parallelism in multiple channel receivers. The preamble detector receives the digitized input I and Q samples (1) represent the reconstructed base band with preamble. The preamble detection proceeds via a carrier derotation block (2), Sign blocks (3a and 3b), a differential decoder (5), a multiplexer (6), a preamble shift register (7), and other logic circuit block to found the preamble.
PCT/US2004/030679 2003-09-18 2004-09-17 Method and apparatus for efficient preamble detection in digital data receivers WO2005029753A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US50417103P 2003-09-18 2003-09-18
US60/504,171 2003-09-18
US10/944,503 US7428273B2 (en) 2003-09-18 2004-09-16 Method and apparatus for efficient preamble detection in digital data receivers
US10/944,503 2004-09-16

Publications (2)

Publication Number Publication Date
WO2005029753A2 WO2005029753A2 (en) 2005-03-31
WO2005029753A3 true WO2005029753A3 (en) 2006-05-04

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PCT/US2004/030679 WO2005029753A2 (en) 2003-09-18 2004-09-17 Method and apparatus for efficient preamble detection in digital data receivers

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US (1) US7428273B2 (en)
WO (1) WO2005029753A2 (en)

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US20050063493A1 (en) 2005-03-24
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