WO2005031865A1 - Electronic package having a folded flexible substrate and method of manufacturing the same - Google Patents

Electronic package having a folded flexible substrate and method of manufacturing the same Download PDF

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Publication number
WO2005031865A1
WO2005031865A1 PCT/US2004/030993 US2004030993W WO2005031865A1 WO 2005031865 A1 WO2005031865 A1 WO 2005031865A1 US 2004030993 W US2004030993 W US 2004030993W WO 2005031865 A1 WO2005031865 A1 WO 2005031865A1
Authority
WO
WIPO (PCT)
Prior art keywords
fold
electronic package
mold cap
microelectronic die
controlling member
Prior art date
Application number
PCT/US2004/030993
Other languages
French (fr)
Inventor
José SALTA, III
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to EP04784735A priority Critical patent/EP1665379B1/en
Priority to JP2006527142A priority patent/JP4503604B2/en
Priority to CN2004800270058A priority patent/CN1853272B/en
Priority to AT04784735T priority patent/ATE556434T1/en
Publication of WO2005031865A1 publication Critical patent/WO2005031865A1/en
Priority to HK06106657.5A priority patent/HK1084506A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/4809—Loop shape
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/06579—TAB carriers; beam leads
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • This invention relates to an electronic package of the type having a
  • microelectronic die and to a method of constructing an electronic package.
  • Integrated circuits are usually manufactured in and on semiconductor
  • microelectronic dies each die carrying a respective integrated circuit.
  • Such a die
  • the package substrate is coupled to a package substrate for purposes of structural integrity.
  • conductors in the form of traces thereon, metal lines therein, and/ or vias
  • Two dies can, for example, be mounted to a
  • dies are above one another.
  • a package substrate of the aforementioned kind is usually uniformly flexible across its width. When one portion of the package substrate is folded
  • a fold region may be created at an
  • Bending at arbitrary locations may cause inconsistencies in bending from one
  • Figures 4A-D illustrate one manner of forming an existing electronic
  • a cover piece 316 is
  • microelectronic dies 310 located over the microelectronic dies 310, the microelectronic dies 312, and the
  • the cover piece 316 has a protrusion 318 contacting a fold
  • mold caps 324 are subsequently injection-
  • microelectronic dies 310 microelectronic dies 312, and flexible substrate 314.
  • mold caps 324 form square edges 326 facing one another, with the fold
  • Figure 1A is a cross-sectional side view a portion of a flexible substrate
  • Figure IB is a view similar to Figure 1, after the cover pieces are placed on
  • Figure IC is a view similar to Figure IB, after the cover piece is removed;
  • Figure ID is a view similar to Figure IC, after the shape-defining piece is
  • Figure IE is a view similar to Figure ID, after the flexible substrate is
  • Figure IF is a view similar to Figure IE, showing the entire electronic
  • Figure 2 is a perspective view of the electronic assembly with the flexible substrate shown in exploded form and before being folded;
  • Figure 3A is a cross-sectional side view of components of an electronic
  • Figure 3B is a view similar to Figure 3A, after the cover piece is placed on
  • Figure 3C is a view similar to Figure 3B, after the cover and shape-
  • Figure 3D is a view similar to Figure 3C, illustrating the entire electronic
  • Figure 4A is a cross-sectional side view of components of an electronic
  • Figure 4B is a view similar to Figure 4A, after two mold caps are
  • Figure 4C is a view similar to Figure 4B, after the cover piece is removed;
  • Figure 4D is a view similar to Figure 4C, after a flexible substrate of the
  • microelectronic die is mounted to a flexible substrate.
  • a mold cap is injection-
  • the mold cap has a curved convex edge surface around
  • edge surface to reduce defects, ensure consistent formfactor from one
  • FIG. 1A of the accompanying drawings illustrates components of a
  • partially fabricated electronic package including a flexible substrate 10 and a
  • microelectronic die 12 together with molding components including a cover piece
  • the flexible substrate 10 has first and second portions 18 and 20 and a
  • substrate 10 includes a core of flexible dielectric material and conductors in the
  • microelectronic die 12 is mounted to the first portion 18 of the flexible
  • the microelectronic die 12 has an integrated circuit formed therein,
  • the microelectronic die 12 is connected to the terminals of
  • each wire bonding wire is the flexible substrate 10 by way of wire bonding wires 24, each wire bonding wire
  • the shape-defining piece 16 is placed on the fold portion 22, toward the
  • the shape-defining piece 16 has a height 25 and a
  • the shape-defining piece 16 further has a curved concave surface 28
  • shape-defining piece 16 has an upper left edge 32 with a height 34.
  • concave surface 28 extends all the way to a lower surface 36 of the shape-defining
  • the cover piece 14 has an overall height 42 as measured from an upper
  • a first surface 48 is machined in the
  • cover piece 14 is illustrated with the first surface 48 above the
  • the first surface 48 is above the lower
  • a second surface 52 is machined into the cover piece 14 and is illustrated
  • the second surface 52 has a width 54
  • the second surface 52 is machined to a height 56 which is approximately the same
  • differential height 60 is more than the height 34 of the upper left edge 32
  • An injection port 62 is formed into the cover piece 14.
  • the injection port 62 is formed from the upper surface 44 to the first
  • Figure IB illustrates the components of Figure 1 A after the cover piece 14
  • cap 64 is injected and formed in the remaining space between the flexible
  • substrate 10 microelectronic die 12, cover piece 14, and shape-defining piece 16.
  • differential height 60 is more than the height 34.
  • the first surface 48 is spaced
  • a liquid resin is injected through the injection port 62.
  • the resin comes
  • the resin is
  • a recess 66 having an upper surface 68 and side surfaces 70 is formed in the mold cap 64 because the first surface (48 in Figure 1A) is lower than the upper left edge
  • an adhesive layer 72 is attached to the mold cap 64.
  • the mold cap 64 has a curved convex surface 74 at an edge thereof.
  • convex surface 74 has the same shape as the curved concave surface of the shape-
  • the adhesive layer 72 is formed within
  • portion 20 is positioned over and attached to the adhesive layer 72.
  • portion of the flexible substrate 10 is thus bent, whereas other portions remain
  • Controlled folding also results in a consistent formfactor from one electronic
  • Figure IF illustrates the entire electronic package 82. Wire bonding wires
  • Figure 2 illustrates further components of the electronic package 82 before
  • the electronic package 82 in addition to the flexible substrate 10
  • microelectronic die 12 further includes a plurality of conductive
  • interconnection members 84 may further include a second microelectronic
  • a core of the flexible substrate 10 is a flexible layer 88 made of polyimide,
  • First and second thin metal layers 90 and 92 are formed on upper
  • thin metal layer 90 is then patterned so that areas are removed and other areas,
  • a first solder mask 98 is formed over the remaining portions of the first
  • a relatively resilient ground metal layer 102 is then plated on a surface of
  • a second solder mask 104 is subsequently formed
  • the second microelectronic die 86 can be connected by way of wire
  • the conductive interconnection members 84 are conductive interconnection members 84 to some of the contacts 94.
  • the microelectronic dies 12 and 86 can be interconnected to one another and to the conductive interconnection members 84. Signals can thus be
  • microelectronic dies 12 and 86 are in
  • ground metal layer 102 provides the otherwise
  • ground metal layer 102 is included.
  • Figures 3A-D illustrate the manufacture of an electronic package having
  • microelectronic dies 220 and 222 to which the
  • microelectronic dies 212 and 286 are respectively mounted. Wire bonding wires
  • the first and second components 216B are located on a fold portion 260 of the flexible substrate 210.
  • the first and second components 216B are located on a fold portion 260 of the flexible substrate 210.
  • second microelectronic dies 212 and 286 are located on first and second portions
  • a cover piece 214 has a
  • protrusion 250 which is approximately as high as the shape-defining pieces 216A and 216B, and has a width that is approximately equal to the space in between the
  • shape-defining pieces 216A and 216B are shape-defining pieces 216A and 216B.
  • the protrusion 250 is inserted between the shape-defining pieces 216A and 216B,
  • the curved convex surfaces 274 each form
  • an adhesive layer 230 is applied to one of the
  • Folding of the flexible substrate 210 is controlled because the fold portion 260

Abstract

An electronic package is provided and its method of construction. A microelectronic die is mounted to a flexible substrate. A mold cap is injection­molded over the die. The mold cap has a curved convex edge surface around which the flexible substrate wraps. Folding of the flexible substrate is controlled by the edge surface to reduce defects, ensure consistent form factor from one package to the next, and allow for the inclusion of a relatively resilient ground plane.

Description

ELECTRONIC PACKAGE HAVING A FOLDED FLEXIBLE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
BACKGROUND OF THE INVENTION
1). Field of the Invention
[0001] This invention relates to an electronic package of the type having a
microelectronic die and to a method of constructing an electronic package.
2). Discussion of Related Art
[0002] Integrated circuits are usually manufactured in and on semiconductor
wafer substrates that are subsequently "singulated" or "diced" into individual
microelectronic dies, each die carrying a respective integrated circuit. Such a die
may be extremely thin, often less than 100 microns, and is subsequently mounted
to a package substrate for purposes of structural integrity. The package substrate
also has conductors in the form of traces thereon, metal lines therein, and/ or vias
therein to provide electric intercormection to other devices, often other integrated
circuits or other dies mounted to the same package substrate.
[0003] In order to save space in x and y, it is often required to stack more than
one die on top of one another in a z-direction, with integrated circuits of the dies
interconnected with one another. Two dies can, for example, be mounted to a
flexible substrate, and the flexible substrate be folded into positions such that the
dies are above one another.
[0004] A package substrate of the aforementioned kind is usually uniformly flexible across its width. When one portion of the package substrate is folded
over another portion of the package substrate, a fold region may be created at an
undesired, even arbitrary area of the package substrate. Folding of the substrate
at undesired areas may cause damage to certain components of the substrate.
Bending at arbitrary locations may cause inconsistencies in bending from one
assembly to the next, which may result in incorrect downstream packaging.
Uncontrolled folding may also result in an undesired formf actor of the final
electronic package.
[0005] Figures 4A-D illustrate one manner of forming an existing electronic
package. In Figure 4A, two microelectronic dies 310 are mounted via two other
microelectronic dies 312 to a flexible package substrate 314. A cover piece 316 is
located over the microelectronic dies 310, the microelectronic dies 312, and the
flexible substrate 314. The cover piece 316 has a protrusion 318 contacting a fold
portion 320 of the flexible substrate 314.
[0006] As illustrated in Figure 4B, mold caps 324 are subsequently injection-
molded within remaining spaces defined within the confines of the cover piece
316, microelectronic dies 310, microelectronic dies 312, and flexible substrate 314.
When the cover piece 316 is removed, as illustrated in Figure 4C, it can be seen
that the mold caps 324 form square edges 326 facing one another, with the fold
portion 320 between the edges 326.
[0007] As illustrated in Figure 4D, the fold portion 320 is subsequently folded to
place a portion of the flexible substrate 314 carrying one of the microelectronic
dies 310 over a portion of the flexible substrate carrying the other microelectronic die 310. Folding of the fold portion 320 is not controlled, and is not consistent
from one package to the next.
[0008]
[0009] BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The invention is described by way of examples with reference to the
accompanying drawings, wherein:
[0011] Figure 1A is a cross-sectional side view a portion of a flexible substrate
and a microelectronic die of an electronic package, together with a shape-defining
piece and a cover piece used to construct the electronic package;
[0012] Figure IB is a view similar to Figure 1, after the cover pieces are placed on
the flexible substrate, and a mold cap of the electronic package is injection-molded
within remaining spaces defined by other components of the electronic package,
the shape-defining piece, and the cover piece;
[0013] Figure IC is a view similar to Figure IB, after the cover piece is removed;
[0014] Figure ID is a view similar to Figure IC, after the shape-defining piece is
removed and an adhesive is applied within a recess of the mold cap;
[0015] Figure IE is a view similar to Figure ID, after the flexible substrate is
folded around the mold cap, with a fold portion of the flexible substrate wrapping
around a curved convex surface of the mold cap;
[0016] Figure IF is a view similar to Figure IE, showing the entire electronic
assembly;
[0017] Figure 2 is a perspective view of the electronic assembly with the flexible substrate shown in exploded form and before being folded;
[0018] Figure 3A is a cross-sectional side view of components of an electronic
package, together with two shape-defining pieces and a cover piece used to
construct the electronic package, according to another embodiment of the
invention;
[0019] Figure 3B is a view similar to Figure 3A, after the cover piece is placed on
a flexible substrate of the electronic package, and two mold caps are injection-
molded, each over a respective microelectronic die of the electronic package;
[0020] Figure 3C is a view similar to Figure 3B, after the cover and shape-
defining pieces are removed;
[0021] Figure 3D is a view similar to Figure 3C, illustrating the entire electronic
package after the flexible substrate is folded and a fold portion thereof wraps
around curved convex surfaces of both mold caps;
[0022] Figure 4A is a cross-sectional side view of components of an electronic
package with a mold cap thereon, according to the prior art;
[0023] Figure 4B is a view similar to Figure 4A, after two mold caps are
injection-molded over microelectronic dies of the electronic package;
[0024] Figure 4C is a view similar to Figure 4B, after the cover piece is removed;
and
[0025] Figure 4D is a view similar to Figure 4C, after a flexible substrate of the
electronic package is folded. DETAILED DESCRIPTION OF THE INVENTION
[0026] An electronic package is provided and its method of construction. A
microelectronic die is mounted to a flexible substrate. A mold cap is injection-
molded over the die. The mold cap has a curved convex edge surface around
which the flexible substrate wraps. Folding of the flexible substrate is controlled
by the edge surface to reduce defects, ensure consistent formfactor from one
package to the next, and allow for the inclusion of a relatively resilient ground
plane.
[0027] Figure 1A of the accompanying drawings illustrates components of a
partially fabricated electronic package, including a flexible substrate 10 and a
microelectronic die 12, together with molding components including a cover piece
14 and a shape-defining piece 16.
[0028] The flexible substrate 10 has first and second portions 18 and 20 and a
fold portion 22 between the first and second portions 18 and 20. The flexible
substrate 10 includes a core of flexible dielectric material and conductors in the
form of metal planes, metal lines, and vias formed in and on the flexible core.
[0029] The microelectronic die 12 is mounted to the first portion 18 of the flexible
substrate 10. The microelectronic die 12 has an integrated circuit formed therein,
and is electrically connected to terminals on the flexible substrate 10. In the
present embodiment, the microelectronic die 12 is connected to the terminals of
the flexible substrate 10 by way of wire bonding wires 24, each wire bonding wire
24 having one end connected to a contact on an upper surface of the microelectronic die 12 and an opposing end connected to a terminal on the flexible
substrate 10.
[0030] The shape-defining piece 16 is placed on the fold portion 22, toward the
left of the fold portion 22. The shape-defining piece 16 has a height 25 and a
width 26. The shape-defining piece 16 further has a curved concave surface 28
facing left toward the microelectronic die 12. The curved concave surface 28 ends
slightly below an upper surface 30 of the shape-defining piece 16, so that the
shape-defining piece 16 has an upper left edge 32 with a height 34. The curved
concave surface 28 extends all the way to a lower surface 36 of the shape-defining
piece 16, so that the curved concave surface 28 and the lower surface 36 meet at a
relatively sharp edge 38 on the flexible substrate 10.
[0031] The cover piece 14 has an overall height 42 as measured from an upper
surface 44 to a lower surface 46 thereof. A first surface 48 is machined in the
cover piece 14. The cover piece 14 is illustrated with the first surface 48 above the
first portion 18 of the flexible substrate 10. The first surface 48 is above the lower
surface 46 by a height 50.
[0032] A second surface 52 is machined into the cover piece 14 and is illustrated
directly above the shape-defining piece 16. The second surface 52 has a width 54
which is approximately the same as the width 26 of the shape-defining piece 16.
The second surface 52 is machined to a height 56 which is approximately the same
as the height 25 of the shape-defining piece 16.
[0033] Because the second surface 52 is machined more deeply than the first
surface 48, there is a differential height 60 between the height 56 and the height 50. The differential height 60 is more than the height 34 of the upper left edge 32
of the shape-defining piece 16.
[0034] An injection port 62 is formed into the cover piece 14. In the present
example, the injection port 62 is formed from the upper surface 44 to the first
surface 48 of the cover piece 14.
[0035] Figure IB illustrates the components of Figure 1 A after the cover piece 14
is placed on the flexible substrate 10 and the shape-defining piece 16, and a mold
cap 64 is injected and formed in the remaining space between the flexible
substrate 10, microelectronic die 12, cover piece 14, and shape-defining piece 16.
When comparing Figures 1A and IB, it can be seen that the portion of the cover
piece 14 having the second surface 52 fits over the shape-defining piece 16
because the width 54 of the second surface 52 is approximately the same as the
width 26 of the shape-defining piece 16. The first surface 48 of the cover piece 14
is slightly below the upper left edge 32 of the shape-defining piece 16 because the
differential height 60 is more than the height 34. The first surface 48 is spaced
from an upper surface of the microelectronic die 12.
[0036] A liquid resin is injected through the injection port 62. The resin comes
into contact and fills a space defined by the microelectronic die 12, areas of the
first portion 18 not covered by the microelectronic die 12, the curved concave
surface 28 of the shape-defining piece 16, and the first surface 48. The resin is
then cured so that it solidifies.
[0037] As illustrated in Figure IC, the cover piece 14 is subsequently removed.
A recess 66 having an upper surface 68 and side surfaces 70 is formed in the mold cap 64 because the first surface (48 in Figure 1A) is lower than the upper left edge
(32 in Figure 1 A).
[0038] As illustrated in Figure ID, the shape-defining piece (16 of Figure IC) is
subsequently removed, and an adhesive layer 72 is attached to the mold cap 64.
The mold cap 64 has a curved convex surface 74 at an edge thereof. The curved
convex surface 74 has the same shape as the curved concave surface of the shape-
defining piece (28 and 16 in Figure 1A). The adhesive layer 72 is formed within
the recess (66 in Figure IC), so that an upper surface 76 thereof is substantially at
the same height as a terminating edge of the curved convex surface 74.
[0039] Referring to Figure IE, the flexible substrate 10 is subsequently folded in
a direction 80 around the mold cap 64. An inner surface of the fold portion 22
wraps around the curved convex surface 74 of the mold cap 64. The second
portion 20 is positioned over and attached to the adhesive layer 72. A desired
portion of the flexible substrate 10 is thus bent, whereas other portions remain
substantially flat. By preventing folding in undesired areas, damage to certain
components of the flexible substrate 10 can be prevented. Furthermore, bending
at predefined locations results in consistencies in bending from one electronic
package to the next, which leads to desired and corrected downstream packaging.
Controlled folding also results in a consistent formfactor from one electronic
package to the next.
[0040] Figure IF illustrates the entire electronic package 82. Wire bonding wires
24 are located on different sides of the microelectronic die 12. Edges of the flexible
substrate 10 that originally opposed one another are now located in line above one another and in line with an edge of the mold cap 64.
[0041] Figure 2 illustrates further components of the electronic package 82 before
being folded. The electronic package 82, in addition to the flexible substrate 10
and the microelectronic die 12, further includes a plurality of conductive
interconnection members 84, and may further include a second microelectronic
die 86. A core of the flexible substrate 10 is a flexible layer 88 made of polyimide,
an insulator. First and second thin metal layers 90 and 92 are formed on upper
and lower surfaces of the flexible layer 88, respectively. The thin metal layers 90
and 92 are initially formed over the length and width of the flexible layer 88. The
thin metal layer 90 is then patterned so that areas are removed and other areas,
including contacts 94 and traces 96, remain behind.
[0042] A first solder mask 98 is formed over the remaining portions of the first
thin metal layer 90. Areas 100 of the first solder mask 98 are selectively removed
in an etching process, to expose the contacts 94 of the first thin metal layer 90.
[0043] A relatively resilient ground metal layer 102 is then plated on a surface of
the second thin metal layer 92. A second solder mask 104 is subsequently formed
on exposed surfaces of the ground metal layer 102, and patterned to form
openings 106. The second microelectronic die 86 can be connected by way of wire
bonding wires 108 through the openings 106 in the second solder mask 104 and
openings in the ground metal layer 102, the second metal layer 92, and the flexible
layer 88 to some of the contacts 94. The conductive interconnection members 84
are connected in a similar manner through vias 110 to some of the contacts 94. In
such a manner, the microelectronic dies 12 and 86 can be interconnected to one another and to the conductive interconnection members 84. Signals can thus be
provided through the conductive interconnection members 84 to either or both of
the microelectronic dies 12 and 86, and the microelectronic dies 12 and 86 are in
communication with one another.
[0044] The inclusion of the ground metal layer 102 provides the otherwise
flexible substrate 10 with a certain amount of resiliency that tends to resist
bending of the flexible substrate 10. Such a resistance in bending tends to create a
large curvature when an attempt is made to bend the flexible substrate 10, instead
of creating a small fold region. The shaped curved convex surface of the mold cap
(74 and 64 in Figure IE) controls folding of the flexible substrate 10, even if the
ground metal layer 102 is included.
[0045] Figures 3A-D illustrate the manufacture of an electronic package having
first and second microelectronic dies 212 and 286 respectively mounted on the
same side of an unfolded flexible substrate 210. In the present example, the
electronic package includes microelectronic dies 220 and 222, to which the
microelectronic dies 212 and 286 are respectively mounted. Wire bonding wires
224 connect the microelectronic dies 212 and 286 and the microelectronic dies 220
and 222 to the flexible substrate 210.
[0046] With specific reference to Figure 3A, two shape-defining pieces 216A and
216B are located on a fold portion 260 of the flexible substrate 210. The first and
second microelectronic dies 212 and 286 are located on first and second portions,
respectively, on opposing sides of the fold portion 260. A cover piece 214 has a
protrusion 250 which is approximately as high as the shape-defining pieces 216A and 216B, and has a width that is approximately equal to the space in between the
shape-defining pieces 216A and 216B.
[0047] With specific reference to Figure 3B, the cover piece 214 is moved so that
the protrusion 250 is inserted between the shape-defining pieces 216A and 216B,
and remaining areas over the microelectronic dies 212 and 286 are injection-
molded with mold caps 240. As illustrated in Figure 3C, the cover piece 214 and
shape-defining pieces 216 A and 216B are subsequently removed. The mold caps
240 have curved convex surfaces 274. The curved convex surfaces 274 each form
approximately a quarter of a circle, in cross-section, whereas the curved convex
surface 74 illustrated in Figure ID forms approximately a semi-circle in cross-
section.
[0048] Referring to Figure 3D, an adhesive layer 230 is applied to one of the
mold caps 240, and the fold portion 260 of the flexible substrate 210 is folded to
place the second microelectronic die 286 over the first microelectronic die 212.
Folding of the flexible substrate 210 is controlled because the fold portion 260
wraps around the curved convex surfaces 274 of both mold caps 240.
[0049] While certain exemplary embodiments have been described and shown in
the accompanying drawings, it is to be understood that such embodiments are
merely illustrative and not restrictive of the current invention, and that this
invention is not restricted to the specific constructions and arrangements shown
and described since modifications may occur to those ordinarily skilled in the art.

Claims

CLAIMSWhat is claimed:
1. An electronic package, comprising: a substrate having first and second portions and a fold portion between the
first and second portions; a first microelectronic die mounted to the first portion; and at least a first fold-controlling member, the fold portion being wrapped
partially around the first fold-controlling member to place the second portion
over the first portion.
2. The electronic package of claim 1, wherein the first fold-controlling member
is a portion of a first mold cap over the first microelectronic die.
3. The electronic package of claim 2, further comprising an adhesive layer on
the mold cap, the second portion being attached to the adhesive layer.
4. The electronic package of claim 1, wherein the surface of the first fold-
controlling member around which the fold portion is wrapped is curved.
5. The electronic package of claim 4, wherein the surface is curved from the
first portion up to the second portion.
6. The electronic package of claim 1, wherein the first fold-controlling member
is a portion on a first mold cap over the first microelectronic die, the surface of the
first fold-controlling member around which the fold portion is wrapped is curved
from the first portion up to the second portion, further comprising an adhesive
layer on the mold cap, the second portion being attached to the adhesive layer.
7. The electronic package of claim 1, further comprising a second
microelectronic die mounted to the second portion.
8. The electronic package of claim 7, further comprising at least a second fold-
controlling member, the fold portion being wrapped partially around the second
fold-controlling member to place the second portion over the second portion.
9. The electronic package of claim 8, wherein the first and second fold-
controlling members are attached to the first and second portions, respectively,
before the fold portion is wrapped around the fold-controlling portions.
10. The electronic package of claim 9, wherein the second fold-controlling
member is a portion of a second mold cap over the second microelectronic die.
11. The electronic package of claim 10, further comprising an adhesive layer on
the first mold cap, the second mold cap being attached to the adhesive layer.
12. The electronic package of claim 7, further comprising a second
microelectronic die mounted to the second portion, wherein the first fold-
controlling member is a portion on a first mold cap over the first microelectronic
die, wherein the second fold-controlling member is a portion or a second mold
cap over the first microelectronic die, further comprising an adhesive layer on the
first mold cap, the second mold cap being attached to the adhesive layer.
13. An electronic package, comprising: a substrate having first and second portions and a fold portion between the
first and second portions; a microelectronic die mounted to the first portion; a mold cap over the microelectronic die and attached to the first portion, the
mold cap having a curved surface at an edge thereof, the fold portion being
wrapped partially around the mold cap and substantially conforming to a shape
of the curved surface, to place the second portion over the first portion.
14. The electronic package of claim 13, further comprising an adhesive layer on
the mold cap, the second portion being attached to the adhesive layer.
15. The electronic package of claim 14, wherein the second portion is attached
directly to the adhesive layer.
16. An electronic package, comprising: a substrate having first and second portions and a fold portion between the
first and second portions; a first microelectronic die mounted to the first portion; a second microelectronic die mounted to the second portion; a first mold cap over the first microelectronic die and attached to the first
portion, the first mold cap having a first curved surface at an edge thereof; a second mold cap over the second microelectronic die and attached to the
second portion, the second mold cap having a second curved surface at an edge
thereof, the fold portion being partially wrapped around the first curved surface
and partially around the second curved surface to place the second portion over
the first portion.
17. The electronic package of claim 16, further comprising an adhesive layer on
the first mold cap, the second mold cap being attached to the adhesive layer.
18. The electronic package of claim 16, wherein the first and second curved
surfaces jointly form a continuous curvature from the first portion to the second
portion.
19. A method of constructing an electronic package, comprising: mounting a first microelectronic die to a first portion of a substrate having a
fold portion next to the first portion and a second portion next to the fold portion; positioning a fold-controlling member over the substrate; wrapping a fold portion of the substrate partially around a surface of the
fold-controlling portion to place the second portion over the first portion.
20. The method of claim 19, wherein the first fold-controlling member is a
portion on a first mold cap over the first microelectronic die.
21. The method of claim 20, further comprising adhering the second portion to
the mold cap.
22. The method of claim 19, wherein the surface of the first fold-controlling
member around which the fold portion is wrapped is curved.
23. The method of claim 19, wherein the fold-controlling member is injection-
molded.
24. The method of claim 23, further comprising: locating a shape-defining piece on the substrate, the fold-controlling member
being molded against a surface of the shape-defining piece; and removing the shape-defining piece.
25. The method of claim 24, wherein contacting surfaces of the shape-defining
piece and fold-controlling member are concave and converse, respectively.
PCT/US2004/030993 2003-09-22 2004-09-22 Electronic package having a folded flexible substrate and method of manufacturing the same WO2005031865A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP04784735A EP1665379B1 (en) 2003-09-22 2004-09-22 Electronic package having a folded flexible substrate and method of manufacturing the same
JP2006527142A JP4503604B2 (en) 2003-09-22 2004-09-22 Electronic package and method of configuring the same
CN2004800270058A CN1853272B (en) 2003-09-22 2004-09-22 Electronic package having a folded flexible substrate and method of manufacturing the same
AT04784735T ATE556434T1 (en) 2003-09-22 2004-09-22 ELECTRONIC ENCLOSURE HAVING A FOLDED FLEXIBLE SUBSTRATE AND METHOD FOR PRODUCING THE SAME
HK06106657.5A HK1084506A1 (en) 2003-09-22 2006-06-09 Electronic package having a folded flexible substrate and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/668,508 2003-09-22
US10/668,508 US6972482B2 (en) 2003-09-22 2003-09-22 Electronic package having a folded flexible substrate and method of manufacturing the same

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WO2005031865A1 true WO2005031865A1 (en) 2005-04-07

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US (2) US6972482B2 (en)
EP (1) EP1665379B1 (en)
JP (1) JP4503604B2 (en)
KR (1) KR100893653B1 (en)
CN (1) CN1853272B (en)
AT (1) ATE556434T1 (en)
HK (1) HK1084506A1 (en)
SG (1) SG146674A1 (en)
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WO (1) WO2005031865A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6972482B2 (en) 2003-09-22 2005-12-06 Intel Corporation Electronic package having a folded flexible substrate and method of manufacturing the same

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060223227A1 (en) * 2005-04-04 2006-10-05 Tessera, Inc. Molding method for foldover package
US7767543B2 (en) * 2005-09-06 2010-08-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a micro-electro-mechanical device with a folded substrate
CN100459123C (en) * 2005-09-08 2009-02-04 南茂科技股份有限公司 Stack type chip packaging structure, chip packaging body and manufacturing method
US7985623B2 (en) * 2006-04-14 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with contoured encapsulation
US8232628B2 (en) * 2008-01-22 2012-07-31 Nxp B.V. Method for manufacturing a microelectronic package comprising at least one microelectronic device
JP5269532B2 (en) * 2008-09-22 2013-08-21 オリンパスメディカルシステムズ株式会社 Capsule medical device
JP2012506156A (en) * 2008-10-17 2012-03-08 オッカム ポートフォリオ リミテッド ライアビリティ カンパニー Flexible circuit assembly and manufacturing method without using solder
JP4584357B2 (en) * 2008-12-09 2010-11-17 オリンパスメディカルシステムズ株式会社 Capsule type medical device and manufacturing method thereof
US8217507B1 (en) * 2010-01-22 2012-07-10 Amkor Technology, Inc. Edge mount semiconductor package
CN103523739A (en) * 2013-11-05 2014-01-22 华进半导体封装先导技术研发中心有限公司 Packaging structure of three-dimensional flexible substrate of environment MEMS sensor and manufacturing method
CN104637886B (en) * 2013-11-12 2017-09-22 财团法人工业技术研究院 Folding type packaging structure
KR102334240B1 (en) * 2015-07-31 2021-12-01 엘지디스플레이 주식회사 Foldable organic light emitting display device
DE102015219190A1 (en) * 2015-10-05 2017-04-06 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method for producing an electronic component and electronic component
US10388636B2 (en) * 2015-12-21 2019-08-20 Intel Corporation Integrating system in package (SIP) with input/output (IO) board for platform miniaturization
US11355829B2 (en) * 2017-09-12 2022-06-07 Knowles Cazenovia, Inc. Vertical switched filter bank

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010006252A1 (en) 1996-12-13 2001-07-05 Young Kim Stacked microelectronic assembly and method therefor
US6300679B1 (en) 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
US20010040793A1 (en) 2000-02-01 2001-11-15 Tetsuya Inaba Electronic device and method of producing the same
US6351029B1 (en) 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US20030020153A1 (en) 2001-07-24 2003-01-30 Ted Bruce Chip stack with differing chip package types
US20040104470A1 (en) * 2002-08-16 2004-06-03 Tessera, Inc. Microelectronic packages with self-aligning features

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06101493B2 (en) * 1986-03-28 1994-12-12 松下電器産業株式会社 Plastic chip carrier
JPS63228654A (en) * 1987-03-18 1988-09-22 Hitachi Ltd Electronic device and manufacture thereof
US5345205A (en) * 1990-04-05 1994-09-06 General Electric Company Compact high density interconnected microwave system
US6323060B1 (en) * 1999-05-05 2001-11-27 Dense-Pac Microsystems, Inc. Stackable flex circuit IC package and method of making same
US6972482B2 (en) 2003-09-22 2005-12-06 Intel Corporation Electronic package having a folded flexible substrate and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010006252A1 (en) 1996-12-13 2001-07-05 Young Kim Stacked microelectronic assembly and method therefor
US6300679B1 (en) 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
US6351029B1 (en) 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US20010040793A1 (en) 2000-02-01 2001-11-15 Tetsuya Inaba Electronic device and method of producing the same
US20030020153A1 (en) 2001-07-24 2003-01-30 Ted Bruce Chip stack with differing chip package types
US20040104470A1 (en) * 2002-08-16 2004-06-03 Tessera, Inc. Microelectronic packages with self-aligning features

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6972482B2 (en) 2003-09-22 2005-12-06 Intel Corporation Electronic package having a folded flexible substrate and method of manufacturing the same
US7148087B2 (en) 2003-09-22 2006-12-12 Intel Corporation Electronic package having a folded flexible substrate and method of manufacturing the same

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Publication number Publication date
JP2007506285A (en) 2007-03-15
US20060008949A1 (en) 2006-01-12
TWI253162B (en) 2006-04-11
HK1084506A1 (en) 2006-07-28
KR100893653B1 (en) 2009-04-17
TW200512922A (en) 2005-04-01
ATE556434T1 (en) 2012-05-15
EP1665379A1 (en) 2006-06-07
CN1853272B (en) 2010-11-17
CN1853272A (en) 2006-10-25
US6972482B2 (en) 2005-12-06
EP1665379B1 (en) 2012-05-02
SG146674A1 (en) 2008-10-30
US20050062141A1 (en) 2005-03-24
US7148087B2 (en) 2006-12-12
JP4503604B2 (en) 2010-07-14
KR20060054466A (en) 2006-05-22

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