WO2005036807A3 - Forward error correction mapping and de-mapping techniques - Google Patents

Forward error correction mapping and de-mapping techniques Download PDF

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Publication number
WO2005036807A3
WO2005036807A3 PCT/US2004/027681 US2004027681W WO2005036807A3 WO 2005036807 A3 WO2005036807 A3 WO 2005036807A3 US 2004027681 W US2004027681 W US 2004027681W WO 2005036807 A3 WO2005036807 A3 WO 2005036807A3
Authority
WO
WIPO (PCT)
Prior art keywords
mapping
error correction
forward error
techniques
mapping techniques
Prior art date
Application number
PCT/US2004/027681
Other languages
French (fr)
Other versions
WO2005036807A2 (en
Inventor
Niklas Linkewitsch
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to DE112004001600T priority Critical patent/DE112004001600B4/en
Priority to GB0606296A priority patent/GB2422078B/en
Priority to CN2004800258681A priority patent/CN1849767B/en
Publication of WO2005036807A2 publication Critical patent/WO2005036807A2/en
Publication of WO2005036807A3 publication Critical patent/WO2005036807A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909—Product codes

Abstract

Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.
PCT/US2004/027681 2003-09-10 2004-08-25 Forward error correction mapping and de-mapping techniques WO2005036807A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE112004001600T DE112004001600B4 (en) 2003-09-10 2004-08-25 Mapping and demapping techniques for forward error correction
GB0606296A GB2422078B (en) 2003-09-10 2004-08-25 Forward error correction mapping and de-mapping techniques
CN2004800258681A CN1849767B (en) 2003-09-10 2004-08-25 Forward error correction mapping and de-mapping techniques

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/660,404 US7415658B2 (en) 2003-09-10 2003-09-10 Forward error correction mapping and de-mapping techniques
US10/660,404 2003-09-10

Publications (2)

Publication Number Publication Date
WO2005036807A2 WO2005036807A2 (en) 2005-04-21
WO2005036807A3 true WO2005036807A3 (en) 2005-08-18

Family

ID=34227057

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/027681 WO2005036807A2 (en) 2003-09-10 2004-08-25 Forward error correction mapping and de-mapping techniques

Country Status (6)

Country Link
US (3) US7415658B2 (en)
CN (2) CN101977092B (en)
DE (2) DE112004001600B4 (en)
GB (1) GB2422078B (en)
TW (1) TWI269563B (en)
WO (1) WO2005036807A2 (en)

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US7415658B2 (en) 2003-09-10 2008-08-19 Intel Corporation Forward error correction mapping and de-mapping techniques
FR2869744A1 (en) * 2004-04-29 2005-11-04 Thomson Licensing Sa METHOD FOR TRANSMITTING DIGITAL DATA PACKETS AND APPARATUS IMPLEMENTING THE METHOD
US8116309B2 (en) * 2006-08-11 2012-02-14 PSIMAST, Inc Enhanced Ethernet protocol for shortened data frames within a constrained neighborhood based on unique ID
US8160057B2 (en) * 2008-06-30 2012-04-17 Applied Micro Circuits Corporation Multi-channel optical transport network training signal
US8296630B2 (en) * 2008-10-02 2012-10-23 Fujitsu Limited Multi-mode forward error correction
US8359518B2 (en) * 2009-10-27 2013-01-22 Altera Canada Co. 2D product code and method for detecting false decoding errors
US8392788B2 (en) * 2009-11-24 2013-03-05 Cortina Systems, Inc. Transport network system with transparent transport and method of operation thereof
CN101789845B (en) * 2010-02-22 2013-01-16 烽火通信科技股份有限公司 Method and circuit applying SFEC to realize bit width transformation of bus in OTN (optical transport network)
US8499219B2 (en) * 2011-12-13 2013-07-30 Broadcom Corporation Encoding methods and systems for binary product codes
US9438376B2 (en) * 2013-03-15 2016-09-06 Cortina Systems, Inc. Apparatus and method for forward error correction over a communication channel
US9979566B2 (en) 2016-09-27 2018-05-22 Intel Corporation Hybrid forward error correction and replay technique for low latency
US10567102B2 (en) 2017-02-06 2020-02-18 Valens Semiconductor Ltd. Efficient double parity forward error correction on a communication network
CN114079534B (en) * 2020-08-20 2023-03-28 腾讯科技（深圳）有限公司 Encoding method, decoding method, apparatus, medium, and electronic device

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EP0663776A2 (en) * 1994-01-18 1995-07-19 General Instrument Corporation Of Delaware Method for communicating block coded digital data with associated synchronization/control data
US20020161972A1 (en) * 2001-04-30 2002-10-31 Talagala Nisha D. Data storage array employing block checksums and dynamic striping
US20030135514A1 (en) * 2001-08-03 2003-07-17 Patel Sujal M. Systems and methods for providing a distributed file system incorporating a virtual hot spare

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US4329708A (en) * 1979-10-25 1982-05-11 Sony Corporation Digital signal processing apparatus
EP0663776A2 (en) * 1994-01-18 1995-07-19 General Instrument Corporation Of Delaware Method for communicating block coded digital data with associated synchronization/control data
US20020161972A1 (en) * 2001-04-30 2002-10-31 Talagala Nisha D. Data storage array employing block checksums and dynamic striping
US20030135514A1 (en) * 2001-08-03 2003-07-17 Patel Sujal M. Systems and methods for providing a distributed file system incorporating a virtual hot spare

Also Published As

Publication number Publication date
US7415658B2 (en) 2008-08-19
DE112004001600B4 (en) 2010-06-24
CN1849767B (en) 2010-11-03
DE112004001600T5 (en) 2006-07-27
US20050053285A1 (en) 2005-03-10
CN101977092B (en) 2013-06-12
GB2422078A (en) 2006-07-12
WO2005036807A2 (en) 2005-04-21
DE112004003070B4 (en) 2012-03-01
GB2422078B (en) 2007-07-18
TWI269563B (en) 2006-12-21
US20120137196A1 (en) 2012-05-31
US8132087B2 (en) 2012-03-06
CN1849767A (en) 2006-10-18
US20080301535A1 (en) 2008-12-04
TW200518534A (en) 2005-06-01
US8707142B2 (en) 2014-04-22
CN101977092A (en) 2011-02-16
GB0606296D0 (en) 2006-05-10

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