WO2005038864A3 - Circuit and method for controlling a clock synchronizing circuit for low power refresh operation - Google Patents

Circuit and method for controlling a clock synchronizing circuit for low power refresh operation Download PDF

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Publication number
WO2005038864A3
WO2005038864A3 PCT/US2004/032037 US2004032037W WO2005038864A3 WO 2005038864 A3 WO2005038864 A3 WO 2005038864A3 US 2004032037 W US2004032037 W US 2004032037W WO 2005038864 A3 WO2005038864 A3 WO 2005038864A3
Authority
WO
WIPO (PCT)
Prior art keywords
refresh operation
circuit
controlling
low power
clock synchronizing
Prior art date
Application number
PCT/US2004/032037
Other languages
French (fr)
Other versions
WO2005038864A2 (en
Inventor
Aaron M Schoenfeld
Ross E Dermott
Original Assignee
Micron Technology Inc
Aaron M Schoenfeld
Ross E Dermott
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=34422918&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2005038864(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Micron Technology Inc, Aaron M Schoenfeld, Ross E Dermott filed Critical Micron Technology Inc
Priority to EP04789283A priority Critical patent/EP1671357B1/en
Priority to DE602004021124T priority patent/DE602004021124D1/en
Priority to AT04789283T priority patent/ATE431612T1/en
Priority to JP2006534066A priority patent/JP4956734B2/en
Publication of WO2005038864A2 publication Critical patent/WO2005038864A2/en
Publication of WO2005038864A3 publication Critical patent/WO2005038864A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Abstract

A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.
PCT/US2004/032037 2003-10-09 2004-09-29 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation WO2005038864A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP04789283A EP1671357B1 (en) 2003-10-09 2004-09-29 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
DE602004021124T DE602004021124D1 (en) 2003-10-09 2004-09-29 CIRCUIT AND METHOD FOR CONTROLLING A CLOCK SYNCHRONIZATION CIRCUIT FOR LOW POWER REFRESHING OPERATION
AT04789283T ATE431612T1 (en) 2003-10-09 2004-09-29 CIRCUIT AND METHOD FOR CONTROLLING A CLOCK SYNCHRONIZATION CIRCUIT FOR A LOW POWER REFRESH OPERATION
JP2006534066A JP4956734B2 (en) 2003-10-09 2004-09-29 Circuit and method for controlling a clock synchronization circuit for low power refresh operation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/684,123 2003-10-09
US10/684,123 US6975556B2 (en) 2003-10-09 2003-10-09 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation

Publications (2)

Publication Number Publication Date
WO2005038864A2 WO2005038864A2 (en) 2005-04-28
WO2005038864A3 true WO2005038864A3 (en) 2006-08-03

Family

ID=34422918

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/032037 WO2005038864A2 (en) 2003-10-09 2004-09-29 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation

Country Status (8)

Country Link
US (5) US6975556B2 (en)
EP (1) EP1671357B1 (en)
JP (1) JP4956734B2 (en)
KR (1) KR100903012B1 (en)
CN (1) CN1902708A (en)
AT (1) ATE431612T1 (en)
DE (1) DE602004021124D1 (en)
WO (1) WO2005038864A2 (en)

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US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US6975556B2 (en) * 2003-10-09 2005-12-13 Micron Technology, Inc. Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
US7345940B2 (en) * 2003-11-18 2008-03-18 Infineon Technologies Ag Method and circuit configuration for refreshing data in a semiconductor memory
US7233538B1 (en) * 2004-08-02 2007-06-19 Sun Microsystems, Inc. Variable memory refresh rate for DRAM
US7366862B2 (en) * 2004-11-12 2008-04-29 Lsi Logic Corporation Method and apparatus for self-adjusting input delay in DDR-based memory systems
JP4919333B2 (en) * 2005-09-29 2012-04-18 株式会社ハイニックスセミコンダクター Data input device for semiconductor memory device
JP4837357B2 (en) * 2005-10-18 2011-12-14 エルピーダメモリ株式会社 Semiconductor memory device
US7970086B2 (en) * 2007-08-15 2011-06-28 Infineon Technologies Ag System and method for clock drift compensation
CN101903953B (en) * 2007-12-21 2013-12-18 莫塞德技术公司 Non-volatile semiconductor memory device with power saving feature
JP2010176783A (en) * 2009-02-02 2010-08-12 Elpida Memory Inc Semiconductor device, its control method, and semiconductor system including semiconductor device and controller controlling the same
US7957218B2 (en) * 2009-06-11 2011-06-07 Freescale Semiconductor, Inc. Memory controller with skew control and method
US8300464B2 (en) 2010-04-13 2012-10-30 Freescale Semiconductor, Inc. Method and circuit for calibrating data capture in a memory controller
KR20120070436A (en) * 2010-12-21 2012-06-29 에스케이하이닉스 주식회사 A semiconductor memory apparatus
US8942056B2 (en) 2011-02-23 2015-01-27 Rambus Inc. Protocol for memory power-mode control
US8933715B2 (en) 2012-04-08 2015-01-13 Elm Technology Corporation Configurable vertical integration
KR101980162B1 (en) * 2012-06-28 2019-08-28 에스케이하이닉스 주식회사 Memrory
US9153310B2 (en) 2013-01-16 2015-10-06 Maxlinear, Inc. Dynamic random access memory for communications systems
US10169262B2 (en) * 2015-07-14 2019-01-01 Qualcomm Incorporated Low-power clocking for a high-speed memory interface
KR20180047778A (en) * 2016-11-01 2018-05-10 삼성전자주식회사 Memory device with stepwise low power states
KR20180114712A (en) * 2017-04-11 2018-10-19 에스케이하이닉스 주식회사 Refresh controller and semiconductor memory device including the same
EP3641951B1 (en) 2017-06-22 2023-09-20 The Procter & Gamble Company Films including a water-soluble layer and a vapor-deposited organic coating
CN110719968A (en) 2017-06-22 2020-01-21 宝洁公司 Film comprising a water-soluble layer and a vapor-deposited inorganic coating
US10339998B1 (en) * 2018-03-27 2019-07-02 Micron Technology, Inc. Apparatuses and methods for providing clock signals in a semiconductor device
US10892764B1 (en) * 2020-08-14 2021-01-12 Winbond Electronics Corp. Delay locked loop device and update method thereof

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US6525988B2 (en) * 2000-11-24 2003-02-25 Samsung Electronics Co., Ltd. Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same
US6828106B2 (en) * 1999-02-26 2004-12-07 Cyclacel Limited Methods and compositions using coiled binding partners

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Patent Citations (2)

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US6828106B2 (en) * 1999-02-26 2004-12-07 Cyclacel Limited Methods and compositions using coiled binding partners
US6525988B2 (en) * 2000-11-24 2003-02-25 Samsung Electronics Co., Ltd. Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same

Also Published As

Publication number Publication date
US20100014371A1 (en) 2010-01-21
US20110273938A1 (en) 2011-11-10
EP1671357A2 (en) 2006-06-21
US20060274592A1 (en) 2006-12-07
EP1671357B1 (en) 2009-05-13
EP1671357A4 (en) 2007-03-14
US6975556B2 (en) 2005-12-13
KR20060118468A (en) 2006-11-23
US7106646B2 (en) 2006-09-12
CN1902708A (en) 2007-01-24
US7606101B2 (en) 2009-10-20
JP2007508649A (en) 2007-04-05
WO2005038864A2 (en) 2005-04-28
US7983110B2 (en) 2011-07-19
US20050254327A1 (en) 2005-11-17
US20050078539A1 (en) 2005-04-14
ATE431612T1 (en) 2009-05-15
US8400868B2 (en) 2013-03-19
DE602004021124D1 (en) 2009-06-25
JP4956734B2 (en) 2012-06-20
KR100903012B1 (en) 2009-06-17

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