WO2005041023A3 - System and method using embedded microprocessor as a node in an adaptable computing machine - Google Patents

System and method using embedded microprocessor as a node in an adaptable computing machine Download PDF

Info

Publication number
WO2005041023A3
WO2005041023A3 PCT/US2004/002246 US2004002246W WO2005041023A3 WO 2005041023 A3 WO2005041023 A3 WO 2005041023A3 US 2004002246 W US2004002246 W US 2004002246W WO 2005041023 A3 WO2005041023 A3 WO 2005041023A3
Authority
WO
WIPO (PCT)
Prior art keywords
node
nodes
present
psn
ace
Prior art date
Application number
PCT/US2004/002246
Other languages
French (fr)
Other versions
WO2005041023A2 (en
Inventor
Rojit Jacob
Original Assignee
Quicksilver Tech Inc
Rojit Jacob
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quicksilver Tech Inc, Rojit Jacob filed Critical Quicksilver Tech Inc
Publication of WO2005041023A2 publication Critical patent/WO2005041023A2/en
Publication of WO2005041023A3 publication Critical patent/WO2005041023A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • G06F15/17381Two dimensional, e.g. mesh, torus

Abstract

The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing. The present invention further provides an interconnection scheme so that a plurality of ACE devices operates under the control of a single k-node.
PCT/US2004/002246 2003-09-29 2004-01-26 System and method using embedded microprocessor as a node in an adaptable computing machine WO2005041023A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/673,678 2003-09-29
US10/673,678 US7502915B2 (en) 2002-09-30 2003-09-29 System and method using embedded microprocessor as a node in an adaptable computing machine

Publications (2)

Publication Number Publication Date
WO2005041023A2 WO2005041023A2 (en) 2005-05-06
WO2005041023A3 true WO2005041023A3 (en) 2006-03-09

Family

ID=34520478

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/002246 WO2005041023A2 (en) 2003-09-29 2004-01-26 System and method using embedded microprocessor as a node in an adaptable computing machine

Country Status (2)

Country Link
US (1) US7502915B2 (en)
WO (1) WO2005041023A2 (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7900052B2 (en) * 2002-11-06 2011-03-01 International Business Machines Corporation Confidential data sharing and anonymous entity resolution
US7870182B2 (en) * 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US7853632B2 (en) * 2003-12-29 2010-12-14 Xilinx, Inc. Architectural floorplan for a digital signal processing circuit
US7480690B2 (en) * 2003-12-29 2009-01-20 Xilinx, Inc. Arithmetic circuit with multiplexed addend inputs
US7853634B2 (en) * 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a SIMD circuit
US7882165B2 (en) * 2003-12-29 2011-02-01 Xilinx, Inc. Digital signal processing element having an arithmetic logic unit
US7860915B2 (en) * 2003-12-29 2010-12-28 Xilinx, Inc. Digital signal processing circuit having a pattern circuit for determining termination conditions
US7844653B2 (en) * 2003-12-29 2010-11-30 Xilinx, Inc. Digital signal processing circuit having a pre-adder circuit
US7840627B2 (en) * 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US8495122B2 (en) * 2003-12-29 2013-07-23 Xilinx, Inc. Programmable device with dynamic DSP architecture
US7840630B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Arithmetic logic unit circuit
US7567997B2 (en) * 2003-12-29 2009-07-28 Xilinx, Inc. Applications of cascading DSP slices
US7467175B2 (en) 2003-12-29 2008-12-16 Xilinx, Inc. Programmable logic device with pipelined DSP slices
US7467177B2 (en) * 2003-12-29 2008-12-16 Xilinx, Inc. Mathematical circuit with dynamic rounding
US7849119B2 (en) * 2003-12-29 2010-12-07 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit
US7853636B2 (en) * 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit for convergent rounding
US7472155B2 (en) * 2003-12-29 2008-12-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US7865542B2 (en) * 2003-12-29 2011-01-04 Xilinx, Inc. Digital signal processing block having a wide multiplexer
US7483422B2 (en) * 2005-02-10 2009-01-27 International Business Machines Corporation Data processing system, method and interconnect fabric for selective link information allocation in a data processing system
EP1713007B1 (en) * 2005-04-11 2008-09-17 STMicroelectronics S.r.l. A dynamically reconfigurable System-on-Chip comprising a plurality of reconfigurable gate array devices
US8204213B2 (en) * 2006-03-29 2012-06-19 International Business Machines Corporation System and method for performing a similarity measure of anonymized data
US8082289B2 (en) 2006-06-13 2011-12-20 Advanced Cluster Systems, Inc. Cluster computing support for application programs
US8204831B2 (en) * 2006-11-13 2012-06-19 International Business Machines Corporation Post-anonymous fuzzy comparisons without the use of pre-anonymization variants
US9653004B2 (en) * 2008-10-16 2017-05-16 Cypress Semiconductor Corporation Systems and methods for downloading code and data into a secure non-volatile memory
US8479133B2 (en) * 2009-01-27 2013-07-02 Xilinx, Inc. Method of and circuit for implementing a filter in an integrated circuit
US8543635B2 (en) * 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage
US20170339343A1 (en) * 2016-05-17 2017-11-23 Tijee Corporation Multi-functional camera
US11809875B2 (en) * 2021-10-07 2023-11-07 Dell Products L.P. Low-power pre-boot operations using a multiple cores for an information handling system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023755A (en) * 1992-07-29 2000-02-08 Virtual Computer Corporation Computer with programmable arrays which are reconfigurable in response to instructions to be executed
US20030154357A1 (en) * 2001-03-22 2003-08-14 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5165023A (en) * 1986-12-17 1992-11-17 Massachusetts Institute Of Technology Parallel processing system with processor array and network communications system for transmitting messages of variable length
US5450557A (en) * 1989-11-07 1995-09-12 Loral Aerospace Corp. Single-chip self-configurable parallel processor
CA2073516A1 (en) * 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
US5636368A (en) * 1994-12-23 1997-06-03 Xilinx, Inc. Method for programming complex PLD having more than one function block type
US5892961A (en) * 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5737631A (en) * 1995-04-05 1998-04-07 Xilinx Inc Reprogrammable instruction set accelerator
US5646544A (en) * 1995-06-05 1997-07-08 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5646545A (en) * 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
US5784313A (en) * 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5943242A (en) * 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US5734582A (en) * 1995-12-12 1998-03-31 International Business Machines Corporation Method and system for layout and schematic generation for heterogeneous arrays
US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US5889816A (en) * 1996-02-02 1999-03-30 Lucent Technologies, Inc. Wireless adapter architecture for mobile computing
US6237029B1 (en) * 1996-02-26 2001-05-22 Argosystems, Inc. Method and apparatus for adaptable digital protocol processing
US5956518A (en) * 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US5907580A (en) * 1996-06-10 1999-05-25 Morphics Technology, Inc Method and apparatus for communicating information
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US5828858A (en) * 1996-09-16 1998-10-27 Virginia Tech Intellectual Properties, Inc. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US5825202A (en) * 1996-09-26 1998-10-20 Xilinx, Inc. Integrated circuit with field programmable and application specific logic areas
DE19651075A1 (en) * 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration procedure for programmable blocks at runtime
US6338106B1 (en) * 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654595A1 (en) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures
DE19704728A1 (en) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
US6542998B1 (en) * 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (en) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US5970254A (en) * 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US6120551A (en) * 1997-09-29 2000-09-19 Xilinx, Inc. Hardwire logic device emulating an FPGA
US6173389B1 (en) * 1997-12-04 2001-01-09 Billions Of Operations Per Second, Inc. Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
DE69827589T2 (en) * 1997-12-17 2005-11-03 Elixent Ltd. Configurable processing assembly and method of using this assembly to build a central processing unit
DE19861088A1 (en) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
US6230307B1 (en) * 1998-01-26 2001-05-08 Xilinx, Inc. System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
DE19807872A1 (en) * 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
JPH11261440A (en) * 1998-03-11 1999-09-24 Oki Electric Ind Co Ltd Receiver
US6088043A (en) * 1998-04-30 2000-07-11 3D Labs, Inc. Scalable graphics processor architecture
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US6282627B1 (en) * 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6150838A (en) * 1999-02-25 2000-11-21 Xilinx, Inc. FPGA configurable logic block with multi-purpose logic/memory circuit
US6433578B1 (en) * 1999-05-07 2002-08-13 Morphics Technology, Inc. Heterogeneous programmable gate array
US6326806B1 (en) * 2000-03-29 2001-12-04 Xilinx, Inc. FPGA-based communications access point and system for reconfiguration
DE50115584D1 (en) * 2000-06-13 2010-09-16 Krass Maren PIPELINE CT PROTOCOLS AND COMMUNICATION
US20020133688A1 (en) * 2001-01-29 2002-09-19 Ming-Hau Lee SIMD/MIMD processing on a reconfigurable array
US7210129B2 (en) * 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7444531B2 (en) * 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US6836839B2 (en) * 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
EP1537486A1 (en) * 2002-09-06 2005-06-08 PACT XPP Technologies AG Reconfigurable sequencer structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023755A (en) * 1992-07-29 2000-02-08 Virtual Computer Corporation Computer with programmable arrays which are reconfigurable in response to instructions to be executed
US20030154357A1 (en) * 2001-03-22 2003-08-14 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Virtex-II Pro Platform FPGAs: Functional Description DS083-2 (v2.5)", PRODUCT SPECIFICATION XILINX, XX, XX, 20 January 2003 (2003-01-20), pages 13 - 46, XP002279387 *

Also Published As

Publication number Publication date
US20040143724A1 (en) 2004-07-22
WO2005041023A2 (en) 2005-05-06
US7502915B2 (en) 2009-03-10

Similar Documents

Publication Publication Date Title
WO2005041023A3 (en) System and method using embedded microprocessor as a node in an adaptable computing machine
TWI439928B (en) Configurable executing unit, method of operating the same, and computer program product and instruction set thereof
EP1416388A4 (en) Integrated circuit device
US7539848B1 (en) Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor
IL142676A0 (en) Control program product and data processing system
AU2003295744A1 (en) Processing architecture for a reconfigurable arithmetic node in an adaptive computing system
WO2003038645A3 (en) A scalable processing architecture
WO2007095397A3 (en) Programmable processing unit
WO2005101190A3 (en) Processor having parallel vector multiply and reduce operations with sequential semantics
WO2006116046A3 (en) Asynchronous processor
WO2008131143A3 (en) Dynamically configurable and re-configurable data path
SE9903606D0 (en) A computer based method and system for controlling an industrial process
TW200730862A (en) Magnetic sensor control device
WO2004056154A3 (en) Hearing device and method for choosing a program in a multi program hearing device
WO2013176809A3 (en) System and method for control of linear and rotary vibrators in an electronic device
WO2003081454A8 (en) Method and device for data processing
WO2004034159A3 (en) A method of controlling an electronic or computer system
WO2021044219A3 (en) Hardware architecture for modularized eyewear systems apparatuses, and methods
WO2001014960A3 (en) Generic interface for a software module
ATE523847T1 (en) DIGITAL SIGNAL PROCESSOR WITH SEVERAL INDEPENDENT ASSOCIATED PROCESSORS
WO2004025700A3 (en) Programmable serial interface for a semiconductor circuit
WO2007027616A3 (en) Programmable digital filter
JP6351273B2 (en) I / O unit
WO2002007449A3 (en) Method and system for determining the actual projection data for a projection of a spatially variable surface
EP1686510A4 (en) Electronic device and control method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 69(1) EPC (COMMUNICATION DATED 04-07-2006, EPO FORM 1205A)

122 Ep: pct application non-entry in european phase