WO2005050557A2 - Method and system for multiple 3-d graphic pipeline over a pc bus - Google Patents

Method and system for multiple 3-d graphic pipeline over a pc bus Download PDF

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Publication number
WO2005050557A2
WO2005050557A2 PCT/IL2004/001069 IL2004001069W WO2005050557A2 WO 2005050557 A2 WO2005050557 A2 WO 2005050557A2 IL 2004001069 W IL2004001069 W IL 2004001069W WO 2005050557 A2 WO2005050557 A2 WO 2005050557A2
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WIPO (PCT)
Prior art keywords
graphic
gpus
data
gpu
hub
Prior art date
Application number
PCT/IL2004/001069
Other languages
French (fr)
Other versions
WO2005050557A3 (en
Inventor
Reuven Bakalash
Offir Remez
Gigy Bar-Or
Efi Fogel
Amir Shaham
Original Assignee
Lucid Information Technology Ltd.
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Publication date
Application filed by Lucid Information Technology Ltd. filed Critical Lucid Information Technology Ltd.
Priority to JP2006540774A priority Critical patent/JP2007512613A/en
Priority to CA002546427A priority patent/CA2546427A1/en
Priority to EP04799376A priority patent/EP1687732A4/en
Priority to US10/579,682 priority patent/US7808499B2/en
Publication of WO2005050557A2 publication Critical patent/WO2005050557A2/en
Publication of WO2005050557A3 publication Critical patent/WO2005050557A3/en
Priority to US11/340,402 priority patent/US7812844B2/en
Priority to US11/386,454 priority patent/US7834880B2/en
Priority to US11/655,735 priority patent/US8085273B2/en
Priority to US11/897,536 priority patent/US7961194B2/en
Priority to US11/901,692 priority patent/US7777748B2/en
Priority to US11/901,727 priority patent/US20080094402A1/en
Priority to US11/901,714 priority patent/US20080074429A1/en
Priority to US11/901,733 priority patent/US20080094404A1/en
Priority to US11/901,713 priority patent/US20080068389A1/en
Priority to US11/901,716 priority patent/US20080246772A1/en
Priority to US11/901,697 priority patent/US20080074428A1/en
Priority to US11/901,715 priority patent/US20080074431A1/en
Priority to US11/901,745 priority patent/US20080079737A1/en
Priority to US11/901,696 priority patent/US20080088631A1/en
Priority to US11/903,187 priority patent/US20080094403A1/en
Priority to US11/903,202 priority patent/US20080198167A1/en
Priority to US11/903,203 priority patent/US20080316216A1/en
Priority to US11/904,043 priority patent/US20080088632A1/en
Priority to US11/904,041 priority patent/US20080084421A1/en
Priority to US11/904,040 priority patent/US7940274B2/en
Priority to US11/904,022 priority patent/US20080084418A1/en
Priority to US11/904,042 priority patent/US20080084422A1/en
Priority to US11/904,039 priority patent/US20080084419A1/en
Priority to US11/904,294 priority patent/US20080084423A1/en
Priority to US11/904,317 priority patent/US8125487B2/en
Priority to US11/904,300 priority patent/US7944450B2/en
Priority to US11/977,155 priority patent/US8629877B2/en
Priority to US11/977,161 priority patent/US7796129B2/en
Priority to US11/977,172 priority patent/US7800610B2/en
Priority to US11/977,177 priority patent/US7796130B2/en
Priority to US11/977,178 priority patent/US7800611B2/en
Priority to US11/977,164 priority patent/US7800619B2/en
Priority to US11/977,719 priority patent/US20080117218A1/en
Priority to US11/978,149 priority patent/US20080129743A1/en
Priority to US11/978,239 priority patent/US7812846B2/en
Priority to US11/978,226 priority patent/US7812845B2/en
Priority to US11/978,220 priority patent/US7843457B2/en
Priority to US11/978,228 priority patent/US7808504B2/en
Priority to US11/978,146 priority patent/US20080129741A1/en
Priority to US11/978,148 priority patent/US20080129742A1/en
Priority to US11/978,229 priority patent/US20080122850A1/en
Priority to US11/980,318 priority patent/US20080211817A1/en
Priority to US11/978,993 priority patent/US20080129747A1/en
Priority to US11/980,089 priority patent/US8134563B2/en
Priority to US12/077,072 priority patent/US20090027383A1/en
Priority to US12/229,215 priority patent/US20090135190A1/en
Priority to US12/231,304 priority patent/US8284207B2/en
Priority to US12/231,295 priority patent/US20090128550A1/en
Priority to US12/231,296 priority patent/US20090179894A1/en
Priority to US12/941,233 priority patent/US8754894B2/en
Priority to US12/946,032 priority patent/US8754897B2/en
Priority to US13/101,438 priority patent/US20110279462A1/en
Priority to US13/646,710 priority patent/US20130120410A1/en
Priority to US14/153,105 priority patent/US9405586B2/en
Priority to US14/304,991 priority patent/US9659340B2/en
Priority to US14/305,010 priority patent/US9584592B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1438—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using more than one graphics controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware

Definitions

  • the present invention relates to a method and system for 3-D (three- dimensional) multiple graphic processing. More particularly, the invention relates to a method and system for improving the parallelization of image processing by Graphic Processing, Units (GPUs), based on unified framework of three parallelization methods, which are time division, image division and object division methods.
  • GPUs Graphic Processing, Units
  • GPU Graphic Processing Unit
  • CPU Central Processing Unit
  • a GPU is a single-chip processor which is used primarily for computing 3-D functions. This includes tasks such as, lighting effects, object transformations, and 3-D motion. These are mathematically-intensive tasks, which otherwise, would put quite a strain on the CPU, but since the specialized GPU can handle most of the 3-D calculations, it helps the computer to perform these tasks more efficiently, and, of course, faster.
  • Polygons in 3-D graphics are two-dimensional primitives, allowing generating and displaying of 3-D complex graphical objects.
  • the polygons are the faces of the object and are composed from N vertices.
  • a polygon is a closed plane figure, bounded by three or more line segments.
  • Frame Buffer is a buffer that stores the contents of an image, pixel by pixel. Generally, the portion of memory is reserved for holding the complete bit-mapped image that is sent to the monitor, for display. Typically the frame buffer is stored in the memory chips on the video adapter. In some instances, however, the video chipset is integrated into the motherboard design, and the frame buffer is stored in the general main memory.
  • Object compositing unit performs re-composition of multiple three- dimensional rasters into final image.
  • the merged data is resolved for the closest pixel to the viewer in 3-D space, based on the depth value of pixels.
  • the new method based on autonomous associative decision, allows the use of multiple GPUs for any frame complexity.
  • Display list is a description of the 3-D scene through a list of graphic primitives, such as polygons and attributes.
  • the display list provides intermediate image storage for quick image retrieval.
  • Vertex array a Vertex Array is an array of vertices describing the 3-D scene.
  • a Vertex Array provides intermediate image storage for quick image retrieval.
  • Alpha blending controls the way in which the graphic information is displayed, such as levels of transparency, or opacity.
  • the three dimensional graphic pipeline architecture breaks-down into segmented stages of CPU, Bus, GPU vertex processing and GPU fragment (pixel) processing.
  • a given pipeline is only as strong as the weakest link of one of the above stages, thus the main bottleneck determines the overall throughput. Enhancing performance is all that required for reducing or eliminating bottlenecks.
  • the major bottleneck strongly depends on the application. Extreme cases are CAD-like (Computer Aided Design) applications, characterized by an abundance of polygons (vertices), vs. video- game applications having a small polygon count but intensive fragment activity (e.g., texturing). The first class suffers from vertex processing bottlenecks, while the second class suffers from fragment bottlenecks. Both are frequently jammed over the PC bus. Many applications have mixed characteristics, where bottlenecks may randomly alternate between extremes, on a single frame basis.
  • the only way to improve the performance of the GPU is by means of parallelizing multiple GPUs according to one of the bottleneck solving methods.
  • time division time domain composition
  • image division screen space composition
  • each GPU renders a subset of the pixels of each frame.
  • each GPU renders the next successive frame. It has the disadvantage of having each GPU render an entire frame. Thus, the speed at which each frame is rendered is limited to the rendering rate of a single GPU. While multiple GPUs enable a higher frame rate, a delay can be imparted in the response time (latency) of the system to a user's input. This occurs because, while at any given time, only one GPU is engaged in displaying a rendered frame, each of the GPUs is in the process of rendering one of a series of frames in a sequence. To maintain the high frame rate, the system delays the user's input until the specific GPU, which first received the signal cycles through the sequence, is again engaged in displa3>ing its rendered frame.
  • Image division method splits the screen between N GPUs, such that each one displays 1/N of the image.
  • the entire polygon set is transferred to each GPU for processing, however, the pixel processing is significantly reduced to the window size.
  • Image division has no latency issues, but it has a similar bottleneck with large data sets, since each GPU must examine the entire database to determine which graphic elements fall within the portion of the screen allocated to said GPU.
  • Image division method suits applications with intensive pixel processing.
  • Object division method is based on distribution of data subsets between multiple GPUs.
  • the data subsets are rendered in the GPU pipeline, and converted to Frame Buffer (FB) of fragments (sub-image pixels).
  • FB Frame Buffer
  • the multiple FB's sub-images have to be merged (composited) to generate the final image to be displayed.
  • Object division delivers parallel rendering on the level of a single frame of very complex data consisting of large amount of polygons.
  • the input data is decomposed in the polygon level and re-composed in the pixel level.
  • a proprietary driver intelligently distributes data streams, which are generated by the application, between all GPUs.
  • the rasters, generated by the GPUs are composited into final raster, and moved to the display.
  • the object division method well suits applications that need to render a vast amount of geometrical data.
  • these are CAD, Digital Content Creation, and comparable visual simulation applications, considered as "viewers,” meaning that the data has been pre-designed such that their three-dimensional positions in space are not under the interactive control of the user.
  • the user does have interactive control over the viewer's position, the direction of view, and the scale of the graphic data.
  • the user also may have control over the selection of a subset of the data and the method by which it is rendered. This includes manipulating the effects of image lighting, coloration, transparency and other visual characteristics of the underlying data.
  • the data tends to be very complex, as it usually consists of massive amount of geometrical entities at the display list or vertex array. Therefore, the construction time of a single frame tends to be very long (e.g., typically 0.5 sec for 20 million polygons), which in turn slows down the overall system performance.
  • the present invention is directed to a system for improving the parallelization of image processing, using one or more parallelization modes, wherein the image that is displayed on at least one computer screen by one or more Graphics
  • Processing Units which comprises: one or more software applications, for issuing graphic commands; one or more graphic libraries, for storing data used to implement the graphic commands; one or more Software Hub Drivers, for controlling a Hardware Hub, for interacting with the operation system of the computer and the graphic libraries, for performing real-time analysis of a data stream, from which frames of the image are generated, for determining the parallelization mode of each GPU, and for forwarding the data stream or a portion thereof to each GPU;
  • one or more GPU Drivers for allowing the GPUs to interact with the graphic libraries; and at least one I/O module for interconnecting between the Software module and the
  • Hardware Hub wherein, the Hardware Hub distributes between the GPUs, for each frame, graphic commands and the data stream or a portion thereof, according to their relative complexity within the image, and defines the complexity
  • the Software Hub Driver also composites a graphics output for display, using the outputs obtained from at least one GPU, while alternating, whenever required, the parallelization mode for the each frame.
  • the hardware hub comprises a compositing unit for composing a complete frame from processed portions of the data stream.
  • the hardware hub comprises a hub router for routing polygonal data, for routing graphic command stream, for routing pixel data and for routing the results of composition, while operating in the object division mode or in the image division mode or in the time division mode or in any combination thereof.
  • the hardware hub comprises a control unit for receiving commands from the Software Hub Driver within the I/O module.
  • the hardware hub comprises a memory unit for storing intermediate processing results of one or more GPUs and data required for composition and transferring the processed data for display.
  • the Software Hub Driver is capable of performing the following operations: interception of the graphic commands from the standard graphic library by means of the OS interface and utilities; forwarding and creating graphic commands to the GPU Driver by means of the
  • OS interface and utilities controlling the Hardware Hub, registry and installation operations by means of the OS interface and utilities: maintaining the consistency of graphic machine states across the GPUs, based on the input graphic commands stream, while using state monitoring;
  • the present invention is directed to a method for improving the parallelization of image processing, using one or more parallelization modes, wherein the image that is displayed on at least one computer screen by one or more Graphic Processing Units.
  • Software applications are provided for issuing graphic command and graphic libraries are provided for storing data used to implement the graphic commands.
  • a Software Hub Drivers is provided for controlling a Hardware Hub, for interacting with the operation system of the computer and the graphic libraries, for performing real-time analysis of a data stream, from which frames of the image are generated, for determining the parallelization mode of each GPU, and for forwarding the data stream or a portion thereof to each GPU.
  • GPU Drivers are provided for allowing the GPUs to interact with the graphic libraries and an I/O module is provided for interconnecting between the Software module and the Hardware Hub.
  • graphic commands and the data stream or a portion thereof are distributed between the GPUs for each frame by the Hardware Hub, according to their relative complexity within the image, wherein the complexity is defined by the Software Hub Driver.
  • the Software Hub Driver also composites a graphics output for display, using the outputs obtained from at least one GPU, while alternating, whenever required, the parallelization mode for the each frame.
  • the parallelization mode is an Object division parallelization mode
  • the following steps are performed: for each frame, generating a stream of graphic operations and polygonal data; marking the polygonal data and graphic commands by means of the Software Hub Driver for distribution between multiple GPUs; sending the marked data to the Hardware Hub; distributing the marked data via the Hub Router to the multiple GPUs; rendering the data by means of GPUs; retrieving the data from the Frame Buffers and forwarding the retrieved data to the compositing unit via the Hub Router; compositing the content of the Frame Buffers into a single Frame Buffer; and
  • Wfctenever the parallelization mode is an Image division parallelization mode
  • the following steps are performed: subdividing the screen to portions and assigning different viewports to GPUs by means of the Software Hub Driver; moving the entire polygonal data and graphic commands to the Hub Router;
  • each GPU receives the same data; rendering the data by means of GPUs; forwarding a portion of the content stored in the Frame Buffers to compositing unit in Hardware Hub for the complete image creation; and forwarding the image to at least one designated GPU for display.
  • the parallelization mode is a Time division parallelization mode
  • the following steps are performed: forwarding to each one of the multiple GPUs the entire amount of polygons for rendering; redirecting the entire polygonal data and graphic commands by means of Software Hub Driver to all GPUs, while alternating between them; rendering the data by means of GPUs; transferring rendered data from at least one GPU via the Hub Router; and
  • the distribution of polygons between multiple GPUs is performed by distributing blocks of data between multiple GPUs and by testing each graphic operation for blocking mode, in which one or more parallelization modes are carried out, thereafter.
  • the data is redirected in regular non-blocking path to at least one designated GPU, This process is repeated until a blocking operation is detected.
  • GPUs are synchronized by performing a flush operation in order to terminate rendering and clean up the internal pipeline in each GPU; performing a composition operation for merging the contents of the Frame Buffers into a single Frame Buffer and bytransmitting the single Frame Buffer back to all GPUs.
  • the composited complete frame is terminated at all GPUs, except one or more designated GPUs, whenever a Swap operation is detected and displaying the image by means of the one or more designated GPUs.
  • the same data is processed by all GPUs, as long as the blocking mode is active and the Swap operation is not detected, whenever the blocking mode is inactive, the designated data is further processed by multiple GPUs,.
  • Fig. 1 is a block diagram of a multiple GPU architecture system, according to an embodiment of the present invention
  • Fig. 2 is a block diagram of Hardware Hub components, according to an embodiment of the present invention
  • Fig. 3 is a block diagram of Object division parallelization mode, according to an embodiment of the present invention
  • Fig. 4 is a block diagram of Image division parallelization mode, according to an embodiment of the present invention
  • Fig. 5 is a block diagram of Time division parallelization mode, according to an embodiment of the present invention
  • Fig. 6 is a schematic block diagram of a possible integration of the Software Hub Driver into the operating system environment, according to an embodiment of the present invention
  • Fig. 1 is a block diagram of a multiple GPU architecture system, according to an embodiment of the present invention
  • Fig. 2 is a block diagram of Hardware Hub components, according to an embodiment of the present invention
  • Fig. 3 is a block diagram of Object division parallelization mode, according to an embodiment of the present invention
  • Fig. 4 is a block diagram of
  • FIG. 7 is a functional block diagram presenting the main tasks of the Software Hub Driver, according to an embodiment of the present invention
  • Fig. 8 is a flow chart presenting an process for distribution of the polygons between the multiple GPUs, according to an embodiment of the present invention
  • Fig. 9 discloses a sample configuration of the system, employing 8 GPUs, according to an embodiment of the present invention.
  • the current invention calls for the introduction of an extended PC graphic architecture including novel operational component, the 3-D pipeline Hub.
  • Fig. 1 presents multiple GPU architecture system 100, according to an embodiment of the present invention.
  • the hub 110 is located in a unique position on the PC bus, between the CPU (Central Processing Unit) and a cluster of GPUs 130.
  • the multiple graphic pipeline architecture as described in Fig. 1, consists of Software Application 121, Graphic Library 122, Software Hub Driver 123, GPU Driver 124, Hardware Hub 110, cluster of GPUs 130, and display(s) 140.
  • one of the GPUs is designated as a display unit. It should be noted, that it is possible to have more than one display unit, or include a display unit directly inside the Hardware Hub.
  • a display unit can drive multiple screens, as well.
  • the Hub mechanism consists of a Hardware Hub component 110, located on the PC bus between I/O (Input/Output) chipset 160, being a I/O module, and a cluster of GPUs 130, and a Software module comprising Software Hub Driver 123, executed by the PC.
  • I/O Input/Output
  • Software module comprising Software Hub Driver 123, executed by the PC.
  • the Hardware Hub 110 carries on at least the following action: distributes decomposed polygon stream and graphic commands between GPUs; composites graphics output for displaj ⁇ according to different parallel modes; makes cache of data; and alternates modes of parallelism.
  • the Software Hub Driver 123 besides controlling the Hardware Hub 110, also carries on at least the following actions: interacts with the OS (Operation System) and graphic library, such as OpenGL, DirectX; performs real-time analysis of the data stream; determines the parallelization mode; and decomposes the data and command stream.
  • OS Operaation System
  • graphic library such as OpenGL, DirectX
  • One advantage of this method is that the unique location of the Hardware Hub 110 allows it to control the graphic pipeline, while being transparent to the application 121.
  • Hardware Hub 110 allows it to control a graphic pipeline between the User Interface 150 and Display 140, while being transparent to the GPU.
  • Each GPU of the cluster keeps working as if it is the only graphic processor hooked on the I/O chipset 160.
  • Still another advantage of this method is that the unique location of the Hardware Hub 110 allows it to control the graphic pipeline for different parallelization modes: image division mode, time division mode or object division mode.
  • Hardware Hub 110 allows it to sense in real-time the varying parameters of application's load, such as polygon count, texture volume, human interaction, and to intelligently decide and carry on the current optimal parallelization method.
  • the display(s) 140 may be connected directly or indirectly to the Hardware Hub 110.
  • Control Unit 210 accepts proprietary commands from the Software Hub Driver over the bus, and accordingly controls the other units.
  • Hub Router 230 routs polygonal data and graphic command stream from left to right, routs pixel data from right to compositing unit, and routs compositing results to the right.
  • Compositing Unit 240 performs various compositing schemes according to parallelization mode.
  • Auxiliary Memory block 220 is used for storing intermediate processing results of one or more GPUs, data required for composition and transferring the processed data for display.
  • the Hardware Hub 110 utilizes its units according to parallelization modes: an Object division mode, an Image division mode, a Time division mode. These modes are adaptively handled by the Hardware Hub 110 according to application needs.
  • Fig. 3 discloses the operation of the Object division parallelization mode, according to an embodiment the present invention.
  • CPU executes the ' 3-D graphic application 310, which along with standard graphic library generate a stream of graphic operations and polygonal data. They are typically organized in data blocks either as Display List, Vertex Array or free polygons, which are polygons that are neither organized in Display List nor in Vertex Array.
  • the Software Hub Driver at step 320 marks the polygonal data and graphic commands for distribution between multiple GPUs, in a way that the overall load is balanced. The marked data is forwarded to Hardware Hub. At step 330 it is distributed via the Hub Router to multiple GPUs.
  • the Frame Buffers are retrieved and forwarded via the Hub Router to the compositing unit at step 350.
  • the frame buffers are composited to a single frame buffer, which is forwarded to the designated GPU for display.
  • the single frame buffer is displayed at step 360.
  • Fig. 4 discloses the operation of the Image division parallelization mode, according to an embodiment the present invention.
  • the Software Hub Driver assigns different viewports to GPUs in order to subdivide the screen between them.
  • the viewports aspects are set according to load balancing considerations, to keep the overall GPU load evenly balanced.
  • step 420 the entire polygonal data and graphic commands are moved to the Hub Router at Hardware Hub, and they are transmitted at step 430 to multiple GPUs. All GPUs receive the same data.
  • the partial frame buffers are brought to compositing unit in Hardware Hub for the full image creation at step 450, and then this image is moved out to designated GPU for display.
  • the full image is displayed at step 460.
  • Fig. 5 discloses the operation of the Time division parallelization mode, according to an embodiment the present invention.
  • time division the processing of each frame takes N frame time units, while N GPUs (or N clusters of GPUs) are participating.
  • the entire amount of polygons is forwarded to each GPU, for rendering.
  • the Software Hub Driver redirects the polygonal data and graphic commands at step 530 to a cluster of GPUs at a time, while alternating between them.
  • the data is transferred to the above cluster of GPUs via the Hub Router, rendered in the GPUs at step 540, and then the resulting frame buffer at step 550 is redirected via Hub Router to the designated GPU for display. All GPUs are coordinated by Software Hub Driver to create a continuous sequence of frames.
  • the resulting frame buffer is displayed at step 560.
  • the Hardware Hub competence is its scaling technology: Architecture and cluster of proprietary processes devoted to scale existing GPUs performance in PC based systems, by enabling the use of multiple GPUs in parallel on the level of chip, card or chip IP (Intellectual Property) core, and handling multiple bus paths between the CPU and GPU.
  • the technology achieves linear increase in performance. It- is invariant to a graphics vendor and also it is transparent to an application.
  • the graphic pipeline bottlenecks of vertex processing, fragment processing and bus transfer are completely and intelligently resolved. As bottlenecks may shift between frames, the Hardware Hub is designed with a smart real-time feedback system between the Control Unit 210, disclosed in Fig. 2, and Software Hub Driver 123, disclosed in Fig. 1, by means of the bus, utilizing the different parallelization modes to overcome different bottlenecks and maintain maximum performance at the frame level.
  • the Software Hub Driver is a software package residing in the PC and coexisting with computer's operating system, standard graphic library, application and Vendor's GPU Driver.
  • Fig. 6 is a schematic block diagram of a possible integration of the Software Hub Driver 630 into the operating system environment according to an embodiment the present invention.
  • graphic application block 610 there is standard graphic library block 620.
  • the Software Hub Driver 630 is located beneath the standard graphic library 620, intercepting the graphic command and data stream on the way to the Vendor's GPU Driver 640.
  • the Software Hub Driver 630 also controls the Hardware Hub 660.
  • Fig.7 is a functional block diagram presenting the main tasks of the Software Hub Driver, according to an embodiment the present invention.
  • OS interface and Utilities block 710 is responsible for interception of the graphic commands from the standard graphic library, forwarding and creating graphic commands to Vendor's GPU Driver, controlling the Hardware Hub, registry and installation, OS services and utilities.
  • State Monitoring block 720 is responsible for maintaining consistency of graphic machine states across the GPUs, based on the input graphic commands stream.
  • Application and graphic resources analysis block 730 is responsible for the application observation - estimating the type of graphic load and bottleneck in the current application graphic context, graphic resources (GPUs) load estimation for load balance based on graphic commands stream and time measurements, handling the feedback from GPUs in regard to load balancing.
  • Parallelism policy management block 740 is based on load analysis.
  • Parallelization modes which are the Object division mode, Image division mode and Time division mode, are combined together in order to achieve best performance and optimal load handling.
  • Parallelization policy is based on the analysis of the load, and it must preserve the state of the graphic system at all relevant GPUs across the electronic circuit or chip. For example, changing of a state by adding a new light source in the scene at some time point, must affect all subsequent polygons at different GPUs.
  • Parallelism policy management block 740 is responsible for the interpretation of the policy for specific manipulation in graphic functions.
  • Distributed graphic functions control block 750 is responsible for modification of graphic command and data stream based on the parallelization policy.
  • the decomposition and more importantly, the composition, must be accurate and efficient. Certain operations must be performed in the order they are submitted by the application. For example, in case of semi-transparency, the commands and potygon stream must keep a certain order for creating a correct graphic result.
  • the proposed decomposition process is performed by the Software Hub Driver.
  • CPU runs the 3-D graphic application, generating flow of graphic commands and data. They are typically organized in blocks, such as Display Lists or Vertex Arrays, stored in the system memory.
  • the Software Hub Driver running in the CPU, decomposes the set of scene polygons (or vertices). Their physical distribution is performed by the Hardware Hub.
  • the polygons are rendered in the GPU, while maintaining the resulting Frame Buffer in local memory. All FBs are transferred, via Hub Router, to compositing unit in Hardware Hub, to be merged into single FB. Finally, the composited FB is forwarded for display.
  • the Software Hub Driver carries out the following process of distribution of the polygons between the multiple GPUs. It is assumed, that the regular way the graphic application works, remains unchanged. Per frame, a typical application generates a stream of graphic calls that includes blocks of graphic data; each block consists of a list of geometric operations, such as single vertex operations or ' buffer based operations (vertex array). Typically, the decomposition process splits the data between GPUs preserving the blocks as basic data units. Geometric operations are attached to the block(s) of data, instructing the way the data is handled. A block is directed to designated GPUs. However, there are operations belonging to the group of Blocking Operations, such as Flush, Swap, Alpha blending, which affect the entire graphic system, setting the system to blocking mode.
  • Blocking operations are exceptional in that they require a composed valid FB data, thus in the parallel setting of the present invention, they have an effect on all GPUs. Therefore, whenever one of the Blocking operations is issued, all the GPUs must be synchronized. Each frame has at least 2 blocking operations: Flush and Swap, which terminate the frame.
  • Fig. 8 is a flow chart presenting the process for distribution of the polygons between the multiple GPUs, according to an embodiment the present invention.
  • the frame activity starts with distributing blocks of data between GPUs.
  • Each graphic operation is tested for blocking mode at step 820.
  • data is redirected to the designated GPU at the step 830. This loop is repeated until a blocking operation is detected.
  • all GPUs must be synchronized at step 840 by at least the following sequence: performing a flush operation in order to terminate rendering and clean up the internal pipeline (flushing) in GPU; performing a composition in order to merge the contents of FBs into a single FB; and - transmitting the contents of said single FB back to all GPUs, in order to create a common ground for continuation.
  • the Swap operation activates the double buffering mechanism, swapping the back and front color buffers. If Swap is detected at step 850, it means that a composited complete frame must be terminated at all GPU, except GPU0. All GPUs have the final composed contents of a FB designated to store said contents, but only the one connected to the screen (GPU0) displays the image at step 860.
  • Another case is operations that are applied globally to the scene and need to be broadcasted to all the GPUs. If one of the other blocking operations is identified, such as Alpha blending for transparency, then all GPUs are flushed as before at step 840, and merged into a common FB. This time the Swap operation is not detected (step 850), and therefore all GPUs have the same data, and as long as the blocking mode is on (step 870), all of them keep processing the same data (step 880). If the end of the block mode is detected at step 870, GPUs return working on designated data (step 830).
  • the present invention introduces a dynamic load-balancing technique that combines the object division method with the image division and time division methods in image and time domains, based on the load exhibits by previous processing stages. Combining all the three parallel methods into a unified framework dramatically increases the effectiveness of our invention.
  • Parallel processing is implemented by a pipeline, such as any common GPU allows the data to be processed in parallel, in time, image and object domains.
  • the processing performed on the graphical processing system either in parallel on multi-GPU or sequential, results in a sequence of complete raster images stored in a frame buffer, and sent to the display unit. These images are referred as frames in short.
  • a frame consists of fragments.
  • a fragment is an extended pixel stored in memory, which consists of attributes such as color, alpha, depth, stencil, etc.
  • each GPU is responsible for the production of a complete frame. In the other two domains, which are the image and object domains, all GPU operate in parallel to produce a single frame.
  • Screen-space parallel- processing implies that each GPU renders a subset of the fragments of each frame
  • object parallel-processing implies that the input data for each frame, in particular the geometric data (e.g., the polygon set representing the scene) is distributed between the multi GPUs.
  • Each one of three domains has advantages and disadvantages.
  • the effectiveness of each discipline is a dynamic function based on input data. Moreover, in many cases no single discipline is superior. In these cases a combination of two or even all the three disciplines ma ⁇ *- yield the most optimum results.
  • the present invention describes the specification for a parallel-processing system of three-dimensional data. It provides a novel process for object parallel-processing that consists of efficient decomposition of the data between the different GPU, and then the composition of the frames produced on the various GPUs into a final frame ready to be rendered.
  • the present invention provides a method to integrate all the three parallel modes dynamically into a unified framework to achieve maximum load balancing.
  • the set of available GPUs can be reconfigured based on the time it took to render the previous frames, and the bottlenecks exhibited during the processing of these frames.
  • Fig. 9 discloses a sample configuration of the system, employing 8 GPUs, according to an embodiment of the present invention. According to the above sample configuration, a balanced graphic application is assumed.
  • the GPUs are divided into two groups for time division parallelism. GPUs indexed with 1, 2, 3, and 4 are configured to process even frames and GPUs indexed with 5, 6, 7, and 8 are configured to process odd frames.
  • GPUs with the lower indexes (1,2 and 5,6 respectively) are configured to process half of the screen
  • the high- indexed GPU (3,4 and 7,8 respectively) are configured to process the other half.
  • GPUs indexed with 1, 3, 5 and 7 are fed with half of the objects
  • GPUs indexed with 2 , 4, 6 and 8 are fed with the other half of the objects.
  • the system detects that the bottlenecks exhibited in previous frames occur at the raster stage of the pipeline, it means that fragment processing dominates the time it takes to render the frames and that the configuration is imbalanced.
  • the GPUs are reconfigured, so that each GPU will render a quarter of the screen within the respective frame.
  • the original partition for time division, between GPUs 1,2,3,4 and between 5,6,7,8 still holds, but GPU 2 and GPU 5 are configured to render the first quarter of screen in even and odd frames respectively.
  • GPUs are reconfigured, so that each GPU will process a quarter of the geometrical data within the respective frame. That is, GPU 3 and GPU 5 are configured to process the first quarter of the polygons in even and odd frames respectively.
  • any combination between the parallel modes can be scheduled to evenly balance the graphic load.
  • the parallelization process between all GPUs may be based on an object division mode or image division mode or time division mode or any combination thereof in order to optimize the processing performance of each frame.

Abstract

Method and system for improving the parallelization of image processing, using one or more parallelization modes, wherein the4 image that is displayed on at least one computer screen by one or more Graphics Processing Units (GPUs) (130). Software applications (121) are provided for issuing graphics command and graphics libraries (122) are provided for storing data used to implement the graphics commands. A Software Hub Drivers (123) is provided for controlling a Hardware Hub (110), for performing real-time analysis of a data stream, from which frames of the image are generated, for determining the parallelization mode of each GPU, and for forwarding the data stream or a portion thereof to each GPU. GPU Drivers (124) are provided for allowing the GPUs to interact with the graphics libraries and an I/O module (160) is provided for interconnecting between the Software module and the Hardware Hub.

Description

METHOD AND SYSTEM FOR MULTIPLE 3-D GRAPHIC PIPELINE OVER A PC BUS
Field of the Invention
The present invention relates to a method and system for 3-D (three- dimensional) multiple graphic processing. More particularly, the invention relates to a method and system for improving the parallelization of image processing by Graphic Processing, Units (GPUs), based on unified framework of three parallelization methods, which are time division, image division and object division methods.
Definitions. Acronyms and Abbreviations
Throughout this specification, the following definitions are employed:
GPU: GPU (Graphic Processing Unit) like the CPU (Central Processing Unit), a GPU is a single-chip processor which is used primarily for computing 3-D functions. This includes tasks such as, lighting effects, object transformations, and 3-D motion. These are mathematically-intensive tasks, which otherwise, would put quite a strain on the CPU, but since the specialized GPU can handle most of the 3-D calculations, it helps the computer to perform these tasks more efficiently, and, of course, faster.
Polygon: Polygons in 3-D graphics are two-dimensional primitives, allowing generating and displaying of 3-D complex graphical objects. The polygons are the faces of the object and are composed from N vertices. Actually, a polygon is a closed plane figure, bounded by three or more line segments.
Frame Buffer: a Frame Buffer (FB) is a buffer that stores the contents of an image, pixel by pixel. Generally, the portion of memory is reserved for holding the complete bit-mapped image that is sent to the monitor, for display. Typically the frame buffer is stored in the memory chips on the video adapter. In some instances, however, the video chipset is integrated into the motherboard design, and the frame buffer is stored in the general main memory.
Object compositing unit: performs re-composition of multiple three- dimensional rasters into final image. The merged data is resolved for the closest pixel to the viewer in 3-D space, based on the depth value of pixels. The new method, based on autonomous associative decision, allows the use of multiple GPUs for any frame complexity.
Display list: a Display List is a description of the 3-D scene through a list of graphic primitives, such as polygons and attributes. The display list provides intermediate image storage for quick image retrieval.
Vertex array: a Vertex Array is an array of vertices describing the 3-D scene. A Vertex Array provides intermediate image storage for quick image retrieval.
Alpha blending: Alpha blending controls the way in which the graphic information is displayed, such as levels of transparency, or opacity.
Background of the Invention
The three dimensional graphic pipeline architecture breaks-down into segmented stages of CPU, Bus, GPU vertex processing and GPU fragment (pixel) processing. A given pipeline is only as strong as the weakest link of one of the above stages, thus the main bottleneck determines the overall throughput. Enhancing performance is all that required for reducing or eliminating bottlenecks. The major bottleneck strongly depends on the application. Extreme cases are CAD-like (Computer Aided Design) applications, characterized by an abundance of polygons (vertices), vs. video- game applications having a small polygon count but intensive fragment activity (e.g., texturing). The first class suffers from vertex processing bottlenecks, while the second class suffers from fragment bottlenecks. Both are frequently jammed over the PC bus. Many applications have mixed characteristics, where bottlenecks may randomly alternate between extremes, on a single frame basis.
The only way to improve the performance of the GPU is by means of parallelizing multiple GPUs according to one of the bottleneck solving methods. There are two predominant methods for rendering graphic data with multiple GPUs. These methods include time division (time domain composition), in which each GPU renders the next successive frame, and image division (screen space composition), in which each GPU renders a subset of the pixels of each frame. The third one, much less popular, is the object division (polygon decomposition) method.
In the time division method each GPU renders the next successive frame. It has the disadvantage of having each GPU render an entire frame. Thus, the speed at which each frame is rendered is limited to the rendering rate of a single GPU. While multiple GPUs enable a higher frame rate, a delay can be imparted in the response time (latency) of the system to a user's input. This occurs because, while at any given time, only one GPU is engaged in displaying a rendered frame, each of the GPUs is in the process of rendering one of a series of frames in a sequence. To maintain the high frame rate, the system delays the user's input until the specific GPU, which first received the signal cycles through the sequence, is again engaged in displa3>ing its rendered frame. In practical applications, this condition serves to limit the number of GPUs that are used in a system. With large data sets, there is another bottleneck, due to the fact that each GPU must be able to access all the data. This requires either maintaining multiple copy operations of large data sets or possible conflicts in accessing the single copy operation.
Image division method splits the screen between N GPUs, such that each one displays 1/N of the image. The entire polygon set is transferred to each GPU for processing, however, the pixel processing is significantly reduced to the window size. Image division has no latency issues, but it has a similar bottleneck with large data sets, since each GPU must examine the entire database to determine which graphic elements fall within the portion of the screen allocated to said GPU. Image division method suits applications with intensive pixel processing.
Object division method is based on distribution of data subsets between multiple GPUs. The data subsets are rendered in the GPU pipeline, and converted to Frame Buffer (FB) of fragments (sub-image pixels). The multiple FB's sub-images have to be merged (composited) to generate the final image to be displayed. Object division delivers parallel rendering on the level of a single frame of very complex data consisting of large amount of polygons. The input data is decomposed in the polygon level and re-composed in the pixel level. A proprietary driver intelligently distributes data streams, which are generated by the application, between all GPUs. The rasters, generated by the GPUs, are composited into final raster, and moved to the display. The object division method well suits applications that need to render a vast amount of geometrical data. Typically, these are CAD, Digital Content Creation, and comparable visual simulation applications, considered as "viewers," meaning that the data has been pre-designed such that their three-dimensional positions in space are not under the interactive control of the user. However, the user does have interactive control over the viewer's position, the direction of view, and the scale of the graphic data. The user also may have control over the selection of a subset of the data and the method by which it is rendered. This includes manipulating the effects of image lighting, coloration, transparency and other visual characteristics of the underlying data.
In above applications, the data tends to be very complex, as it usually consists of massive amount of geometrical entities at the display list or vertex array. Therefore, the construction time of a single frame tends to be very long (e.g., typically 0.5 sec for 20 million polygons), which in turn slows down the overall system performance.
Therefore, there is a need to provide a system which can guarantee the best system performance, being exposed to high traffic over the PC (Personal Computer) Bus.
It is an object of the present invention to provide an amplified strength of the GPU by means of parallelizing multiple GPUs.
It is another object of the present invention to provide a system, wherein the construction time of a single frame does not slow down the overall system response.
It is still another object of the present invention to provide a system and method, wherein the graphic pipeline bottlenecks of vertex processing and fragment processing are transparently and intelligently resolved.
It is still a further object of the present invention to provide a system and method that has high scalability and unlimited scene complexity.
It is still a further object of the present invention to provide a process overcoming difficulties that are imposed by the data decomposition, which is partition of data and graphic commands between GPUs. It is still a further object of the present invention to provide a method and for an intelligent decomposition of data and graphic commands, preserving the basic features of graphic libraries as state machines and complying with graphic standards.
Other objects and advantages of the invention will become apparent as the description proceeds.
Summary of the Invention
The present invention is directed to a system for improving the parallelization of image processing, using one or more parallelization modes, wherein the image that is displayed on at least one computer screen by one or more Graphic
Processing Units, which comprises: one or more software applications, for issuing graphic commands; one or more graphic libraries, for storing data used to implement the graphic commands; one or more Software Hub Drivers, for controlling a Hardware Hub, for interacting with the operation system of the computer and the graphic libraries, for performing real-time analysis of a data stream, from which frames of the image are generated, for determining the parallelization mode of each GPU, and for forwarding the data stream or a portion thereof to each GPU;
one or more GPU Drivers, for allowing the GPUs to interact with the graphic libraries; and at least one I/O module for interconnecting between the Software module and the
Hardware Hub, wherein, the Hardware Hub distributes between the GPUs, for each frame, graphic commands and the data stream or a portion thereof, according to their relative complexity within the image, and defines the complexity The Software Hub Driver also composites a graphics output for display, using the outputs obtained from at least one GPU, while alternating, whenever required, the parallelization mode for the each frame.
Parallelization is based on an object division mode or on an image division mode or on a time division mode or on any combination thereof. The hardware hub comprises a compositing unit for composing a complete frame from processed portions of the data stream. The hardware hub comprises a hub router for routing polygonal data, for routing graphic command stream, for routing pixel data and for routing the results of composition, while operating in the object division mode or in the image division mode or in the time division mode or in any combination thereof. The hardware hub comprises a control unit for receiving commands from the Software Hub Driver within the I/O module. The hardware hub comprises a memory unit for storing intermediate processing results of one or more GPUs and data required for composition and transferring the processed data for display.
Preferably, the Software Hub Driver is capable of performing the following operations: interception of the graphic commands from the standard graphic library by means of the OS interface and utilities; forwarding and creating graphic commands to the GPU Driver by means of the
OS interface and utilities; controlling the Hardware Hub, registry and installation operations by means of the OS interface and utilities: maintaining the consistency of graphic machine states across the GPUs, based on the input graphic commands stream, while using state monitoring;
estimating the type of graphic load and overload in the executed application graphic context, while using application and graphic resources analysis; load estimation of the GPUs load balance based on graphic commands stream and time measurements, while using application and graphic resources analysis;
adjusting the load distribution between GPUs according to feedback received from each GPU regarding the load balance, while using application and graphic resources analysis; performing manipulation in graphic functions according to the current parallelization mode; and controlling the distributed graphic functions, while modifying the graphic commands and the data stream according to the current parallelization mode.
The present invention is directed to a method for improving the parallelization of image processing, using one or more parallelization modes, wherein the image that is displayed on at least one computer screen by one or more Graphic Processing Units. Software applications are provided for issuing graphic command and graphic libraries are provided for storing data used to implement the graphic commands. A Software Hub Drivers is provided for controlling a Hardware Hub, for interacting with the operation system of the computer and the graphic libraries, for performing real-time analysis of a data stream, from which frames of the image are generated, for determining the parallelization mode of each GPU, and for forwarding the data stream or a portion thereof to each GPU. GPU Drivers are provided for allowing the GPUs to interact with the graphic libraries and an I/O module is provided for interconnecting between the Software module and the Hardware Hub. graphic commands and the data stream or a portion thereof are distributed between the GPUs for each frame by the Hardware Hub, according to their relative complexity within the image, wherein the complexity is defined by the Software Hub Driver. The Software Hub Driver also composites a graphics output for display, using the outputs obtained from at least one GPU, while alternating, whenever required, the parallelization mode for the each frame.
Whenever the parallelization mode is an Object division parallelization mode, the following steps are performed: for each frame, generating a stream of graphic operations and polygonal data; marking the polygonal data and graphic commands by means of the Software Hub Driver for distribution between multiple GPUs; sending the marked data to the Hardware Hub; distributing the marked data via the Hub Router to the multiple GPUs; rendering the data by means of GPUs; retrieving the data from the Frame Buffers and forwarding the retrieved data to the compositing unit via the Hub Router; compositing the content of the Frame Buffers into a single Frame Buffer; and
forwarding the content of the single Frame Buffer to at least one designated GPU for display.
Wfctenever the parallelization mode is an Image division parallelization mode, the following steps are performed: subdividing the screen to portions and assigning different viewports to GPUs by means of the Software Hub Driver; moving the entire polygonal data and graphic commands to the Hub Router;
transmitting the entire polygonal data and graphic commands to GPUs, wherein each GPU receives the same data; rendering the data by means of GPUs; forwarding a portion of the content stored in the Frame Buffers to compositing unit in Hardware Hub for the complete image creation; and forwarding the image to at least one designated GPU for display.
Whenever the parallelization mode is a Time division parallelization mode, the following steps are performed: forwarding to each one of the multiple GPUs the entire amount of polygons for rendering; redirecting the entire polygonal data and graphic commands by means of Software Hub Driver to all GPUs, while alternating between them; rendering the data by means of GPUs; transferring rendered data from at least one GPU via the Hub Router; and
redirecting the resulting content of the Frame Buffer via Hub Router to at least one designated GPU for display.
The distribution of polygons between multiple GPUs is performed by distributing blocks of data between multiple GPUs and by testing each graphic operation for blocking mode, in which one or more parallelization modes are carried out, thereafter. The data is redirected in regular non-blocking path to at least one designated GPU, This process is repeated until a blocking operation is detected. Then GPUs are synchronized by performing a flush operation in order to terminate rendering and clean up the internal pipeline in each GPU; performing a composition operation for merging the contents of the Frame Buffers into a single Frame Buffer and bytransmitting the single Frame Buffer back to all GPUs. Then the composited complete frame is terminated at all GPUs, except one or more designated GPUs, whenever a Swap operation is detected and displaying the image by means of the one or more designated GPUs. the same data is processed by all GPUs, as long as the blocking mode is active and the Swap operation is not detected, whenever the blocking mode is inactive, the designated data is further processed by multiple GPUs,. Brief Description of the Drawings
In the drawings: Fig. 1 is a block diagram of a multiple GPU architecture system, according to an embodiment of the present invention; Fig. 2 is a block diagram of Hardware Hub components, according to an embodiment of the present invention; Fig. 3 is a block diagram of Object division parallelization mode, according to an embodiment of the present invention; Fig. 4 is a block diagram of Image division parallelization mode, according to an embodiment of the present invention; Fig. 5 is a block diagram of Time division parallelization mode, according to an embodiment of the present invention; Fig. 6 is a schematic block diagram of a possible integration of the Software Hub Driver into the operating system environment, according to an embodiment of the present invention; Fig. 7 is a functional block diagram presenting the main tasks of the Software Hub Driver, according to an embodiment of the present invention; Fig. 8 is a flow chart presenting an process for distribution of the polygons between the multiple GPUs, according to an embodiment of the present invention; and Fig. 9 discloses a sample configuration of the system, employing 8 GPUs, according to an embodiment of the present invention.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated between the figures to indicate corresponding or analogous elements.
Detailed Description of the Preferred Embodiments
The Multiple 3-D Graphic Pipeline
The current invention calls for the introduction of an extended PC graphic architecture including novel operational component, the 3-D pipeline Hub.
Fig. 1 presents multiple GPU architecture system 100, according to an embodiment of the present invention. The hub 110 is located in a unique position on the PC bus, between the CPU (Central Processing Unit) and a cluster of GPUs 130. The multiple graphic pipeline architecture, as described in Fig. 1, consists of Software Application 121, Graphic Library 122, Software Hub Driver 123, GPU Driver 124, Hardware Hub 110, cluster of GPUs 130, and display(s) 140. Usually, one of the GPUs is designated as a display unit. It should be noted, that it is possible to have more than one display unit, or include a display unit directly inside the Hardware Hub. A display unit can drive multiple screens, as well.
The Hub mechanism consists of a Hardware Hub component 110, located on the PC bus between I/O (Input/Output) chipset 160, being a I/O module, and a cluster of GPUs 130, and a Software module comprising Software Hub Driver 123, executed by the PC.
The Hardware Hub 110 carries on at least the following action: distributes decomposed polygon stream and graphic commands between GPUs; composites graphics output for displaj^ according to different parallel modes; makes cache of data; and alternates modes of parallelism.
The Software Hub Driver 123, besides controlling the Hardware Hub 110, also carries on at least the following actions: interacts with the OS (Operation System) and graphic library, such as OpenGL, DirectX; performs real-time analysis of the data stream; determines the parallelization mode; and decomposes the data and command stream.
One advantage of this method is that the unique location of the Hardware Hub 110 allows it to control the graphic pipeline, while being transparent to the application 121. The application 121, along with Graphic Library 122, such as OpenGL, keeps working as it was a single GPU.
Another advantage of this method is that the unique location of the Hardware Hub 110 allows it to control a graphic pipeline between the User Interface 150 and Display 140, while being transparent to the GPU. Each GPU of the cluster keeps working as if it is the only graphic processor hooked on the I/O chipset 160.
Still another advantage of this method is that the unique location of the Hardware Hub 110 allows it to control the graphic pipeline for different parallelization modes: image division mode, time division mode or object division mode.
Further advantage of this method is that the unique location of the Hardware Hub 110 allows it to sense in real-time the varying parameters of application's load, such as polygon count, texture volume, human interaction, and to intelligently decide and carry on the current optimal parallelization method.
It should be noted that according to all embodiments of the present invention, the display(s) 140 may be connected directly or indirectly to the Hardware Hub 110.
Reference is now made to Fig. 2, which discloses the components of the Hardware Hub 110, according to an embodiment the present invention. Control Unit 210, accepts proprietary commands from the Software Hub Driver over the bus, and accordingly controls the other units. Hub Router 230 routs polygonal data and graphic command stream from left to right, routs pixel data from right to compositing unit, and routs compositing results to the right. Compositing Unit 240 performs various compositing schemes according to parallelization mode. Auxiliary Memory block 220 is used for storing intermediate processing results of one or more GPUs, data required for composition and transferring the processed data for display.
The Hardware Hub 110 utilizes its units according to parallelization modes: an Object division mode, an Image division mode, a Time division mode. These modes are adaptively handled by the Hardware Hub 110 according to application needs.
Fig. 3 discloses the operation of the Object division parallelization mode, according to an embodiment the present invention. CPU executes the ' 3-D graphic application 310, which along with standard graphic library generate a stream of graphic operations and polygonal data. They are typically organized in data blocks either as Display List, Vertex Array or free polygons, which are polygons that are neither organized in Display List nor in Vertex Array. The Software Hub Driver at step 320 marks the polygonal data and graphic commands for distribution between multiple GPUs, in a way that the overall load is balanced. The marked data is forwarded to Hardware Hub. At step 330 it is distributed via the Hub Router to multiple GPUs. After the rendering process in GPUs at step 340 is accomplished, the Frame Buffers are retrieved and forwarded via the Hub Router to the compositing unit at step 350. Here the frame buffers are composited to a single frame buffer, which is forwarded to the designated GPU for display. The single frame buffer is displayed at step 360.
Fig. 4 discloses the operation of the Image division parallelization mode, according to an embodiment the present invention. In this mode the Software Hub Driver assigns different viewports to GPUs in order to subdivide the screen between them. The viewports aspects are set according to load balancing considerations, to keep the overall GPU load evenly balanced. In step 420, the entire polygonal data and graphic commands are moved to the Hub Router at Hardware Hub, and they are transmitted at step 430 to multiple GPUs. All GPUs receive the same data. After rendering at step 440, the partial frame buffers are brought to compositing unit in Hardware Hub for the full image creation at step 450, and then this image is moved out to designated GPU for display. The full image is displayed at step 460.
Fig. 5 discloses the operation of the Time division parallelization mode, according to an embodiment the present invention. In time division the processing of each frame takes N frame time units, while N GPUs (or N clusters of GPUs) are participating. The entire amount of polygons is forwarded to each GPU, for rendering. At each frame time unit, the Software Hub Driver redirects the polygonal data and graphic commands at step 530 to a cluster of GPUs at a time, while alternating between them. The data is transferred to the above cluster of GPUs via the Hub Router, rendered in the GPUs at step 540, and then the resulting frame buffer at step 550 is redirected via Hub Router to the designated GPU for display. All GPUs are coordinated by Software Hub Driver to create a continuous sequence of frames. The resulting frame buffer is displayed at step 560.
The Hardware Hub competence is its scaling technology: Architecture and cluster of proprietary processes devoted to scale existing GPUs performance in PC based systems, by enabling the use of multiple GPUs in parallel on the level of chip, card or chip IP (Intellectual Property) core, and handling multiple bus paths between the CPU and GPU. The technology achieves linear increase in performance. It- is invariant to a graphics vendor and also it is transparent to an application. In the present invention, the graphic pipeline bottlenecks of vertex processing, fragment processing and bus transfer are completely and intelligently resolved. As bottlenecks may shift between frames, the Hardware Hub is designed with a smart real-time feedback system between the Control Unit 210, disclosed in Fig. 2, and Software Hub Driver 123, disclosed in Fig. 1, by means of the bus, utilizing the different parallelization modes to overcome different bottlenecks and maintain maximum performance at the frame level.
The Software Hub Driver
The Software Hub Driver is a software package residing in the PC and coexisting with computer's operating system, standard graphic library, application and Vendor's GPU Driver. Fig. 6 is a schematic block diagram of a possible integration of the Software Hub Driver 630 into the operating system environment according to an embodiment the present invention. Next to graphic application block 610 there is standard graphic library block 620. The Software Hub Driver 630 is located beneath the standard graphic library 620, intercepting the graphic command and data stream on the way to the Vendor's GPU Driver 640. The Software Hub Driver 630 also controls the Hardware Hub 660. Fig.7 is a functional block diagram presenting the main tasks of the Software Hub Driver, according to an embodiment the present invention. OS interface and Utilities block 710 is responsible for interception of the graphic commands from the standard graphic library, forwarding and creating graphic commands to Vendor's GPU Driver, controlling the Hardware Hub, registry and installation, OS services and utilities. State Monitoring block 720 is responsible for maintaining consistency of graphic machine states across the GPUs, based on the input graphic commands stream. Application and graphic resources analysis block 730 is responsible for the application observation - estimating the type of graphic load and bottleneck in the current application graphic context, graphic resources (GPUs) load estimation for load balance based on graphic commands stream and time measurements, handling the feedback from GPUs in regard to load balancing. Parallelism policy management block 740 is based on load analysis. All parallelization modes, which are the Object division mode, Image division mode and Time division mode, are combined together in order to achieve best performance and optimal load handling. Parallelization policy is based on the analysis of the load, and it must preserve the state of the graphic system at all relevant GPUs across the electronic circuit or chip. For example, changing of a state by adding a new light source in the scene at some time point, must affect all subsequent polygons at different GPUs. Parallelism policy management block 740 is responsible for the interpretation of the policy for specific manipulation in graphic functions. Distributed graphic functions control block 750 is responsible for modification of graphic command and data stream based on the parallelization policy.
Object Division Decomposition Process
Object division is a well known concept, but data decomposition (partition of data and graphic commands between GPUs), while being also a known concept, has not been applied yet effectively, as it imposes various great difficulties. These difficulties are handled successfully by a proposed process and its implementation according to the present invention.
The decomposition, and more importantly, the composition, must be accurate and efficient. Certain operations must be performed in the order they are submitted by the application. For example, in case of semi-transparency, the commands and potygon stream must keep a certain order for creating a correct graphic result.
Intelligent decomposition of data and graphic commands is needed, preserving the basic features of graphic libraries as state machines, and complying with the graphic standards. The proposed decomposition process, according to the present invention, is performed by the Software Hub Driver. CPU runs the 3-D graphic application, generating flow of graphic commands and data. They are typically organized in blocks, such as Display Lists or Vertex Arrays, stored in the system memory.
According to the present invention, the Software Hub Driver, running in the CPU, decomposes the set of scene polygons (or vertices). Their physical distribution is performed by the Hardware Hub.
The polygons are rendered in the GPU, while maintaining the resulting Frame Buffer in local memory. All FBs are transferred, via Hub Router, to compositing unit in Hardware Hub, to be merged into single FB. Finally, the composited FB is forwarded for display.
The Software Hub Driver carries out the following process of distribution of the polygons between the multiple GPUs. It is assumed, that the regular way the graphic application works, remains unchanged. Per frame, a typical application generates a stream of graphic calls that includes blocks of graphic data; each block consists of a list of geometric operations, such as single vertex operations or' buffer based operations (vertex array). Typically, the decomposition process splits the data between GPUs preserving the blocks as basic data units. Geometric operations are attached to the block(s) of data, instructing the way the data is handled. A block is directed to designated GPUs. However, there are operations belonging to the group of Blocking Operations, such as Flush, Swap, Alpha blending, which affect the entire graphic system, setting the system to blocking mode. Blocking operations are exceptional in that they require a composed valid FB data, thus in the parallel setting of the present invention, they have an effect on all GPUs. Therefore, whenever one of the Blocking operations is issued, all the GPUs must be synchronized. Each frame has at least 2 blocking operations: Flush and Swap, which terminate the frame.
Fig. 8 is a flow chart presenting the process for distribution of the polygons between the multiple GPUs, according to an embodiment the present invention. The frame activity starts with distributing blocks of data between GPUs. Each graphic operation is tested for blocking mode at step 820. In a regular (non-blocking) path, data is redirected to the designated GPU at the step 830. This loop is repeated until a blocking operation is detected.
When the blocking operation is detected, all GPUs must be synchronized at step 840 by at least the following sequence: performing a flush operation in order to terminate rendering and clean up the internal pipeline (flushing) in GPU; performing a composition in order to merge the contents of FBs into a single FB; and - transmitting the contents of said single FB back to all GPUs, in order to create a common ground for continuation. The Swap operation activates the double buffering mechanism, swapping the back and front color buffers. If Swap is detected at step 850, it means that a composited complete frame must be terminated at all GPU, except GPU0. All GPUs have the final composed contents of a FB designated to store said contents, but only the one connected to the screen (GPU0) displays the image at step 860.
Another case is operations that are applied globally to the scene and need to be broadcasted to all the GPUs. If one of the other blocking operations is identified, such as Alpha blending for transparency, then all GPUs are flushed as before at step 840, and merged into a common FB. This time the Swap operation is not detected (step 850), and therefore all GPUs have the same data, and as long as the blocking mode is on (step 870), all of them keep processing the same data (step 880). If the end of the block mode is detected at step 870, GPUs return working on designated data (step 830).
Adaptive handling of graphic load by combining three division methods In addition, the present invention introduces a dynamic load-balancing technique that combines the object division method with the image division and time division methods in image and time domains, based on the load exhibits by previous processing stages. Combining all the three parallel methods into a unified framework dramatically increases the effectiveness of our invention.
Parallel processing is implemented by a pipeline, such as any common GPU allows the data to be processed in parallel, in time, image and object domains. The processing performed on the graphical processing system, either in parallel on multi-GPU or sequential, results in a sequence of complete raster images stored in a frame buffer, and sent to the display unit. These images are referred as frames in short. A frame consists of fragments. A fragment is an extended pixel stored in memory, which consists of attributes such as color, alpha, depth, stencil, etc. When processing is performed in parallel in the time domain, typically each GPU is responsible for the production of a complete frame. In the other two domains, which are the image and object domains, all GPU operate in parallel to produce a single frame. Screen-space parallel- processing implies that each GPU renders a subset of the fragments of each frame, and object parallel-processing implies that the input data for each frame, in particular the geometric data (e.g., the polygon set representing the scene) is distributed between the multi GPUs.
Each one of three domains (time, image and object domains) has advantages and disadvantages. The effectiveness of each discipline is a dynamic function based on input data. Moreover, in many cases no single discipline is superior. In these cases a combination of two or even all the three disciplines ma}*- yield the most optimum results.
The present invention describes the specification for a parallel-processing system of three-dimensional data. It provides a novel process for object parallel-processing that consists of efficient decomposition of the data between the different GPU, and then the composition of the frames produced on the various GPUs into a final frame ready to be rendered.
The present invention provides a method to integrate all the three parallel modes dynamically into a unified framework to achieve maximum load balancing. At each frame, the set of available GPUs can be reconfigured based on the time it took to render the previous frames, and the bottlenecks exhibited during the processing of these frames. Fig. 9 discloses a sample configuration of the system, employing 8 GPUs, according to an embodiment of the present invention. According to the above sample configuration, a balanced graphic application is assumed. The GPUs are divided into two groups for time division parallelism. GPUs indexed with 1, 2, 3, and 4 are configured to process even frames and GPUs indexed with 5, 6, 7, and 8 are configured to process odd frames. Within each group, two GPU subgroups are set for image division: the GPUs with the lower indexes (1,2 and 5,6 respectively) are configured to process half of the screen, and the high- indexed GPU (3,4 and 7,8 respectively) are configured to process the other half. Finally, for the object division, GPUs indexed with 1, 3, 5 and 7 are fed with half of the objects, and GPUs indexed with 2 , 4, 6 and 8 are fed with the other half of the objects.
If at some point the system detects that the bottlenecks exhibited in previous frames occur at the raster stage of the pipeline, it means that fragment processing dominates the time it takes to render the frames and that the configuration is imbalanced. At that point the GPUs are reconfigured, so that each GPU will render a quarter of the screen within the respective frame. The original partition for time division, between GPUs 1,2,3,4 and between 5,6,7,8 still holds, but GPU 2 and GPU 5 are configured to render the first quarter of screen in even and odd frames respectively. GPUs 1 and GPU 6 - the second quarter, GPU 4 and GPU 7 - the third quarter, and GPU 3 and GPU 8 - the forth quarter. No object division is implied.
In addition, if at some point the system detects that the bottleneck exhibited in previous frames occurs at the geometry stage of the pipe, the GPUs are reconfigured, so that each GPU will process a quarter of the geometrical data within the respective frame. That is, GPU 3 and GPU 5 are configured to process the first quarter of the polygons in even and odd frames respectively. GPU 1 and GPU 7 - the second quarter, GPU 4 and GPU 6 - the third quarter and GPU 2 and GPU 8 - the forth quarter. No image division is implied.
It should be noted, that taking 8 GPUs is sufficient in order to combine all three parallel modes, which are time, image and object division modes, per frame. Taking the number of GPUs larger than 8, also enables combining all 3 modes, but in a non-symmetric fashion. The flexibility also exists in frame count in a time division cycle. In the above example, the cluster of 8 GPUs was broken down into the two groups, each group handling a frame. However, it is possible to extend the number of frames in a time division mode to a sequence, which is longer than 2 frames, for example 3 or 4 frames.
Taking a smaller number of GPUs still allows the combination of the parallel modes, however the combination of two modes only. For example, taking only 4 GPUs enables to combine image and object division modes, without time division mode. It is clearly understood from Fig. 9, while taking the group of GPUl, GPU2, GPU3 and GPU4, which is the left cluster. Similarly, the group of GPUl, GPU2, GPU5 and GPU6, which is the upper cluster, employs both object and time division modes. Finally, the configuration of the group of GPU2, GPU4, GPU5 and GPU6, which is the middle cluster, employs image and time division modes.
It should be noted, that similarly to the above embodiments, any combination between the parallel modes can be scheduled to evenly balance the graphic load.
It also should be noted, that according to the present invention, the parallelization process between all GPUs may be based on an object division mode or image division mode or time division mode or any combination thereof in order to optimize the processing performance of each frame. While some embodiments of the invention have been described by way of illustration, it will be apparent that the invention can be put into practice with man3^ modifications, variations and adaptations, and with the use of numerous equivalents or alternative solutions that are within the scope of persons skilled in the art, without departing from the spirit of the invention or exceeding the scope of the claims.

Claims

Claims 1. A system for improving the parallelization of image processing, using one or more parallelization modes, wherein said image that is displayed on at least one computer screen by one or more Graphic Processing Units, comprising at least: a. one or more software applications, for issuing graphic commands; b. one or more graphic libraries, for storing data used to implement said graphic commands; c. one or more Software Hub Drivers, for controlling a Hardware Hub, for interacting with the operation system of said computer and said graphic libraries, for performing real-time analysis of a data stream, from which frames of said image are generated, for determining the parallelization mode of each GPU, and for forwarding said data stream or a portion thereof to each GPU; d. one or more GPU Drivers, for allowing said GPUs to interact with said graphic libraries; and e. at least one I/O module for interconnecting between said Software module and said Hardware Hub, wherein, said Hardware Hub distributes, for each frame, between said GPUs, graphic commands and said data stream or a portion thereof, according to their relative complexity within said image, said complexity is defined by said Software Hub Driver; and composites a graphics output for display, using the outputs obtained from at least one GPU, while alternating, whenever required, said parallelization mode for said each frame.
2. System according to claim 1, wherein the parallelization is based on an object division mode or on an image division mode or on a time division mode or on any combination thereof.
3. System according to claim 1, wherein the hardware hub comprises at least one compositing unit at least for composing a complete frame from processed portions of the data stream.
4. System according to claim 2, wherein the hardware hub comprises at least one hub router for routing polygonal data, for routing graphic command stream, for routing pixel data and for routing the results of composition, while operating in the object division mode or in the image division mode or in the time division mode or in any combination thereof.
5. System according to claim 1, wherein the hardware hub comprises at least one control unit for receiving commands from the Software Hub Driver within the I/O module.
6. System according to claim 1, wherein the hardware hub comprises a memory unit for storing intermediate processing results of one or more GPUs and data required for composition and transferring the processed data for display.
7. System according to claim 1, wherein the Software Hub Driver is capable of performing the following operations: a. interception of the graphic commands from the standard graphic library by means of the OS interface and utilities; b. forwarding and creating graphic commands to the GPU Driver by means of the OS interface and utilities; c. controlling the Hardware Hub, registry and installation operations by means of the OS interface and utilities: d. maintaining the consistency of graphic machine states across the GPUs, based on the input graphic commands stream, while using state monitoring; e. estimating the type of graphic load and overload in the executed application graphic context, while using application and graphic resources analysis; f. load estimation of the GPUs load balance based on graphic commands stream and time measurements, while using application and graphic resources analysis; g. adjusting the load distribution between GPUs according to feedback received from each GPU regarding said load balance, while using application and graphic resources analysis; h. performing manipulation in graphic functions according to the current parallelization mode; and i. controlling the distributed graphic functions, while modifying said graphic commands and said data stream according to said current parallelization mode.
8. A method for improving the parallelization of image processing, using one or more parallelization modes, wherein said image that is displayed on at least one computer screen by one or more Graphic Processing Units, comprising at least: a. providing one or more software applications, for issuing graphic commands; b. providing one or more graphic libraries, for storing data used to implement said graphic commands; c. providing one or more Software Hub Drivers, for controlling a Hardware Hub, for interacting with the operation system of said computer and said graphic libraries, for performing real-time analysis of a data stream, from which frames of said image are generated, for determining the parallelization mode of each GPU, and for forwarding said data stream or a portion thereof to each GPU; d. providing one or more GPU Drivers, for allowing said GPUs to interact with said graphic libraries. e. providing at least one I/O module for interconnecting between said Software module and said Hardware Hub; and f. for each frame, distributing between said GPUs and by means of said Hardware Hub, graphic commands and said data stream or a portion thereof, according to their relative complexity within said image, said complexity is defined by said Software Hub Driver; and compositing a graphics output for display, using the outputs obtained from at least one GPU, while alternating, whenever required, said parallelization mode for said each frame.
9. A method according to claim 8, wherein the parallelization mode is an Object division parallelization mode and the following steps are performed: a. for each frame, generating a stream of graphic operations and polygonal data; b. marking the polygonal data and graphic commands by means of the Software Hub Driver for distribution between multiple GPUs; c. sending the marked data to the Hardware Hub; d. distributing said marked data via the Hub Router to said multiple GPUs; e. rendering the data by means of GPUs; f. retrieving the data from the Frame Buffers and forwarding the retrieved data to the compositing unit via the Hub Router; g. compositing the content of said Frame Buffers into a single Frame Buffer; and h. forwarding the content of said single Frame Buffer to at least one designated GPU for display.
10. A method according to claim 8, wherein the parallelization mode is an Image division parallelization mode and the following steps are performed: a. subdividing the screen to portions and assigning different viewports to GPUs by means of the Software Hub Driver; b. moving the entire polygonal data and graphic commands to the Hub Router; c. transmitting said entire polygonal data and graphic commands to GPUs, wherein each GPU receives the same data; d. rendering the data by means of GPUs; e. forwarding a portion of the content stored in the Frame Buffers to compositing unit in Hardware Hub for the complete image creation; and f. forwarding said image to at least one designated GPU for display.
11. A method according to claim 8, wherein the parallelization mode is a Time division parallelization mode and the following steps are performed: a. forwarding to each one of the multiple GPUs the entire amount of polygons for rendering; b. redirecting the entire polygonal data and graphic commands by means of Software • Hub Driver to all GPUs, while alternating between them; c. rendering the data by means of GPUs; d. transferring rendered data from at least one GPU via the Hub Router; and e. redirecting the resulting content of the Frame Buffer via Hub Router to at least one designated GPU for display.
12. A method according to claim 8, wherein the distribution of polygons between multiple GPUs is performed by: a. distributing blocks of data between multiple GPUs; b. testing each graphic operation for blocking mode, in which one or more parallelization modes are carried out; c. redirecting the data in regular non-blocking path to at least one designated GPU; d. repeating step (b) and (c) until a blocking operation is detected; e. synchronizing GPUs by the following sequence: e.l. performing a flush operation in order to terminate rendering and clean up the internal pipeline in each GPU; e.2. performing a composition operation for merging the contents of the Frame Buffers into a single Frame Buffer; and e.3. transmitting said single Frame Buffer back to all GPUs; f. terminating the composited complete frame at all GPUs, except one or more designated GPUs, whenever a Swap operation is detected and displaying the image by means of said one or more designated GPUs; g. processing the same data by means of all GPUs, as long as the blocking mode is active and the Swap operation is not detected; and h. continuing to process the designated data by means of multiple GPUs, whenever the blocking mode is inactive.
13. Method according to claim 8, wherein the parallelization is based on an object division mode or on an image division mode or on a time division mode or on any combination thereof.
PCT/IL2004/001069 2003-11-19 2004-11-19 Method and system for multiple 3-d graphic pipeline over a pc bus WO2005050557A2 (en)

Priority Applications (60)

Application Number Priority Date Filing Date Title
JP2006540774A JP2007512613A (en) 2003-11-19 2004-11-19 Method and system for multiple 3-D graphic pipelines on a PC bus
CA002546427A CA2546427A1 (en) 2003-11-19 2004-11-19 Method and system for multiple 3-d graphic pipeline over a pc bus
EP04799376A EP1687732A4 (en) 2003-11-19 2004-11-19 Method and system for multiple 3-d graphic pipeline over a pc bus
US10/579,682 US7808499B2 (en) 2003-11-19 2004-11-19 PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
US11/340,402 US7812844B2 (en) 2004-01-28 2006-01-25 PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application
US11/386,454 US7834880B2 (en) 2004-01-28 2006-03-22 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US11/655,735 US8085273B2 (en) 2003-11-19 2007-01-18 Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US11/897,536 US7961194B2 (en) 2003-11-19 2007-08-30 Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US11/901,692 US7777748B2 (en) 2003-11-19 2007-09-18 PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications
US11/901,727 US20080094402A1 (en) 2003-11-19 2007-09-18 Computing system having a parallel graphics rendering system employing multiple graphics processing pipelines (GPPLS) dynamically controlled according to time, image and object division modes of parallel operation during the run-time of graphics-based applications running on the computing system
US11/901,714 US20080074429A1 (en) 2003-11-19 2007-09-18 Multi-mode parallel graphics rendering system (MMPGRS) supporting real-time transition between multiple states of parallel rendering operation in response to the automatic detection of predetermined operating conditions
US11/901,733 US20080094404A1 (en) 2003-11-19 2007-09-18 Computing system having multi-mode parallel graphics rendering subsystem including multiple graphics processing pipelines (GPPLS) and supporting automated division of graphics commands and data during automatic mode control
US11/901,713 US20080068389A1 (en) 2003-11-19 2007-09-18 Multi-mode parallel graphics rendering system (MMPGRS) embodied within a host computing system and employing the profiling of scenes in graphics-based applications
US11/901,716 US20080246772A1 (en) 2003-11-19 2007-09-18 Multi-mode parallel graphics rendering system (MMPGRS) employing multiple graphics processing pipelines (GPPLS) and real-time performance data collection and analysis during the automatic control of the mode of parallel operation of said GPPLS
US11/901,697 US20080074428A1 (en) 2003-11-19 2007-09-18 Method of rendering pixel-composited images for a graphics-based application running on a computing system embodying a multi-mode parallel graphics rendering system
US11/901,715 US20080074431A1 (en) 2003-11-19 2007-09-18 Computing system capable of parallelizing the operation of multiple graphics processing units (GPUS) supported on external graphics cards
US11/901,745 US20080079737A1 (en) 2003-11-19 2007-09-18 Multi-mode parallel graphics rendering and display system supporting real-time detection of mode control commands (MCCS) programmed within pre-profiled scenes of the graphics-based application
US11/901,696 US20080088631A1 (en) 2003-11-19 2007-09-18 Multi-mode parallel graphics rendering and display system supporting real-time detection of scene profile indices programmed within pre-profiled scenes of the graphics-based application
US11/903,187 US20080094403A1 (en) 2003-11-19 2007-09-20 Computing system capable of parallelizing the operation graphics processing units (GPUs) supported on a CPU/GPU fusion-architecture chip and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US11/903,202 US20080198167A1 (en) 2003-11-19 2007-09-20 Computing system capable of parallelizing the operation of graphics processing units (GPUS) supported on an integrated graphics device (IGD) and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US11/903,203 US20080316216A1 (en) 2003-11-19 2007-09-20 Computing system capable of parallelizing the operation of multiple graphics processing pipelines (GPPLS) supported on a multi-core CPU chip, and employing a software-implemented multi-mode parallel graphics rendering subsystem
US11/904,043 US20080088632A1 (en) 2003-11-19 2007-09-25 Computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on an integrated graphics device (IGD) within a bridge circuit, wherewithin image recomposition is carried out
US11/904,041 US20080084421A1 (en) 2003-11-19 2007-09-25 Computing system capable of parallelizing the operation of multiple graphical processing units (GPUs) supported on external graphics cards, with image recomposition being carried out within said GPUs
US11/904,040 US7940274B2 (en) 2003-11-19 2007-09-25 Computing system having a multiple graphics processing pipeline (GPPL) architecture supported on multiple external graphics cards connected to an integrated graphics device (IGD) embodied within a bridge circuit
US11/904,022 US20080084418A1 (en) 2003-11-19 2007-09-25 Computing system capable of parallelizing the operation of multiple graphics processing units (GPUS) supported on an integrated graphics device (IGD) within a bridge circuit
US11/904,042 US20080084422A1 (en) 2003-11-19 2007-09-25 Computing system capable of parallelizing the operation of multiple graphics processing units (GPUS) supported on external graphics cards connected to a graphics hub device with image recomposition being carried out across two or more of said GPUS
US11/904,039 US20080084419A1 (en) 2003-11-19 2007-09-25 Computing system capable of parallelizing the operation of multiple graphics processing units supported on external graphics cards connected to a graphics hub device
US11/904,294 US20080084423A1 (en) 2003-11-19 2007-09-26 Computing system capable of parallelizing the operation of multiple graphics pipelines (GPPLS) implemented on a multi-core CPU chip
US11/904,317 US8125487B2 (en) 2003-11-19 2007-09-26 Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board
US11/904,300 US7944450B2 (en) 2003-11-19 2007-09-26 Computing system having a hybrid CPU/GPU fusion-type graphics processing pipeline (GPPL) architecture
US11/977,155 US8629877B2 (en) 2003-11-19 2007-10-23 Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system
US11/977,161 US7796129B2 (en) 2003-11-19 2007-10-23 Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus
US11/977,172 US7800610B2 (en) 2003-11-19 2007-10-23 PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application
US11/977,177 US7796130B2 (en) 2003-11-19 2007-10-23 PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation
US11/977,178 US7800611B2 (en) 2003-11-19 2007-10-23 Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus
US11/977,164 US7800619B2 (en) 2003-11-19 2007-10-23 Method of providing a PC-based computing system with parallel graphics processing capabilities
US11/977,719 US20080117218A1 (en) 2004-01-28 2007-10-25 PC-based computing system employing parallelized GPU-driven pipeline cores integrated with a routing unit and control unit on a silicon chip of monolithic construction
US11/978,149 US20080129743A1 (en) 2004-01-28 2007-10-26 Silicon chip of monolithic construction for integration in a PC-based computing system and having multiple GPU-driven pipeline cores supporting multiple modes of parallelization dynamically controlled while running a graphics application
US11/978,239 US7812846B2 (en) 2003-11-19 2007-10-26 PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation
US11/978,226 US7812845B2 (en) 2004-01-28 2007-10-26 PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application
US11/978,220 US7843457B2 (en) 2003-11-19 2007-10-26 PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application
US11/978,228 US7808504B2 (en) 2004-01-28 2007-10-26 PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications
US11/978,146 US20080129741A1 (en) 2004-01-28 2007-10-26 PC-based computing system employing a bridge chip having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation
US11/978,148 US20080129742A1 (en) 2004-01-28 2007-10-26 PC-based computing system employing a bridge chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores during the running of a graphics application
US11/978,229 US20080122850A1 (en) 2004-01-28 2007-10-26 PC-based computing system employing a bridge chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application
US11/980,318 US20080211817A1 (en) 2003-11-19 2007-10-30 Internet-based application profile database server system for updating graphic application profiles (GAPS) stored within the multi-mode parallel graphics rendering system of client machines running one or more graphic applications
US11/978,993 US20080129747A1 (en) 2003-11-19 2007-10-30 Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US11/980,089 US8134563B2 (en) 2003-11-19 2007-10-30 Computing system having multi-mode parallel graphics rendering subsystem (MMPGRS) employing real-time automatic scene profiling and mode control
US12/077,072 US20090027383A1 (en) 2003-11-19 2008-03-14 Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition
US12/229,215 US20090135190A1 (en) 2003-11-19 2008-08-20 Multimode parallel graphics rendering systems and methods supporting task-object division
US12/231,304 US8284207B2 (en) 2003-11-19 2008-08-29 Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations
US12/231,295 US20090128550A1 (en) 2003-11-19 2008-08-29 Computing system supporting parallel 3D graphics processes based on the division of objects in 3D scenes
US12/231,296 US20090179894A1 (en) 2003-11-19 2008-08-29 Computing system capable of parallelizing the operation of multiple graphics processing pipelines (GPPLS)
US12/941,233 US8754894B2 (en) 2003-11-19 2010-11-08 Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications
US12/946,032 US8754897B2 (en) 2004-01-28 2010-11-15 Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem
US13/101,438 US20110279462A1 (en) 2003-11-19 2011-05-05 Method of and subsystem for graphics processing in a pc-level computing system
US13/646,710 US20130120410A1 (en) 2003-11-19 2012-10-07 Multi-pass method of generating an image frame of a 3d scene using an object-division based parallel graphics rendering process
US14/153,105 US9405586B2 (en) 2003-11-19 2014-01-13 Method of dynamic load-balancing within a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization
US14/304,991 US9659340B2 (en) 2004-01-28 2014-06-16 Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem
US14/305,010 US9584592B2 (en) 2003-11-19 2014-06-16 Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications

Applications Claiming Priority (4)

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US52308403P 2003-11-19 2003-11-19
US52310203P 2003-11-19 2003-11-19
US60/523,102 2003-11-19
US60/523,084 2003-11-19

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PCT/IL2004/000079 Continuation-In-Part WO2004070652A2 (en) 2003-01-28 2004-01-28 Method and system for compositing three-dimensional graphics images using associative decision mechanism
US10/579,682 A-371-Of-International US7808499B2 (en) 2003-11-19 2004-11-19 PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
PCT/IB2006/001529 Continuation-In-Part WO2006117683A2 (en) 2003-11-19 2006-01-25 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US11/340,402 Continuation-In-Part US7812844B2 (en) 2003-11-19 2006-01-25 PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application
US11/386,454 Continuation-In-Part US7834880B2 (en) 2003-11-19 2006-03-22 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US11/789,039 Continuation-In-Part US20070291040A1 (en) 2003-11-19 2007-04-23 Multi-mode parallel graphics rendering system supporting dynamic profiling of graphics-based applications and automatic control of parallel modes of operation
US11/897,536 Continuation-In-Part US7961194B2 (en) 2003-11-19 2007-08-30 Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US11/904,039 Continuation-In-Part US20080084419A1 (en) 2003-11-19 2007-09-25 Computing system capable of parallelizing the operation of multiple graphics processing units supported on external graphics cards connected to a graphics hub device
US11/904,041 Continuation-In-Part US20080084421A1 (en) 2003-11-19 2007-09-25 Computing system capable of parallelizing the operation of multiple graphical processing units (GPUs) supported on external graphics cards, with image recomposition being carried out within said GPUs
US11/977,178 Continuation US7800611B2 (en) 2003-11-19 2007-10-23 Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus
US11/977,177 Continuation US7796130B2 (en) 2003-11-19 2007-10-23 PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation
US11/977,164 Continuation US7800619B2 (en) 2003-11-19 2007-10-23 Method of providing a PC-based computing system with parallel graphics processing capabilities
US11/977,161 Continuation US7796129B2 (en) 2003-11-19 2007-10-23 Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus
US11/977,172 Continuation US7800610B2 (en) 2003-11-19 2007-10-23 PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application
US11/977,155 Continuation US8629877B2 (en) 2003-11-19 2007-10-23 Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2465812A (en) * 2008-12-01 2010-06-02 Imagination Tech Ltd Distributed processing for rendering 3D images
US7830387B2 (en) 2006-11-07 2010-11-09 Microsoft Corporation Parallel engine support in display driver model
JP2011513874A (en) * 2008-03-11 2011-04-28 コア ロジック，インコーポレイテッド 3D graphics processing supporting a fixed pipeline
US8319782B2 (en) 2008-07-08 2012-11-27 Dell Products, Lp Systems and methods for providing scalable parallel graphics rendering capability for information handling systems
US8751658B2 (en) 2011-03-31 2014-06-10 Fujitsu Limited Allocating method, allocating apparatus, and computer product
CN108416836A (en) * 2018-02-06 2018-08-17 上海滚滚文化传播有限公司 It is a kind of to render the caricature production method for turning two dimensional surface by three-dimensional modeling
CN110730976A (en) * 2017-06-12 2020-01-24 苹果公司 Method and system for a transaction-based display pipeline interfacing with a graphics processing unit
CN111679877A (en) * 2020-05-27 2020-09-18 浙江大华技术股份有限公司 Method and device for changing background of terminal equipment and electronic equipment

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8745173B1 (en) * 2011-12-30 2014-06-03 hopTo Inc. Client computing system for and method of receiving cross-platform remote access to 3D graphics applications
US7222305B2 (en) * 2003-03-13 2007-05-22 Oracle International Corp. Method of sharing a desktop with attendees of a real-time collaboration
US7808499B2 (en) 2003-11-19 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
US7457921B2 (en) * 2005-02-23 2008-11-25 Microsoft Corporation Write barrier for data storage integrity
US8217950B2 (en) * 2005-05-27 2012-07-10 Advanced Micro Devices, Inc. Video processing across multiple graphics processing units
US10026140B2 (en) * 2005-06-10 2018-07-17 Nvidia Corporation Using a scalable graphics system to enable a general-purpose multi-user computer system
US7629978B1 (en) * 2005-10-31 2009-12-08 Nvidia Corporation Multichip rendering with state control
KR100803220B1 (en) * 2006-11-20 2008-02-14 삼성전자주식회사 Method and apparatus for rendering of 3d graphics of multi-pipeline
US8726289B2 (en) * 2008-02-22 2014-05-13 International Business Machines Corporation Streaming attachment of hardware accelerators to computer systems
US7953912B2 (en) * 2008-02-22 2011-05-31 International Business Machines Corporation Guided attachment of accelerators to computer systems
US8250578B2 (en) * 2008-02-22 2012-08-21 International Business Machines Corporation Pipelining hardware accelerators to computer systems
US9117007B2 (en) * 2008-05-14 2015-08-25 Microsoft Technology Licensing, Llc Visualization of streaming real-time data
CN101639930B (en) * 2008-08-01 2012-07-04 辉达公司 Method and system for processing graphical data by a series of graphical processors
US8427474B1 (en) 2008-10-03 2013-04-23 Nvidia Corporation System and method for temporal load balancing across GPUs
US8892804B2 (en) 2008-10-03 2014-11-18 Advanced Micro Devices, Inc. Internal BUS bridge architecture and method in multi-processor systems
US8373709B2 (en) * 2008-10-03 2013-02-12 Ati Technologies Ulc Multi-processor architecture and method
US8228337B1 (en) * 2008-10-03 2012-07-24 Nvidia Corporation System and method for temporal load balancing across GPUs
US8368701B2 (en) * 2008-11-06 2013-02-05 Via Technologies, Inc. Metaprocessor for GPU control and synchronization in a multiprocessor environment
KR101519825B1 (en) * 2008-12-05 2015-05-13 삼성전자주식회사 Data processing device and control method of the same
US9479358B2 (en) * 2009-05-13 2016-10-25 International Business Machines Corporation Managing graphics load balancing strategies
US20110063304A1 (en) * 2009-09-16 2011-03-17 Nvidia Corporation Co-processing synchronizing techniques on heterogeneous graphics processing units
JP5590849B2 (en) * 2009-10-08 2014-09-17 キヤノン株式会社 Data processing apparatus including parallel processing circuit having a plurality of processing modules, its control apparatus, its control method, and program
FR2952731B1 (en) * 2009-11-13 2011-11-04 Bull Sas METHOD AND DEVICE FOR OPTIMIZING THE EXECUTION OF SOFTWARE APPLICATIONS IN A MULTIPROCESSOR ARCHITECTURE COMPRISING SEVERAL INPUT / OUTPUT CONTROLLERS AND SECONDARY CALCULATION UNITS
US9830889B2 (en) 2009-12-31 2017-11-28 Nvidia Corporation Methods and system for artifically and dynamically limiting the display resolution of an application
US20110242115A1 (en) * 2010-03-30 2011-10-06 You-Ming Tsao Method for performing image signal processing with aid of a graphics processing unit, and associated apparatus
US20110298816A1 (en) * 2010-06-03 2011-12-08 Microsoft Corporation Updating graphical display content
US8675002B1 (en) 2010-06-09 2014-03-18 Ati Technologies, Ulc Efficient approach for a unified command buffer
JP2012003619A (en) * 2010-06-18 2012-01-05 Sony Corp Information processor, control method thereof and program
JP5835942B2 (en) 2010-06-25 2015-12-24 キヤノン株式会社 Image processing apparatus, control method thereof, and program
US20120001905A1 (en) * 2010-06-30 2012-01-05 Ati Technologies, Ulc Seamless Integration of Multi-GPU Rendering
US20120001925A1 (en) 2010-06-30 2012-01-05 Ati Technologies, Ulc Dynamic Feedback Load Balancing
US20120127183A1 (en) * 2010-10-21 2012-05-24 Net Power And Light, Inc. Distribution Processing Pipeline and Distributed Layered Application Processing
US20120147015A1 (en) * 2010-12-13 2012-06-14 Advanced Micro Devices, Inc. Graphics Processing in a Multi-Processor Computing System
US8866825B2 (en) * 2010-12-15 2014-10-21 Ati Technologies Ulc Multiple display frame rendering method and apparatus
US8786619B2 (en) 2011-02-25 2014-07-22 Adobe Systems Incorporated Parallelized definition and display of content in a scripting environment
CN102270095A (en) * 2011-06-30 2011-12-07 威盛电子股份有限公司 Multiple display control method and system
US9727385B2 (en) * 2011-07-18 2017-08-08 Apple Inc. Graphical processing unit (GPU) implementing a plurality of virtual GPUs
US9019292B2 (en) 2011-09-12 2015-04-28 Microsoft Technology Licensing Llc Reordering graph execution for processing optimization
US20130148947A1 (en) * 2011-12-13 2013-06-13 Ati Technologies Ulc Video player with multiple grpahics processors
US8842122B2 (en) * 2011-12-15 2014-09-23 Qualcomm Incorporated Graphics processing unit with command processor
US8838749B1 (en) 2011-12-30 2014-09-16 hopTo Inc. Cloud based client computing system for and method of receiving cross-platform remote access to 3D graphics applications
US8769052B1 (en) 2011-12-30 2014-07-01 hopTo Inc. Cloud-based server computing system for and method of providing cross-platform remote access to 3D graphics applications
US8766990B1 (en) 2011-12-30 2014-07-01 hopTo Inc. Server computing system for and method of providing cross-platform remote access to 3D graphics applications
US20150302550A1 (en) * 2012-01-06 2015-10-22 Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi Image generation system
US8692832B2 (en) 2012-01-23 2014-04-08 Microsoft Corporation Para-virtualized asymmetric GPU processors
US20130328884A1 (en) * 2012-06-08 2013-12-12 Advanced Micro Devices, Inc. Direct opencl graphics rendering
CN102868601B (en) * 2012-09-24 2015-05-13 上海天玑科技股份有限公司 Routing system related to network topology based on graphic configuration database businesses
TWI482118B (en) * 2012-10-18 2015-04-21 Wistron Corp System and method for processing load balance of graphic streams
TW201421420A (en) * 2012-11-21 2014-06-01 Inst Information Industry Graphic processing unit virtual apparatus, graphic processing unit host apparatus, and graphic processing unit program processing methods thereof
KR102124395B1 (en) * 2013-08-12 2020-06-18 삼성전자주식회사 Graphics processing apparatus and method thereof
US9348602B1 (en) 2013-09-03 2016-05-24 Amazon Technologies, Inc. Resource allocation for staged execution pipelining
US20150279037A1 (en) 2014-01-11 2015-10-01 Userful Corporation System and Method of Video Wall Setup and Adjustment Using Automated Image Analysis
KR102277353B1 (en) 2014-02-21 2021-07-15 삼성전자주식회사 Video processing method and electronic device
US9471955B2 (en) * 2014-06-19 2016-10-18 Apple Inc. Multiple display pipelines driving a divided display
CN104915320A (en) * 2015-05-28 2015-09-16 浪潮电子信息产业股份有限公司 GPU (Graphic Processing Unit) server
CN106326186B (en) * 2015-06-29 2019-04-30 深圳市中兴微电子技术有限公司 A kind of system on chip, pattern drawing method, middle layer and embedded device
US10499072B2 (en) * 2016-02-17 2019-12-03 Mimax, Inc. Macro cell display compression multi-head raster GPU
EP3301572B1 (en) * 2016-09-30 2023-05-24 Dassault Systèmes Method, program and system for simulating a 3d scene with a set of computing resources running in parallel
KR20180038793A (en) * 2016-10-07 2018-04-17 삼성전자주식회사 Method and apparatus for processing image data
US10504259B2 (en) * 2017-04-24 2019-12-10 Intel Corporation Separately processing regions or objects or interest from a render engine to a display engine or a display panel
CN108153593A (en) * 2017-12-22 2018-06-12 合肥寰景信息技术有限公司 The GPU cluster framework and its load-balancing method of a kind of high concurrent
US10573034B2 (en) 2018-04-13 2020-02-25 Honeywell International Inc. System and method for translation of graphics to newer format using pattern matching
KR102455820B1 (en) * 2018-05-31 2022-10-18 후아웨이 테크놀러지 컴퍼니 리미티드 Apparatus and method for command stream optimization and enhancement
US10747207B2 (en) 2018-06-15 2020-08-18 Honeywell International Inc. System and method for accurate automatic determination of “alarm-operator action” linkage for operator assessment and alarm guidance using custom graphics and control charts
US10699159B2 (en) 2018-08-17 2020-06-30 Honeywell International Inc. Objects aggregation and standardization for legacy graphics conversion
CN109408456B (en) * 2018-12-07 2023-08-29 中国地质大学（武汉） S905D chip and STM32 chip based cooperative hardware circuit
US11397624B2 (en) * 2019-01-22 2022-07-26 Arm Limited Execution of cross-lane operations in data processing systems
CN109962691A (en) * 2019-04-04 2019-07-02 同济大学 A kind of distributed self-adaption filter design method for sensor network
CN111045623B (en) * 2019-11-21 2023-06-13 中国航空工业集团公司西安航空计算技术研究所 Method for processing graphics commands in multi-GPU splicing environment
US11042957B1 (en) 2019-12-12 2021-06-22 Honeywell International Inc. Identification of process and control linkages from custom graphics for the purpose of backbuilding standard operating procedures
US11080814B1 (en) * 2020-02-03 2021-08-03 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against screen regions using prior frame information
CN111491059B (en) * 2020-04-09 2021-08-10 上海众链科技有限公司 Image rendering enhancement system and method
CN112057851A (en) * 2020-09-02 2020-12-11 北京蔚领时代科技有限公司 Multi-display-card-based real-time rendering method for single-frame picture
DE112020007672T5 (en) * 2020-11-12 2023-08-24 Nvidia Corporation INTRA LAYER ADAPTER FOR FIFTH GENERATION NEW RADIO COMMUNICATIONS (5G-NR)
CN114625329A (en) * 2020-12-11 2022-06-14 慧荣科技股份有限公司 Multi-screen display control device
CN114625330A (en) 2020-12-11 2022-06-14 慧荣科技股份有限公司 Multi-screen display control device
US11574579B2 (en) * 2021-06-23 2023-02-07 Dell Products L.P. Enabling display filters in collaborative environments
CN113436232B (en) * 2021-06-29 2023-03-24 上海律信信息科技有限公司 Hardware acceleration method based on tracking algorithm

Family Cites Families (219)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07104923B2 (en) * 1988-12-28 1995-11-13 工業技術院長 Parallel image display processing method
JP2770598B2 (en) * 1990-06-13 1998-07-02 株式会社日立製作所 Graphic display method and apparatus
CA2073516A1 (en) * 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
JP3199205B2 (en) * 1993-11-19 2001-08-13 株式会社日立製作所 Parallel processing unit
EP0693737A3 (en) * 1994-07-21 1997-01-08 Ibm Method and apparatus for managing multiprocessor graphical workload distribution
US5745762A (en) * 1994-12-15 1998-04-28 International Business Machines Corporation Advanced graphics driver architecture supporting multiple system emulations
US5687357A (en) 1995-04-14 1997-11-11 Nvidia Corporation Register array for utilizing burst mode transfer on local bus
US5754866A (en) 1995-05-08 1998-05-19 Nvidia Corporation Delayed interrupts with a FIFO in an improved input/output architecture
US5758182A (en) 1995-05-15 1998-05-26 Nvidia Corporation DMA controller translates virtual I/O device address received directly from application program command to physical i/o device address of I/O device on device bus
US5909595A (en) 1995-05-15 1999-06-01 Nvidia Corporation Method of controlling I/O routing by setting connecting context for utilizing I/O processing elements within a computer system to produce multimedia effects
US5623692A (en) 1995-05-15 1997-04-22 Nvidia Corporation Architecture for providing input/output operations in a computer system
US5794016A (en) * 1995-12-11 1998-08-11 Dynamic Pictures, Inc. Parallel-processor graphics architecture
KR100269106B1 (en) * 1996-03-21 2000-11-01 윤종용 Multiprocessor graphics system
WO1998007266A1 (en) * 1996-08-14 1998-02-19 Northern Telecom Limited Internet-based telephone call manager
US6118462A (en) * 1997-07-01 2000-09-12 Memtrax Llc Computer system controller having internal memory and external memory control
US6169553B1 (en) 1997-07-02 2001-01-02 Ati Technologies, Inc. Method and apparatus for rendering a three-dimensional scene having shadowing
US6201545B1 (en) 1997-09-23 2001-03-13 Ati Technologies, Inc. Method and apparatus for generating sub pixel masks in a three dimensional graphic processing system
US6856320B1 (en) 1997-11-25 2005-02-15 Nvidia U.S. Investment Company Demand-based memory system for graphics applications
US6337686B2 (en) 1998-01-07 2002-01-08 Ati Technologies Inc. Method and apparatus for line anti-aliasing
US6496187B1 (en) * 1998-02-17 2002-12-17 Sun Microsystems, Inc. Graphics system configured to perform parallel sample to pixel calculation
US6182196B1 (en) 1998-02-20 2001-01-30 Ati International Srl Method and apparatus for arbitrating access requests to a memory
US6473089B1 (en) 1998-03-02 2002-10-29 Ati Technologies, Inc. Method and apparatus for a video graphics circuit having parallel pixel processing
US6259460B1 (en) * 1998-03-26 2001-07-10 Silicon Graphics, Inc. Method for efficient handling of texture cache misses by recirculation
US7038692B1 (en) 1998-04-07 2006-05-02 Nvidia Corporation Method and apparatus for providing a vertex cache
US6092124A (en) 1998-04-17 2000-07-18 Nvidia Corporation Method and apparatus for accelerating the rendering of images
US6184908B1 (en) 1998-04-27 2001-02-06 Ati Technologies, Inc. Method and apparatus for co-processing video graphics data
US6212617B1 (en) * 1998-05-13 2001-04-03 Microsoft Corporation Parallel processing method and system using a lazy parallel data type to reduce inter-processor communication
US6477687B1 (en) 1998-06-01 2002-11-05 Nvidia U.S. Investment Company Method of embedding RAMS and other macrocells in the core of an integrated circuit chip
US6636215B1 (en) 1998-07-22 2003-10-21 Nvidia Corporation Hardware-assisted z-pyramid creation for host-based occlusion culling
US7023437B1 (en) 1998-07-22 2006-04-04 Nvidia Corporation System and method for accelerating graphics processing using a post-geometry data stream during multiple-pass rendering
US6646639B1 (en) 1998-07-22 2003-11-11 Nvidia Corporation Modified method and apparatus for improved occlusion culling in graphics systems
US7068272B1 (en) 2000-05-31 2006-06-27 Nvidia Corporation System, method and article of manufacture for Z-value and stencil culling prior to rendering in a computer graphics processing pipeline
US6415345B1 (en) 1998-08-03 2002-07-02 Ati Technologies Bus mastering interface control system for transferring multistream data over a host bus
US6191800B1 (en) * 1998-08-11 2001-02-20 International Business Machines Corporation Dynamic balancing of graphics workloads using a tiling strategy
US6492987B1 (en) 1998-08-27 2002-12-10 Ati Technologies, Inc. Method and apparatus for processing object elements that are being rendered
US6188412B1 (en) 1998-08-28 2001-02-13 Ati Technologies, Inc. Method and apparatus for performing setup operations in a video graphics system
US6292200B1 (en) * 1998-10-23 2001-09-18 Silicon Graphics, Inc. Apparatus and method for utilizing multiple rendering pipes for a single 3-D display
US6362825B1 (en) * 1999-01-19 2002-03-26 Hewlett-Packard Company Real-time combination of adjacent identical primitive data sets in a graphics call sequence
US6753878B1 (en) * 1999-03-08 2004-06-22 Hewlett-Packard Development Company, L.P. Parallel pipelined merge engines
JP3169933B2 (en) * 1999-03-16 2001-05-28 四国日本電気ソフトウェア株式会社 Parallel drawing device
US6535209B1 (en) 1999-03-17 2003-03-18 Nvidia Us Investments Co. Data stream splitting and storage in graphics data processing
US6288418B1 (en) 1999-03-19 2001-09-11 Nvidia Corporation Multiuse input/output connector arrangement for graphics accelerator integrated circuit
US6333744B1 (en) 1999-03-22 2001-12-25 Nvidia Corporation Graphics pipeline including combiner stages
US6577320B1 (en) 1999-03-22 2003-06-10 Nvidia Corporation Method and apparatus for processing multiple types of pixel component representations including processes of premultiplication, postmultiplication, and colorkeying/chromakeying
US6181352B1 (en) 1999-03-22 2001-01-30 Nvidia Corporation Graphics pipeline selectively providing multiple pixels or multiple textures
DE19917092A1 (en) * 1999-04-15 2000-10-26 Sp3D Chip Design Gmbh Accelerated method for grid forming of graphic basic element in order beginning with graphic base element instruction data to produce pixel data for graphic base element
US6990076B1 (en) * 1999-05-18 2006-01-24 Mcnamara Timothy G Synchronous bi-directional data transfer having increased bandwidth and scan test features
US6424320B1 (en) 1999-06-15 2002-07-23 Ati International Srl Method and apparatus for rendering video
US6469703B1 (en) 1999-07-02 2002-10-22 Ati International Srl System of accessing data in a graphics system and method thereof
US6442656B1 (en) 1999-08-18 2002-08-27 Ati Technologies Srl Method and apparatus for interfacing memory with a bus
US6352479B1 (en) 1999-08-31 2002-03-05 Nvidia U.S. Investment Company Interactive gaming server and online community forum
US6578068B1 (en) * 1999-08-31 2003-06-10 Accenture Llp Load balancer in environment services patterns
US6657635B1 (en) 1999-09-03 2003-12-02 Nvidia Corporation Binning flush in graphics data processing
US6844880B1 (en) 1999-12-06 2005-01-18 Nvidia Corporation System, method and computer program product for an improved programmable vertex processing model with instruction set
US6452595B1 (en) 1999-12-06 2002-09-17 Nvidia Corporation Integrated graphics processing unit with antialiasing
US6417851B1 (en) 1999-12-06 2002-07-09 Nvidia Corporation Method and apparatus for lighting module in a graphics processor
US6573900B1 (en) 1999-12-06 2003-06-03 Nvidia Corporation Method, apparatus and article of manufacture for a sequencer in a transform/lighting module capable of processing multiple independent execution threads
US6198488B1 (en) 1999-12-06 2001-03-06 Nvidia Transform, lighting and rasterization system embodied on a single semiconductor platform
US6870540B1 (en) 1999-12-06 2005-03-22 Nvidia Corporation System, method and computer program product for a programmable pixel processing model with instruction set
US7002577B2 (en) 1999-12-06 2006-02-21 Nvidia Corporation Clipping system and method for a single graphics semiconductor platform
US6353439B1 (en) 1999-12-06 2002-03-05 Nvidia Corporation System, method and computer program product for a blending operation in a transform module of a computer graphics pipeline
US6473086B1 (en) 1999-12-09 2002-10-29 Ati International Srl Method and apparatus for graphics processing using parallel graphics processors
US6557065B1 (en) * 1999-12-20 2003-04-29 Intel Corporation CPU expandability bus
US6760031B1 (en) * 1999-12-31 2004-07-06 Intel Corporation Upgrading an integrated graphics subsystem
WO2001069207A1 (en) * 2000-03-16 2001-09-20 Fuji Photo Film Co., Ltd. Measuring method and instrument utilizing total reflection attenuation
US6975319B1 (en) 2000-03-24 2005-12-13 Nvidia Corporation System, method and article of manufacture for calculating a level of detail (LOD) during computer graphics processing
US6831652B1 (en) 2000-03-24 2004-12-14 Ati International, Srl Method and system for storing graphics data
US6747654B1 (en) 2000-04-20 2004-06-08 Ati International Srl Multiple device frame synchronization method and apparatus
US6741243B2 (en) * 2000-05-01 2004-05-25 Broadcom Corporation Method and system for reducing overflows in a computer graphics system
US6725457B1 (en) 2000-05-17 2004-04-20 Nvidia Corporation Semaphore enhancement to improve system performance
US6670958B1 (en) 2000-05-26 2003-12-30 Ati International, Srl Method and apparatus for routing data to multiple graphics devices
US6789154B1 (en) * 2000-05-26 2004-09-07 Ati International, Srl Apparatus and method for transmitting data
US6728820B1 (en) 2000-05-26 2004-04-27 Ati International Srl Method of configuring, controlling, and accessing a bridge and apparatus therefor
US6633296B1 (en) 2000-05-26 2003-10-14 Ati International Srl Apparatus for providing data to a plurality of graphics processors and method thereof
US6662257B1 (en) 2000-05-26 2003-12-09 Ati International Srl Multiple device bridge apparatus and method thereof
US6690372B2 (en) 2000-05-31 2004-02-10 Nvidia Corporation System, method and article of manufacture for shadow mapping
US6664963B1 (en) 2000-05-31 2003-12-16 Nvidia Corporation System, method and computer program product for programmable shading using pixel shaders
US6593923B1 (en) 2000-05-31 2003-07-15 Nvidia Corporation System, method and article of manufacture for shadow mapping
US6724394B1 (en) 2000-05-31 2004-04-20 Nvidia Corporation Programmable pixel shading architecture
US6532013B1 (en) 2000-05-31 2003-03-11 Nvidia Corporation System, method and article of manufacture for pixel shaders for programmable shading
US6801202B2 (en) * 2000-06-29 2004-10-05 Sun Microsystems, Inc. Graphics system configured to parallel-process graphics data using multiple pipelines
US7405734B2 (en) 2000-07-18 2008-07-29 Silicon Graphics, Inc. Method and system for presenting three-dimensional computer graphics images using multiple graphics processing units
US6959110B1 (en) 2000-08-17 2005-10-25 Nvidia Corporation Multi-mode texture compression algorithm
US7116331B1 (en) 2000-08-23 2006-10-03 Intel Corporation Memory controller hub interface
US6842180B1 (en) * 2000-09-20 2005-01-11 Intel Corporation Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor
US6532525B1 (en) 2000-09-29 2003-03-11 Ati Technologies, Inc. Method and apparatus for accessing memory
US6502173B1 (en) 2000-09-29 2002-12-31 Ati Technologies, Inc. System for accessing memory and method therefore
US6828980B1 (en) 2000-10-02 2004-12-07 Nvidia Corporation System, method and computer program product for z-texture mapping
US6731298B1 (en) 2000-10-02 2004-05-04 Nvidia Corporation System, method and article of manufacture for z-texture mapping
JP3580789B2 (en) * 2000-10-10 2004-10-27 株式会社ソニー・コンピュータエンタテインメント Data communication system and method, computer program, recording medium
US6961057B1 (en) 2000-10-12 2005-11-01 Nvidia Corporation Method and apparatus for managing and accessing depth data in a computer graphics system
US6362997B1 (en) 2000-10-16 2002-03-26 Nvidia Memory system for use on a circuit board in which the number of loads are minimized
US6636212B1 (en) 2000-11-14 2003-10-21 Nvidia Corporation Method and apparatus for determining visibility of groups of pixels
US6778181B1 (en) 2000-12-07 2004-08-17 Nvidia Corporation Graphics processing system having a virtual texturing array
US7027972B1 (en) 2001-01-24 2006-04-11 Ati Technologies, Inc. System for collecting and analyzing graphics data and method thereof
US7358974B2 (en) * 2001-01-29 2008-04-15 Silicon Graphics, Inc. Method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video
US6888580B2 (en) 2001-02-27 2005-05-03 Ati Technologies Inc. Integrated single and dual television tuner having improved fine tuning
US7130316B2 (en) 2001-04-11 2006-10-31 Ati Technologies, Inc. System for frame based audio synchronization and method thereof
US6542971B1 (en) 2001-04-23 2003-04-01 Nvidia Corporation Memory access system and method employing an auxiliary buffer
US6664960B2 (en) 2001-05-10 2003-12-16 Ati Technologies Inc. Apparatus for processing non-planar video graphics primitives and associated method of operation
US6700583B2 (en) 2001-05-14 2004-03-02 Ati Technologies, Inc. Configurable buffer for multipass applications
WO2002101497A2 (en) 2001-06-08 2002-12-19 Nvidia Corporation System, method and computer program product for programmable fragment processing in a graphics pipeline
US6697064B1 (en) 2001-06-08 2004-02-24 Nvidia Corporation System, method and computer program product for matrix tracking during vertex processing in a graphics pipeline
US6894687B1 (en) 2001-06-08 2005-05-17 Nvidia Corporation System, method and computer program product for vertex attribute aliasing in a graphics pipeline
US6731282B2 (en) 2001-06-19 2004-05-04 Intel Corporation System and method for parallel rendering of images
JP2003030641A (en) * 2001-07-19 2003-01-31 Nec System Technologies Ltd Plotting device, parallel plotting method therefor and parallel plotting program
US6828987B2 (en) 2001-08-07 2004-12-07 Ati Technologies, Inc. Method and apparatus for processing video and graphics data
US7253818B2 (en) 2001-08-07 2007-08-07 Ati Technologies, Inc. System for testing multiple devices on a single system and method thereof
US6778189B1 (en) 2001-08-24 2004-08-17 Nvidia Corporation Two-sided stencil testing system and method
US6704025B1 (en) 2001-08-31 2004-03-09 Nvidia Corporation System and method for dual-depth shadow-mapping
US6744433B1 (en) 2001-08-31 2004-06-01 Nvidia Corporation System and method for using and collecting information from a plurality of depth layers
US6989840B1 (en) 2001-08-31 2006-01-24 Nvidia Corporation Order-independent transparency rendering system and method
US6947047B1 (en) 2001-09-20 2005-09-20 Nvidia Corporation Method and system for programmable pipelined graphics processing with branching instructions
US6938176B1 (en) 2001-10-05 2005-08-30 Nvidia Corporation Method and apparatus for power management of graphics processors and subsystems that allow the subsystems to respond to accesses when subsystems are idle
US6999076B2 (en) 2001-10-29 2006-02-14 Ati Technologies, Inc. System, method, and apparatus for early culling
US7091971B2 (en) 2001-10-29 2006-08-15 Ati Technologies, Inc. System, method, and apparatus for multi-level hierarchical Z buffering
US6677953B1 (en) 2001-11-08 2004-01-13 Nvidia Corporation Hardware viewport system and method for use in a graphics pipeline
US20030117971A1 (en) * 2001-12-21 2003-06-26 Celoxica Ltd. System, method, and article of manufacture for profiling an executable hardware model using calls to profiling functions
US6683614B2 (en) * 2001-12-21 2004-01-27 Hewlett-Packard Development Company, L.P. System and method for automatically configuring graphics pipelines by tracking a region of interest in a computer graphical display system
US7269125B2 (en) 2001-12-26 2007-09-11 Xm Satellite Radio, Inc. Method and apparatus for timing recovery in an OFDM system
US7012610B2 (en) 2002-01-04 2006-03-14 Ati Technologies, Inc. Portable device for providing dual display and method thereof
US6774895B1 (en) 2002-02-01 2004-08-10 Nvidia Corporation System and method for depth clamping in a hardware graphics pipeline
US6829689B1 (en) 2002-02-12 2004-12-07 Nvidia Corporation Method and system for memory access arbitration for minimizing read/write turnaround penalties
US6947865B1 (en) 2002-02-15 2005-09-20 Nvidia Corporation Method and system for dynamic power supply voltage adjustment for a semiconductor integrated circuit device
US6933943B2 (en) 2002-02-27 2005-08-23 Hewlett-Packard Development Company, L.P. Distributed resource architecture and system
US6700580B2 (en) * 2002-03-01 2004-03-02 Hewlett-Packard Development Company, L.P. System and method utilizing multiple pipelines to render graphical data
US6853380B2 (en) * 2002-03-04 2005-02-08 Hewlett-Packard Development Company, L.P. Graphical display system and method
US20030171907A1 (en) * 2002-03-06 2003-09-11 Shay Gal-On Methods and Apparatus for Optimizing Applications on Configurable Processors
US6919896B2 (en) * 2002-03-11 2005-07-19 Sony Computer Entertainment Inc. System and method of optimizing graphics processing
US7009605B2 (en) 2002-03-20 2006-03-07 Nvidia Corporation System, method and computer program product for generating a shader program
AU2003228353A1 (en) * 2002-03-22 2003-10-13 Michael F. Deering Scalable high performance 3d graphics
US20030212735A1 (en) 2002-05-13 2003-11-13 Nvidia Corporation Method and apparatus for providing an integrated network of processors
US20040153778A1 (en) 2002-06-12 2004-08-05 Ati Technologies, Inc. Method, system and software for configuring a graphics processing communication mode
US6980209B1 (en) 2002-06-14 2005-12-27 Nvidia Corporation Method and system for scalable, dataflow-based, programmable processing of graphics data
US6812927B1 (en) 2002-06-18 2004-11-02 Nvidia Corporation System and method for avoiding depth clears using a stencil buffer
US6876362B1 (en) 2002-07-10 2005-04-05 Nvidia Corporation Omnidirectional shadow texture mapping
US6797998B2 (en) 2002-07-16 2004-09-28 Nvidia Corporation Multi-configuration GPU interface device
US6825843B2 (en) 2002-07-18 2004-11-30 Nvidia Corporation Method and apparatus for loop and branch instructions in a programmable graphics pipeline
US6954204B2 (en) 2002-07-18 2005-10-11 Nvidia Corporation Programmable graphics system and method using flexible, high-precision data formats
US6864893B2 (en) 2002-07-19 2005-03-08 Nvidia Corporation Method and apparatus for modifying depth values using pixel programs
US6952206B1 (en) 2002-08-12 2005-10-04 Nvidia Corporation Graphics application program interface system and method for accelerating graphics processing
US7112884B2 (en) 2002-08-23 2006-09-26 Ati Technologies, Inc. Integrated circuit having memory disposed thereon and method of making thereof
US6779069B1 (en) 2002-09-04 2004-08-17 Nvidia Corporation Computer system with source-synchronous digital link
US7324547B1 (en) * 2002-12-13 2008-01-29 Nvidia Corporation Internet protocol (IP) router residing in a processor chipset
US6885376B2 (en) * 2002-12-30 2005-04-26 Silicon Graphics, Inc. System, method, and computer program product for near-real time load balancing across multiple rendering pipelines
WO2004070652A2 (en) 2003-01-28 2004-08-19 Lucid Information Technology Ltd. Method and system for compositing three-dimensional graphics images using associative decision mechanism
US7062272B2 (en) * 2003-02-18 2006-06-13 Qualcomm Incorporated Method and apparatus to track count of broadcast content recipients in a wireless telephone network
US7145565B2 (en) 2003-02-27 2006-12-05 Nvidia Corporation Depth bounds testing
US6911983B2 (en) 2003-03-12 2005-06-28 Nvidia Corporation Double-buffering of pixel data using copy-on-write semantics
US7129909B1 (en) 2003-04-09 2006-10-31 Nvidia Corporation Method and system using compressed display mode list
US6940515B1 (en) 2003-04-10 2005-09-06 Nvidia Corporation User programmable primitive engine
US6900810B1 (en) 2003-04-10 2005-05-31 Nvidia Corporation User programmable geometry engine
US7483031B2 (en) 2003-04-17 2009-01-27 Nvidia Corporation Method for synchronizing graphics processing units
US7120816B2 (en) 2003-04-17 2006-10-10 Nvidia Corporation Method for testing synchronization and connection status of a graphics processing unit module
US7068278B1 (en) 2003-04-17 2006-06-27 Nvidia Corporation Synchronized graphics processing units
US7038678B2 (en) 2003-05-21 2006-05-02 Nvidia Corporation Dependent texture shadow antialiasing
US7038685B1 (en) 2003-06-30 2006-05-02 Nvidia Corporation Programmable graphics processor for multithreaded execution of programs
US7119808B2 (en) * 2003-07-15 2006-10-10 Alienware Labs Corp. Multiple parallel processor computer graphics system
US6995767B1 (en) 2003-07-31 2006-02-07 Nvidia Corporation Trilinear optimization for texture filtering
US7015915B1 (en) 2003-08-12 2006-03-21 Nvidia Corporation Programming multiple chips from a command buffer
US7525547B1 (en) * 2003-08-12 2009-04-28 Nvidia Corporation Programming multiple chips from a command buffer to process multiple images
US7075541B2 (en) 2003-08-18 2006-07-11 Nvidia Corporation Adaptive load balancing in a multi-processor graphics processing system
US6956579B1 (en) * 2003-08-18 2005-10-18 Nvidia Corporation Private addressing in a multi-processor graphics processing system
US7388581B1 (en) * 2003-08-28 2008-06-17 Nvidia Corporation Asynchronous conditional graphics rendering
US8250412B2 (en) 2003-09-26 2012-08-21 Ati Technologies Ulc Method and apparatus for monitoring and resetting a co-processor
US7782325B2 (en) * 2003-10-22 2010-08-24 Alienware Labs Corporation Motherboard for supporting multiple graphics cards
US8274517B2 (en) * 2003-11-14 2012-09-25 Microsoft Corporation Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
US7808499B2 (en) 2003-11-19 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US20080246772A1 (en) 2003-11-19 2008-10-09 Lucid Information Technology, Ltd. Multi-mode parallel graphics rendering system (MMPGRS) employing multiple graphics processing pipelines (GPPLS) and real-time performance data collection and analysis during the automatic control of the mode of parallel operation of said GPPLS
US7961194B2 (en) 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US7015914B1 (en) 2003-12-10 2006-03-21 Nvidia Corporation Multiple data buffers for processing graphics data
US7053901B2 (en) 2003-12-11 2006-05-30 Nvidia Corporation System and method for accelerating a special purpose processor
US7248261B1 (en) 2003-12-15 2007-07-24 Nvidia Corporation Method and apparatus to accelerate rendering of shadow effects for computer-generated images
JP3879002B2 (en) * 2003-12-26 2007-02-07 国立大学法人宇都宮大学 Self-optimizing arithmetic unit
US6975325B2 (en) 2004-01-23 2005-12-13 Ati Technologies Inc. Method and apparatus for graphics processing using state and shader management
US7259606B2 (en) 2004-01-27 2007-08-21 Nvidia Corporation Data sampling clock edge placement training for high speed GPU-memory interface
US7483034B2 (en) * 2004-02-25 2009-01-27 Siemens Medical Solutions Usa, Inc. System and method for GPU-based 3D nonrigid registration
US7289125B2 (en) 2004-02-27 2007-10-30 Nvidia Corporation Graphics device clustering with PCI-express
US7027062B2 (en) 2004-02-27 2006-04-11 Nvidia Corporation Register based queuing for texture requests
US7978194B2 (en) 2004-03-02 2011-07-12 Ati Technologies Ulc Method and apparatus for hierarchical Z buffering and stenciling
US20050195186A1 (en) 2004-03-02 2005-09-08 Ati Technologies Inc. Method and apparatus for object based visibility culling
US20050275760A1 (en) 2004-03-02 2005-12-15 Nvidia Corporation Modifying a rasterized surface, such as by trimming
US7315912B2 (en) 2004-04-01 2008-01-01 Nvidia Corporation Deadlock avoidance in a bus fabric
US7336284B2 (en) 2004-04-08 2008-02-26 Ati Technologies Inc. Two level cache memory architecture
US7265759B2 (en) * 2004-04-09 2007-09-04 Nvidia Corporation Field changeable rendering system for a computing device
US6985152B2 (en) 2004-04-23 2006-01-10 Nvidia Corporation Point-to-point bus bridging without a bridge controller
US20050237329A1 (en) 2004-04-27 2005-10-27 Nvidia Corporation GPU rendering to system memory
US7738045B2 (en) 2004-05-03 2010-06-15 Broadcom Corporation Film-mode (3:2/2:2 Pulldown) detector, method and video device
US7079156B1 (en) 2004-05-14 2006-07-18 Nvidia Corporation Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline
US7426724B2 (en) 2004-07-02 2008-09-16 Nvidia Corporation Optimized chaining of vertex and fragment programs
US7218291B2 (en) 2004-09-13 2007-05-15 Nvidia Corporation Increased scalability in the fragment shading pipeline
JP4450853B2 (en) 2004-09-16 2010-04-14 エヌヴィディア コーポレイション load distribution
US7721118B1 (en) 2004-09-27 2010-05-18 Nvidia Corporation Optimizing power and performance for multi-processor graphics processing
US7571296B2 (en) 2004-11-11 2009-08-04 Nvidia Corporation Memory controller-adaptive 1T/2T timing control
US7598958B1 (en) * 2004-11-17 2009-10-06 Nvidia Corporation Multi-chip graphics processing unit apparatus, system, and method
US8066515B2 (en) * 2004-11-17 2011-11-29 Nvidia Corporation Multiple graphics adapter connection systems
US7477256B1 (en) * 2004-11-17 2009-01-13 Nvidia Corporation Connecting graphics adapters for scalable performance
US7275123B2 (en) 2004-12-06 2007-09-25 Nvidia Corporation Method and apparatus for providing peer-to-peer data transfer within a computing environment
US7451259B2 (en) 2004-12-06 2008-11-11 Nvidia Corporation Method and apparatus for providing peer-to-peer data transfer within a computing environment
US7545380B1 (en) 2004-12-16 2009-06-09 Nvidia Corporation Sequencing of displayed images for alternate frame rendering in a multi-processor graphics system
US7372465B1 (en) * 2004-12-17 2008-05-13 Nvidia Corporation Scalable graphics processing for remote display
US20060156399A1 (en) * 2004-12-30 2006-07-13 Parmar Pankaj N System and method for implementing network security using a sequestered partition
CN101849227A (en) 2005-01-25 2010-09-29 透明信息技术有限公司 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US7924281B2 (en) 2005-03-09 2011-04-12 Ati Technologies Ulc System and method for determining illumination of a pixel by shadow planes
US7796095B2 (en) 2005-03-18 2010-09-14 Ati Technologies Ulc Display specific image processing in an integrated circuit
US7568056B2 (en) 2005-03-28 2009-07-28 Nvidia Corporation Host bus adapter that interfaces with host computer bus to multiple types of storage devices
US7681187B2 (en) 2005-03-31 2010-03-16 Nvidia Corporation Method and apparatus for register allocation in presence of hardware constraints
US7616207B1 (en) 2005-04-25 2009-11-10 Nvidia Corporation Graphics processing system including at least three bus devices
US7545101B2 (en) * 2005-05-05 2009-06-09 Leviton Manufacturing Co., Inc. Multi-zone closed loop daylight harvesting having at least one light sensor
US20080143731A1 (en) * 2005-05-24 2008-06-19 Jeffrey Cheng Video rendering across a high speed peripheral interconnect bus
US7817155B2 (en) 2005-05-24 2010-10-19 Ati Technologies Inc. Master/slave graphics adapter arrangement
US7613346B2 (en) 2005-05-27 2009-11-03 Ati Technologies, Inc. Compositing in multiple video processing unit (VPU) systems
US7539801B2 (en) 2005-05-27 2009-05-26 Ati Technologies Ulc Computing device with flexibly configurable expansion slots, and method of operation
US20060282604A1 (en) 2005-05-27 2006-12-14 Ati Technologies, Inc. Methods and apparatus for processing graphics data using multiple processing circuits
US7325086B2 (en) * 2005-12-15 2008-01-29 Via Technologies, Inc. Method and system for multiple GPU support
US7728841B1 (en) 2005-12-19 2010-06-01 Nvidia Corporation Coherent shader output for multiple targets
US7768517B2 (en) 2006-02-21 2010-08-03 Nvidia Corporation Asymmetric multi-GPU processing
US8284204B2 (en) * 2006-06-30 2012-10-09 Nokia Corporation Apparatus, method and a computer program product for providing a unified graphics pipeline for stereoscopic rendering

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of EP1687732A4 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7830387B2 (en) 2006-11-07 2010-11-09 Microsoft Corporation Parallel engine support in display driver model
JP2011513874A (en) * 2008-03-11 2011-04-28 コア ロジック，インコーポレイテッド 3D graphics processing supporting a fixed pipeline
US8319782B2 (en) 2008-07-08 2012-11-27 Dell Products, Lp Systems and methods for providing scalable parallel graphics rendering capability for information handling systems
GB2465812A (en) * 2008-12-01 2010-06-02 Imagination Tech Ltd Distributed processing for rendering 3D images
US8751658B2 (en) 2011-03-31 2014-06-10 Fujitsu Limited Allocating method, allocating apparatus, and computer product
CN110730976A (en) * 2017-06-12 2020-01-24 苹果公司 Method and system for a transaction-based display pipeline interfacing with a graphics processing unit
CN110730976B (en) * 2017-06-12 2023-12-22 苹果公司 Method and system for a transaction-based display pipeline interfacing with a graphics processing unit
CN108416836A (en) * 2018-02-06 2018-08-17 上海滚滚文化传播有限公司 It is a kind of to render the caricature production method for turning two dimensional surface by three-dimensional modeling
CN111679877A (en) * 2020-05-27 2020-09-18 浙江大华技术股份有限公司 Method and device for changing background of terminal equipment and electronic equipment
CN111679877B (en) * 2020-05-27 2023-08-29 浙江大华技术股份有限公司 Method and device for changing background of terminal equipment and electronic equipment

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