WO2005059964A2

WO2005059964A2 - Current-mode driver

Info

Publication number: WO2005059964A2
Application number: PCT/US2004/041912
Authority: WO
Inventors: Newton E. Ball
Original assignee: Microsemi Corporation
Priority date: 2003-12-16
Filing date: 2004-12-14
Publication date: 2005-06-30
Also published as: WO2005059964A3; US20050156536A1; US7239087B2; US20050162098A1; US20050156540A1; TWI308848B; US7183724B2; US20050156539A1; US7187140B2; US7265499B2; TW200524481A; WO2005059964B1

Abstract

An efficient and flexible current-mode driver delivers power to one or more light sources in a backlight system. In one application, the current-mode driver (306, 308) is configured as an inverter with an input current regulator, a non-resonant polarity-switching network, and a closely-coupled output transformer. The input current regulator can output a regulated current source in a variety of programmable wave shapes. The current-mode driver may further include a rectifier circuit (320, 322, 324, 326) and a second polarity-switching network between the closely-coupled output transformer (310) and a lamp load (312). In another application, the current-mode driver delivers power to a plurality of light sources in substantially one polarity by providing a regulated current to a network of time-sharing semiconductor switches coupled in series with different light sources coupled across each semiconductor switch.

Description

CURRENT-MODE DRIVER

Claim for Priority This application claims the benefit of priority under 35 TJ.S.C. § 119(e) of U.S. Provisional Application Number 60/530,025, filed on December 16, 2003 and entitled "Current-Mode Driver for CCFL," the entirety of which is incorporated herein by reference.

Background of the Invention Field of the Invention. The present invention relates to a current-mode driver for powering different light sources in a backlight system.

Description of the Related Art Inverter controllers for driving lamps typically regulate the voltage across each lamp and any series-connected ballast capacitor or inductor. The voltage regulation technique makes striking the lamp and regulating the lamp current difficult to achieve without costly and complex circuitry. For example, a lamp driver typically includes a starting algorithm that is different from steady state operations to light the lamp. The starting algorithm usually runs at a higher frequency and uses strike detection circuits that complicate the lamp driver design. Furthermore, gas discharge lamps have a negative resistance characteristic, and the lamp driver typically needs some degree of resonance to achieve sufficient high impedance for smooth operation after striking the lamp. Tuning the lamp with shunt capacitance across primary or secondary windings of an output transformer in the lamp driver is common.

Summary of the Invention The present invention proposes an efficient and flexible current-mode driver for delivering power to one or more light sources in a backlight system. Backlight is needed to illuminate a screen to make a visible display in liquid crystal display (LCD) applications, such as a LCD television, a desk top monitor, an automotive display, a notebook computer, a tablet computer, etc. In one embodiment, fluorescent lamps are used as the light sources in the backlight system, and a current-mode inverter generates a regulated current to drive the fluorescent lamps. The regulated current helps to generate a stable light output and to maintain a long operating life for the fluorescent lamps. The current-mode inverter advantageously operates in a single continuous operating mode for both striking and regulating power to a lamp, such as a cold cathode fluorescent lamp (CCFL). In other words, no dedicated circuits or algorithms are needed to strike the lamp. The single continuous mode of operation simplifies the number of functions supported by a current-mode controller in the current-mode inverter. In one embodiment, the current-mode controller has less than half as many functions as a voltage-rnode controller and can be implemented using approximately half as much chip area, h , addition, the curcent-mode inverter has direct control over the lamp current, thus eliminating the need for tuning or other accommodations to account for different lamps or aging of lamps. hi one embodiment, the current-mode inverter includes a current regulator, a non- resonant (or direct-drive) switching network, and a closely-coupled output transformer. The current regulator accepts a direct current (DC) voltage and outputs a regulated current. The non-resonant switching network is directly coupled to the closely-coupled output transformer and produces an alternating current (AC) driving current by periodically alternating conduction paths for the regulated current. The closely-coupled output transformer conducts the AC driving current in a primary winding and a corresponding load current in a secondary winding. The load current has a substantially identical wave shape as the AC driving current with a proportional amplitude. Thus, the current-mode iirverter has direct control over the load current. i one embodiment, a current-mode inverter (e.g., a multi-stage switching inverter) has two switching stages to drive a lamp load in a backlight system. The multi-stage switching inverter includes a first switching stage, a rectifier circuit and a second switching stage. The first switching stage operates at relatively high frequency to periodically couple an input current (e.g., a DC current) through a primary winding of a transformer in alternating sense to generate a primary AC driving current. The secondary winding of the transformer conducts a proportional secondary AC driving current with a relatively high AC voltage. The rectifier circuit is coupled across the secondary winding to generate a relatively high voltage and substantially DC current source. The second switching stage is coupled between the rectifier circuit and a lamp load. The second switching stage includes semiconductor switches directly coupled to the lamp load and operates at relatively low frequency to generate an AC lamp current through the lamp load. In one embodiment, the AC lamp current has a substantially square wave shape. The relatively high frequency operation of the first switching stage (or power switching stage) advantageously reduces size of components (e.g., the transformer). In one embodiment, the first switching stage operates in a frequency range of 100 kilohertz to 4 Megahertz, i one application, the first switching stage operates at approximately 2 Megahertz. The relatively low frequency operation of the second switching stage (or polarity switching stage) advantageously improves efficiency (e.g., by reducing switching loss or by reducing crest factor in load current). In one embodiment, the second switching stage operates in a frequency range of 100 hertz to 4 kilohertz. In one application, the second switching stage operates at approximately 400 hertz. h one embodiment, a controller for a current-mode inverter outputs a current profile signal to an input current regulator. The input current regulator uses the current profile signal to produce a regulated current with a substantially identical wave shape and proportional amplitude. The current profile signal can be programmed for a variety of wave shapes (e.g., sine wave, square wave, trapezoidal wave, triangular wave) and amplitudes to optimize efficiency or to reduce electromagnetic interference (EMI) for specific applications. In one embodiment, the controller includes a clock generator, a current profile generator, and a register state machine to generate the current profile signal. The clock generator outputs a periodic timing (e.g., triangular) waveform, and the register state machine controls the operation of the current profile generator with reference to the periodic timing waveform. hi one embodiment, the current profile generator uses at least two input control signals (e.g., BRITE-W, BRITE-H) and a slope capacitor to determine the wave shape and amplitude of the current profile signal. The amplitude of the current profile signal is periodically set to zero during a zero (or reset) state near the beginning of each cycle of a triangular timing waveform. When the voltage of the triangular timing waveform exceeds the voltage of the first input control signal (e.g., BRITE-W), the current profile signal begins a rising state with its amplitude increasing at a predetermined rising rate. The slope capacitor charges during the rising state. When the voltage across the charging slope capacitor exceeds the voltage of the second input control signal (e.g., BRITE-H), the slope capacitor stops charging. The current profile signal also stops rising in amplitude and begins a plateau state by holding its amplitude at a substantially constant level. The voltage of the triangular timing waveform is noted at or near the beginning of the plateau state. The plateau state ends and the current profile signal begins a falling state in which its amplitude starts fall at a predetermined falling rate at or near the time that the voltage of the triangular timing waveform becomes less than the noted voltage at the beginning of the plateau state. The slope capacitor discharges during the falling state. The slope capacitor finishes discharging and the amplitude of the current profile signal returns to zero at approximately the time that the voltage of the triangular timing waveform becomes less than the first input control signal. The current profile generator advantageously allows for selectable rise and fall slopes for the current profile signal. For example, the rise and fall slopes are determined by the two input control signals (BRITE-W, BRITE-H), the slope capacitor and an optional slope resistor. In one embodiment, the rise and fall times are programmed to be less than one microsecond for a current profile signal with a square wave shape, hi another embodiment, the rise and fall times exceed one microsecond for a current profile signal with a trapezoidal wave shape, h yet another embodiment, the current profile signal has a special trapezoidal wave shape that substantially follows the wave shape of the triangular timing waveform with its amplitude clipped at 2/3 of the peak amplitude of the triangular timing waveform. The special trapezoidal waveform can be subsequently filtered by small reactive components to produce a sine wave with reduced harmonics (e.g., substantially no harmonics less than the 5^th harmonic). In one embodiment, a current-mode driver delivers power to a plurality of light sources in a backlight system by providing a regulated current to a network of semiconductor switches coupled in series and the light sources coupled across the respective semiconductor switches. Each of the semiconductor switches individually closes to isolate its associated light source from the regulated current or selectively opens to allow the associated load to conduct the regulated current, hi one embodiment, the network of semiconductor switches uses a time sharing technique to selectively provide the regulated current to different portions of an array of light emitting diodes (LEDs) used to backlight a LCD. For example, a string of series-connected LEDs corresponding to a row in the array is coupled across each semiconductor switch. The semiconductor switches periodically close in sequential order to minimize backlight in portions of the LCD that is currently updating its image. The time sharing technique advantageously allows a single current source to power banks (or arrays) of series-coupled light sources. ' It should be noted that the applications of the current-mode drivers described above are not limited to lamps or LEDs. The current-mode drivers can also be applied to other types of loads in which current-mode operation or direct control of load current is desired. For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or earned out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

Brief Description of the Drawings Figure 1 is a simplified block diagram of one embodiment of a current-mode inverter. Figure 2A is a simplified schematic of one embodiment of a current-mode inverter with a push-pull polarity-switching stage. Figure 2B is a simplified schematic of another embodiment of a current-mode inverter with a full-bridge polarity-switching stage. Figure 3 A is a simplified schematic of one embodiment of a current-mode inverter with two switching stages. Figure 3B is a simplified schematic of another embodiment of a current-mode inverter with two switching stages. Figure 4 is a simplified block diagram of one embodiment of a controller for a current-mode inverter. Figure 5 illustrates timing waveforms associated with the controller of Figure 4. Figure 6 is one embodiment of a flow chart to illustrate steps in generating a current profile signal by the controller of Figure 4. Figure 7 illustrates a proposed trapezoidal waveform that contains no harmonics lower than the fifth harmonic, so that it can readily be filtered to have a relatively low Total Harmonic Distortion (THD). Figure 8 is a simplified schematic of one embodiment of a current-mode driver that drives multiple loads using a time sharing technique.

Detailed Description of the Embodiments Embodiments of the present invention will be described hereinafter with reference to the drawings. Figure 1 is a simplified block diagram of one embodiment of a current- mode inverter. The current-mode inverter includes an input current regulator 100, a polarity-switching and transformer network (or polarity reversing stage) 102, a feedback circuit 104, and a current regulator controller 106. The input current regulator 100 accepts a DC power source (e.g., a regulated or unregulated DC voltage) and generates a regulated current for the polarity-switching and transformer network 102. The polarity-switching and transformer network 102 includes semiconductor switches, such as metal-oxide- semiconductor field-effect-transistors (MOSFETs), directly coupled to a primary winding of a closely-coupled transformer. The semiconductor switches are controlled by a controller (e.g., a pulse width modulator) to periodically couple the regulated current through the primary winding in alternate sense, thereby generating a primary AC current through the primary winding. A corresponding secondary AC current is generated in a secondary winding of the closely-coupled transformer. The secondary AC current is substantially the current conducted by a lamp load coupled to the secondary winding. In one embodiment, the feedback circuit 104 is coupled to a primary side of the polarity-switching and transformer network 102 to sense the primary AC current. The feedback circuit generates a feedback signal (e.g., a feedback voltage) indicative of the level of the primary AC current. In one embodiment, the feedback signal (I-SENSE) is provided to the current regulator controller 106 for comparison with a brightness control signal (e.g., a voltage representative of a desired lamp current) and outputs a current control signal (V- CONTROL) to the input current regulator 100. The brightness control signal may also be referred to as the current reference or target current signal. The target current signal can be substantially constant or a periodic waveform generated by a current profile generator which is discussed in further details below. The input current regulator 100 controls the level and shape of the regulated current based on the target current signal. The current conducted by the lamp load is directly proportional to the regulated current with its polarity periodically reversed. Thus, the target cunent signal controls the current conducted by the lamp load and its corresponding brightness. For example, the current delivered to the primary winding of the closely- coupled transformer is regulated to substantially follow the wave shape of the target current signal, using the closed loop feedback technique described above. The input current regulator 100 can operate as a hysteretic' pulse width modulation (PWM) switching regulator, a clocked PWM switching regulator, or a linear current regulator. Because the closely-coupled transformer is a current transformer as well as a voltage transformer, the secondary AC current (or lamp current) conducted by the secondary winding of the closely-coupled transformer is related to the primary AC current (or regulated AC current) through the primary winding by the reciprocal of the transfonner turns ratio. The closely-coupled transfonner has a relatively higher ratio of magnetization inductance to leakage inductance (e.g., 300:1) in comparison to ratios (e.g., 10:1) for a loosely-coupled transformer typically used in resonant drivers. In one embodiment, the ratio of the magnetization inductance (or open inductance) to leakage inductance (or shorted inductance) is greater than 30:1 (e.g., 3000:1). Cunent conducted by the secondary winding of the closely-coupled transfonner advantageously has substantially the same wave shape as cunent conducted by the primary winding with a proportional amplitude detennined by the transformer turns ratio. Thus, the lamp cunent can be directly controlled by coupling the feedback circuit 104 to the primary side of the polarity-switching and transformer network 102 and sensing the cunent conducted by the primary winding of the closely-coupled transformer. The proposed primary-side monitoring advantageously eliminates the need for a common ground reference between the primary and secondary sides of the closely-coupled transformer for accurate sensing of the load cunent. That is, lamps coupled to the secondary side of the closely-coupled transfonner can advantageously operate in floating configurations. Alternately, any single point in the secondary side or among the lamps may be connected to ground without affecting the cunent-mode inverter functions. However, a ground connection may affect stray cunents. The cunent-mode inverter directly controls lamp ignition by direct regulation of the lamp cunent. The cunent-mode inverter reliably ignites a lamp of any size or formulation over a wide temperature range and aging. The secondary winding of the closely-coupled transformer operates to automatically produce a sufficient voltage across the lamp to conduct the desired lamp cunent. The output impedance of the cunent-mode inverter is sufficiently high for stable operations under most conditions. The transition from lamp striking to nonnal operation is smooth with no changes in control techniques. The cunent-mode inverter accurately regulates the lamp cunent against supply voltage variations, wide temperature ranges and lamp aging, hi one embodiment, the cunent-mode inverter tolerates 5:1 variations in the load impedance and provides input line voltage compliance over more than a 2:1 range. Thus, the cunent-mode inverter can be adapted to drive many differently sized backlight units. Figure 2A is a simplified schematic of one embodiment of a cunent-mode inverter with a push-pull polarity-switching stage. The cunent-mode inverter includes a switching cunent regulator 218, a push-pull polarity-switching network, and a closely-coupled (or tightly-coupled) transformer 210. In one embodiment, the switching cunent regulator 218 includes a cunent switch (e.g., a P-FET) 200, a series inductor 202 and a catch diode 204. The cunent switch 200 is coupled between an input supply (DC POWER) and a first tenninal of the series inductor 202. The catch diode 204 is coupled between the first tenninal of the series inductor 202 and a ground return. A second terminal of the series inductor 202 outputs a regulated cunent (I-REG). In one embodiment, the push-pull polarity-switching network includes two semiconductor switches (e.g., N-FETs) 206, 208 with drain tenninals coupled to respective opposite terminals of a primary winding of the closely-coupled transformer 210. Source terminals of the semiconductor switches 206, 208 are commonly comiected and coupled to ground via a sensing resistor 214. The regulated cunent at the second terminal of the series inductor 202 is applied to a center tap of the closely-coupled transformer 210. A controller (not shown) outputs driving signals (A, B) to control the semiconductor switches 206, 208 in generating a primary AC cunent in the primary winding of the closely- coupled transformer 210. For example, the semiconductor switches 206, 208 alternately conduct to reverse the direction (or polarity) of the regulated cunent through the primary winding to generate the primary AC cunent. A conesponding secondary AC cunent flows through a secondary winding of the closely-coupled transformer 210 and delivers power to a lamp load 212 coupled across the secondary winding. The secondary AC cunent has a substantially identical wave shape as the primary AC cunent and proportional amplitude. The on states of the semiconductor switches 206, 208 overlap to continuously provide at least one cunent path for the regulated cunent. In one embodiment, both semiconductor switches 206, 208 remain on to stop generating the primary AC cunent, thereby disconnecting power to the lamp load 212 coupled across the secondary winding of the closely-coupled transformer 210. For example, power is not provided to the lamp load 212 in the event of a shorted lamp, a missing lamp or other fault conditions. Other polarity-switching topologies may also be used to generate the primary AC cunent. For example, a full-bridge topology is shown in Figure 2B. The disclosed polarity-switching topologies advantageously do not include reactance components for non- resonant operation. Semiconductor switches are directly coupled to closely-coupled transfonners. The series inductor 202 at the output of the switching cunent regulator 218 provides a high impedance upstream of the closely-coupled transfonner 210 and push-pull polarity- switching network. The high impedance is refened by the closely-coupled transfonner 210 as an even higher impedance as seen by the lamp load 212 coupled across the secondary winding of the closely-coupled transfonner 210. This changes the nature of lamp ignition from a discontinuous "strike" phenomenon to a smooth event. For example, the voltage across the secondary winding of the closely-coupled transformer 210 automatically increases to ignite the lamp load 212. The cunent-mode inverter advantageously operates in a single continuous mode (e.g., at fixed frequencies) for striking and regulating power to the lamp load. The voltage across the secondary winding of the closely-coupled transformer 210 automatically produces sufficient voltage for the lamp load 212 to conduct the desired cunent. The lamp load 212 can be one lamp or a network (or anay) of lamps. The lamp load 212 conducts the secondary AC cunent (or lamp cunent) which has substantially the same wave shape as the primary AC cunent with proportional amplitude. In one embodiment, the sensing (or shunt) resistor 214 monitors the primary AC cunent, thereby monitoring the lamp cunent. A feedback voltage (I-SENSE) across the sensing resistor 214 can be used for brightness control of the lamp load 212. For example, the feedback voltage can be used to control duty cycle or burst mode durations in the switching cunent regulator 218 or in the push-pull polarity switching network. A combination of adjustments may be made to provide a wide dimming range, which is helpful in automotive applications that compensate for wide variations in temperature and ambient light. In one embodiment, the feedback voltage is provided to a comparator circuit 216. The comparator circuit 216 may attenuate, rectify or filter the feedback voltage before comparison with a target cunent signal (TARGET CURRENT). The target cunent signal can be substantially constant with unpredictable variations or can be a periodic waveform, hi one embodiment, the switching cunent regulator 218 operates in a hysteretic mode, and the comparator circuit 216 outputs a control signal to the cunent switch 200 to adjust the level of the regulated cunent in accordance with the target cunent signal, hi one embodiment, the regulated cunent follows the wave shape of the target cunent signal. The hysteretic mode advantageously does not use a clock and is relatively simple to implement. However, other operating modes, as discussed above, are also possible. The closely-coupled transformer 210 is a power transformer and is suitable for driving large anays of large lamps. The closely-coupled characteristic also prevents overshoots in voltages on the semiconductor switches 206, 208. In one embodiment, the semiconductor switches 206. 208 are both on (e.g., closed or conducting) during an idle state. When the semiconductor switches 206, 208 are both on, no net cunent flows through the primary winding of the closely-coupled transformer 210. The semiconductor switches 206, 208 may conduct an idle cunent limited by the switching cunent regulator 218. However, no cunent is provided to the lamp load 212 in the idle state. The lamp load 212 is advantageously short-safe. That is, shorting the lamp load 212 does not result in excessive cunent or damage to the cunent-mode inverter. The switching regulator 218 can provide fault protection in the event of a missing or faulty lamp load by limiting the regulated cunent. As discussed above, the lamp load 212 may include more than one lamp (e.g., an anay of CCFLs) for backlighting a LCD. The lamp load 212 can be ananged in a variety of configurations, which advantageously allows large anay of lamps to run from a single controller and a single power transformer (i.e., the closely-coupled transformer 210) in the cunent-mode inverter. In one embodiment, multiple lamps are coupled in series across the secondary winding of the closely-coupled transfonner 210. Furthermore, the lamp load 212 may include optional capacitors coupled in series with the lamps or balancing transformers for cunent balancing groups of lamps. In a first embodiment, the lamp load includes a plurality of balancing (or load) transformers with primary windings coupled in series across the secondary winding of the closely-coupled transfonner 210 and secondary windings separately coupled to one lamp or multiple lamps, hi a second embodiment, the lamp load 212 includes a plurality of balancing transformers in a ring configuration. Secondary windings of the balancing transformers are coupled in series to form a closed loop in the ring configuration, while primary windings are coupled to different lamps to form parallel primary winding-lamp combinations across the secondary winding of the closely-coupled transformer 210. Further details of this second embodiment of the lamp load 212 are discussed in commonly-owned pending U.S. Application Number 10/958,668, entitled "A Cunent Sharing Scheme for Multiple CCF Lamp Operation," which is hereby incorporated by reference herein. hi a third embodiment, the lamp load 212 includes balancing transfonners (or two- way transformers) to couple multiple lamps in a variety of tree topologies for balancing cunent among the multiple lamps. For example, the two-way transformers can be ananged in a simple tree structure to split a single output cunent into multiple substantially equal cunents for powering the multiple lamps. The two-way transformers can be coupled on one end of the lamps or split between both ends of the lamps. Further details of this third embodiment of the lamp load 212 are discussed in commonly-owned pending U.S. Application Number 10/970,243, entitled "Systems and Methods for a Transformer Configuration with a Tree Topology for Cunent Balancing in Gas Discharge Lamps," which is hereby incorporated by reference herein. Figure 2B illustrates alternate embodiments for circuits shown in Figure 2A. The cunent-mode inverter of Figure 2B illustrates an alternate embodiment of a switching cunent regulator 230 which replaces the catch diode 204 with a semiconductor switch 232. An alternate embodiment of a comparator circuit 234 outputs two PWM control signals to respectively drive the cunent switch 200 and the semiconductor 232. Finally, an alternate embodiment of the polarity-switching stage is illustrated with four semiconductor switches 220, 222, 224, 226 in a full-bridge configuration. In the embodiment of Figure 2B, the polarity-switching stage includes the four semiconductor switches 220, 222, 224, 226 directly coupled to a primary winding of a transfonner (e.g., a closely-coupled transfonner) 228 in a full-bridge configuration for non- resonant operation. The four semiconductor switches 220, 222, 224, 226 are controlled by respective gate control signals (A, B, C, D) coupled to their gate terminals. The gate control signals can be provided by a PWM controller, which is not shown for clarity of illustration. hi the embodiment of Figure 2B, the top semiconductor switches 220, 226 are p- type FETs (i.e., P-FETs) with respective source terminals commonly connected to an output of the switching cunent regulator 230. The top semiconductor switches 220, 226 can alternately be n-type FETs (i.e., N-FETs) with respective drain terminals commonly connected to the output of the switching cunent regulator 230 and with suitable adjustments to the levels of the respective gate control signals (A, D) for driving N-FETs. In the embodiment of Figure 2B, the bottom semiconductor switches 222, 224 are N-FETs with respective source terminals commonly connected and coupled through the sensing resistor 214 to ground. The drain terminals of semiconductor switches 220, 222 are directly coupled to one terminal of the primary winding of the transfonner 228. The drain terminals of the semiconductor switches 224, 226 are directly coupled to an opposite terminal of the primary winding of the transformer 228. The switching cunent regulator 230 outputs a regulated cunent (I-REG), and the semiconductor switches 220, 222, 224, 226 alternately conduct in pairs to couple the regulated cunent through the primary winding of the transformer 228 in alternate sense to generate a primary AC cunent. For example, the first pair of semiconductor switches 220, 224 are closed (or on) while the second pair of semiconductor switches 222, 226 are opened (or off) to allow the primary winding to conduct the regulated cunent in a first direction (or polarity). Then, the first pair of semiconductor switches 220, 224 are opened while the second pair of semiconductor switches 222, 226 are closed to allow the primary winding to conduct the regulated cunent in a second polarity. The primary AC cunent through the primary winding results from periodically alternating the conduction states between the first pair of semiconductor switches 220, 224 and the second pair of semiconductor switches 222, 226. A conesponding secondary AC cunent flows through a secondary winding of the transformer 228 to power the lamp load 212 coupled across the secondary winding, h one embodiment, the conduction (or on) states between the first pair of semiconductor switches 220, 224 and the second pair of semiconductor switches 224, 226 overlap between alternating states to continuously provided a cunent path for the regulated cunent to ground. Both pairs of semiconductor switches 220, 222, 224, 226 remain on in an inactive state to stop the primary winding from conducting cunent, The inactive state occurs when power to the lamp load 212 is not desired (e.g., to turn off the lamp load or in case of a missing or faulty lamp load). Figure 3A is a simplified schematic of one embodiment of a two-stage cunent- mode inverter. The simplified schematic of Figure 3A is substantially similar to the simplified schematic of Figure 2A with an additional rectifier circuit and a full-bridge high- level switching network. Thus, the two-stage cunent-mode inverter has two switching stages. The first switching stage, a push-pull switching network, is coupled on a primary side of a transfonner (e.g., a closely-coupled transfonner) 310. The first switching stage includes two semiconductor switches (e.g., N-FETs) 306, 308 with respective drain tenninals coupled to opposite terminals of a primary winding of the transformer 310. Source terminals of the semiconductor switches 306, 308 are commonly connected and coupled to ground via a sensing resistor 314. The voltage across the sensing resistor 314 is provided as a feedback signal (I-SENSE) to a non-inverting input of a comparator circuit 316. An input control signal (TARGET CURRENT) is provided to an inverting input of the comparator circuit 316. The comparator circuit 316 controls a switching cunent regulator 318 to generate a regulated current (I-REG). The switching cunent regulator 318 is substantially similar to the switching cunent regulator 218 shown in Figure 2 A with a conesponding cunent switch 300, series inductor 302 and catch diode 304. In one embodiment, the regulated cunent is substantially constant during steady state operation with its amplitude determined by the input control signal (TARGET CURRENT). The regulated cunent is provided to a center tap of the transformer 310. The semiconductor switches 306, 308 alternately conduct to reverse the direction of the regulated cunent through the primary winding to generate a primary square wave driving cunent. A secondary winding of the transformer 310 conducts a secondary square wave driving cunent with a proportional amplitude and a relatively high AC voltage. The rectifier circuit is coupled across the secondary winding of the transformer 310 to rectify the secondary square wave driving cunent into a substantially DC cunent source at relatively high voltage. In the embodiment shown in Figure 3 A, the rectifier circuit is a full-wave bridge rectifier implemented by four diodes 320, 322, 324, 326. The second switching stage (i.e., the full-bridge high-level switching network) is coupled between outputs of the rectifier circuit and a lamp load 312. The second switching stage includes four semiconductor switches (SI, S2, S3, S4) 328, 330, 332, 334 directly coupled to the lamp load 312 for non-resonant operation. The semiconductor switches 328, 330, 332, 334 alternately conduct in pairs (e.g., SI and S3, S2 and S4) to generate a square wave load cunent (or lamp cunent) through the lamp load 312. The first switching stage advantageously operates at relatively high frequencies to generate a high voltage AC cunent power across the secondary winding of the transformer 310. High frequency operations (e.g., 2 Megahertz) reduce the size of magnetic components (e.g., the series inductor 302 and the transformer 310). hi one embodiment, the first switching stage operates in a frequency range of 100 kilohertz to 4 Megahertz. The second switching stage advantageously operations at relatively low frequencies (e.g., 250 hertz) to generate the lamp cunent directly across the lamp load 312. Low frequency operations reduce switching loss, which is proportional to frequency, and stray cunents from the lamp load 312 to chassis. In one embodiment, the second switching stage operates in a frequency range of 100 hertz to 4 kilohertz. In one application, the second switching stage operates at approximately 400 hertz. Furthermore, the low frequency operations of the second switching stage improve luminous efficiency by reducing lamp cunent crest factor closer to an ideal value of one. The lamp crest factor is defined as a ratio of the peak lamp cunent level to a root-mean- square (RMS) lamp cunent level. The lamp crest factor improves when rise and fall times as percentages of the period decrease for the lamp cunent. The rise and fall times of the lamp cunent are substantially limited by the transition times of the semiconductor switches 328, 330, 332, 334 and are substantially the same across frequencies. Thus, lower frequency provides a longer period and results in better lamp cunent crest factor. In one embodiment, the semiconductor switches 306, 308 in the first switching stage operate with overlapping closures to facilitate stable cunent-mode operations. The semiconductor switches 328, 330, 332, 334 can also operate with overlapping closures. In one embodiment, the semiconductor switches 306, 308 of the first switching stage are continuously closed during an idle state in which power is not provided to the lamp load 312. The semiconductor switches 328, 330, 332, 334 can also be closed during the idle state. Figure 3B is a simplified schematic of another embodiment of a cunent-mode inverter with two switching stages. The two-stage cu ent-mode inverter of Figure 3B is substantially similar to the two-stage cunent-mode inverter of Figure 3A with the exceptions that the first switching stage uses a full-bridge topology instead of the push-pull topology and the rectifier circuit includes a pair of half-wave voltage doublers 346, 348 instead of the full-wave bridge rectifier. The following discussion focuses on these differences. hi one embodiment, the first switching stage uses four transistors 336, 338, 340 342 to implement the full-bridge topology. A pair of p-type transistors 336, 342 is coupled between the output of the switching cunent regulator 318 and respective ends of a primary winding of a transformer 344. A pair of n-type transistors 338, 340 is coupled between the respective ends of the primary winding and a feedback terminal. The feedback tenninal is coupled to ground via the sensing resistor 314. The transistors 336, 338, 340 342 alternately conduct to couple the regulated cunent in alternate sense through the primary winding to generate a primary AC cunent. In one embodiment, the regulated cunent is substantially constant, and the primary AC cunent has a substantially square wave shape and is associated with relatively low voltage amplitude. A conesponding secondary AC cunent flows through a secondary winding of the transformer 344. The secondary AC cunent follows the wave shape of the primary AC cunent and is associated with relatively high voltage amplitude with a peak voltage of Vx. The two half-wave voltage doublers 346, 348 are coupled across the secondary winding to rectify the secondary AC cunent into a high voltage DC cunent source for the second switching stage. The voltage amplitude across the rectifier outputs associated with the high voltage DC cunent source is approximately four times the peak voltage associated with the secondary AC cunent. hi one embodiment, each of the half- wave doublers 346, 348 includes two diodes, a charging capacitor, and an output capacitor. For example, the first half-wave doubler (or positive doubler) 346 includes a first charging capacitor 350, a first output capacitor 352, a first diode 354 and a second diode 356. The first charging capacitor 350 is coupled between a first (or high-side) tenninal of the secondary winding and an anode of the first diode 354. A cathode of the first diode 354 is coupled to a first (or positive) output of the rectifier circuit. The second diode 356 has an anode coupled to a second (or low-side) tenninal of the secondary winding and a cathode coupled to the anode of the first diode 354. The first output capacitor 352 is coupled between the low-side terminal of the secondary winding and the positive output of the rectifier circuit. During a negative cycle of the secondary AC cunent, with respect to the high-side tenninal of the secondary winding, the first charging capacitor 350 is charged through the second diode 356. During a positive cycle of the secondary AC cunent, the voltage across the first charging capacitor 350 adds in phase with the voltage across the secondary winding and charges the first output capacitor 352 to a positive potential that is about twice the peak amplitude across the secondary winding (e.g., +2Vx with respect to the low-side terminal of the secondary winding) . The second half-wave doubler (or negative doubler) 348 includes a second charging capacitor 358, a second output capacitor 360, a third diode 362 and a fourth diode 364. The second charging capacitor 358 is coupled between the high-side terminal of the secondary winding and a cathode of the third diode 362. An anode of the third diode 362 is coupled to a second (or negative) output of the rectifier circuit. The fourth diode 364 has a cathode coupled to the low-side tenninal of the secondary winding and an anode coupled to the cathode of the third diode 362. The second output capacitor 360 is coupled between the low-side terminal of the secondary winding and the negative output of the rectifier circuit. The negative doubler 348 works in substantially the same manner as the positive doubler 346 but in opposite phase to produce a negative potential that is twice the peak amplitude across the secondary winding (e.g., -2Vx with respect to the low-side terminal of the secondary winding). The negative potential is provided at the negative output of the rectifier circuit. The outputs of the rectifier circuit (or the half- wave doublers 346, 348) are coupled to the lamp load 312 via the second switching stage. In one embodiment, the output capacitors 352, 360 of the half-wave doublers 346, 348 can be eliminated if there is sufficient capacitance in the lamp load 312. A ground reference may be optionally connected at various points between the secondary winding of the transformer 344 and the lamp load 312. In one embodiment, the ground reference is connected to the low-side terminal of the secondary winding for balanced rectifier outputs to drive a floating lamp load 312. The balanced rectifier outputs (e.g., +2Vx at the positive output and -2Vx at the negative output) advantageously minimizes the highest potential in the current-mode inverter to be approximately half of the amplitude across the lamp load 312 for safer operations and less corona discharge from the lamps to chassis. hi another embodiment, the ground reference is connected to the negative output of the rectifier circuit for a single-ended connection to the lamp load 312. In yet another embodiment, the ground reference is connected to one terminal of the lamp load 312.

Similar ground connections can also be made in the cunent-mode inverters illustrated in

Figures 2A, 2B and 3A. In one embodiment, the switching cunent regulator 318, the first switching stage and the second switching stage are advantageously controlled by a common controller. The control signals for the first and second switching stages can be phase-locked or can be independently generated with no phase relationship. The common controller can be implemented in an integrated circuit. The cunent-mode inverters described above offer wide dimming ranges. Multiple dimming (or brightness control) methods (e.g., cunent amplitude adjustments, pulse width variations, burst mode) are available for flexible control and to maintain a desired brightness over aging, temperature and ambient light variations. For example, dimming can be ^■ achieved by adjusting the level of the regulated cunent. One method varies the reference cunent (or the target cunent) to vary the amplitude of the regulated cunent at the output of the switching cunent regulator 318. Another method varies the switching duty cycle in the switching cunent regulator 318 to vary the average amplitude of the regulated cunent. Dimming can also be achieved by changing the switching duty cycle in any of the switching stages between the switching cunent regulator 318 and the lamp load 312. Moreover, dimming can be implemented by operating the switching cunent regulator 318 or any of the switching stages in burst mode and varying the burst durations, hi one embodiment, a combination of dimming methods is used for an expanded dimming range. Figure 4 is a simplified block diagram of one embodiment of a controller for a cunent-mode inverter. The controller advantageously includes a cunent profile generator

406 to allow the cunent-mode inverter to synthesize flexible cunent waveforms (e.g., programmable lamp cunent amplitude and wave shaping). In one embodiment, the controller also includes a clock generator 400 and a register state machine 402. The clock generator 400 outputs a triangular timing waveform (TRI) with oscillation characteristics determined by a resistor (R_OSC) and a capacitor (C_OSC). The triangular timing wavefonn is provided to the register state machine 402, which outputs signals to control the operations of the cunent profile generator 406. hi one embodiment, the cunent profile generator 406 produces a profile signal

(PROFILE-OUT) in a variety of programmable waveform shapes defined by at least a slope capacitor (C-SLOPE), an optional slope resistor (R-SLOPE), and two input control signals

(BRITE-W, BRITE-H). For example, the slope capacitor and input control signals define a rising slope, a plateau, and a falling slope of the profile signal. hi one embodiment, the profile signal is provided to an input cunent regulator to generate a regulated cunent with the programmed waveform shape for the cunent-mode inverter, hi one application, an optional attenuation circuit 418 conditions the profile signal for comparison with a feedback signal (I-SENSE) by a comparator circuit 426 that outputs a driving signal (V-CONTROL) to the input cunent regulator. For example, the optional attenuation circuit 418 includes two resistors 420, 422 configured as a voltage-divider to reduce the amplitude range of the profile signal to match the amplitude range of the feedback signal. The feedback signal may be representative of a load cunent, and the conditioned profile signal (TARGET CURRENT) represents the desired load cunent. The attenuation circuit 418 optionally includes a pre-emphasis capacitor 424 inserted between the resistor 422 and ground to pre-emphasize the profile signal. The pre-emphasis capacitor 424 is periodically discharged by an output signal (DUMP) from the cunent profile generator 406 and provides an upslope to the plateau sections of the profile signal to compensate for magnetization cunent in a transformer of the cunent-mode inverter. hi one embodiment, the comparator circuit 426 is a hysteretic PWM circuit that controls the input cunent regulator to produce a regulated cunent that follows the shape of the conditioned profile signal. The regulated cunent is coupled to a lamp load without significant distortion and in alternate sense using a non-resonant switching network and a high bandwidth, closely-coupled transfonner. Thus, the cunent profile generator 406 advantageously allows direct control of the lamp cunent wave shape, thereby direct control of lamp cunent crest factor. The lamp cunent crest factor can be optimized to increase luminous efficiency of a lamp while extending the lamp's useful life. hi one embodiment, the controller further includes a polarity-switching generator

(PWM/POLARITY GATING) 404. The polarity-switching generator 404 produces driving signals (A, B, C, D) for the non-resonant switching network with reference to the triangular timing wavefonn. In one application, the polarity-switching generator 404 is controlled by signals from the register state machine 402. The outputs of the polarity-switching generator 404 may be provided to level-shifters or buffer circuits 408, 410, 412, 414 to provide appropriate driving levels to semiconductor switches in the non-resonant switching network. hi yet another embodiment, the controller includes a fault processor 416. The fault processor 416 monitors a variety of feedback signals to detennine if a fault exists and outputs a fault signal (FLT) to the polarity-switching generator 404 to implement a shutdown sequence. For example, the fault processor 416 monitors a voltage feedback signal (V-SENSE) for occunence of open lamp conditions after striking. The fault processor 416 also monitors the cunent feedback signal (I-SENSE) and the profile signal to determine possible faults in the cunent regulator. The fault processor 416 can monitor other signals to generate the fault signal and initiate the shut-down sequence. The shut-down sequence includes turning on the semiconductor switches in the non-resonant switching network to stop the deliver of power to the load. The shut-down sequence may also include reducing the regulated cunent to substantially zero. Figure 5 illustrates timing waveforms associated with one embodiment for generating a profile signal using the cunent profile generator 406. A first graph 500 shows a triangular timing waveform (TRI). A second graph 502 shows a first logic waveform (I- GATE). A third graph 504 shows a second logic waveform (DUMP). As discussed above, the second logic waveform is used to periodically discharge the optional pre-emphasis capacitor 424. The third graph 504 shows that the second logic wavefonn is a nareow- width signal that activates for a predetennined duration (Tmin) near each negative peak of the triangular timing wavefonn. In an alternate embodiment, the second logic wavefonn substantially follows the first logic waveform, and discharges the optional pre-emphasis capacitor 424 when the first logic wavefonn is low. A fourth graphs 506 shows a profile signal (PROFILE-OUT). A fifth graph 508 and a sixth graph 510 show driving signals (A, B) for a switching network. The triangular timing wavefonn is used a time base (or a reference waveform) for generating the profile signal and the driving signals. Two substantially identical wave shapes in the profile signal are produced for every cycle of the driving signals. In one embodiment, each cycle of the driving signals conesponds to a cycle in the load cunent. Each wave shape in the profile signal is symmetric about the positive peaks of the triangular timing waveform. The wave shapes of the profile signal have multiple, user programmable, features (e.g., frequency, pulse width, pulse height, rise and fall slopes, etc.). The frequency can be set by adjusting the frequency of the triangular timing wavefonn, which is controlled by the oscillation resistor (R_OSC) and the oscillation capacitor (C_OSC). The pulse width can be set by a first control signal (BRITE-W). An inversion of the first control signal is shown overlaying the triangular timing waveform as graph 512. The first logic waveform has logic transitions at times when the triangular timing waveform crosses the inverted version of the first control signal and represents the pulse width of the profile signal. In one embodiment, the pulse width is limited to be no greater than 95% of the period. The pulse height can be set by a second control signals (BRITE-H). hi one embodiment, the pulse height is limited to range from near zero to about 2/3 of the amplitude of the triangular timing waveform (e.g., approximately zero to 2.5 volts). The rise and fall slopes can be set by the slope capacitor (C-SLOPE) and optionally the slope resistor (R-SLOPE). Refening to the graph 506 of Figure 5, the profile signal is synthesized from three straight lines comprising a leading edge, a plateau, and a falling edge. The leading edge begins when the rising portion of the triangular timing waveform crosses the inverted version of the first control signal (e.g., at time tl). At this time, a positive slope cunent source charges the slope capacitor with a predetermined cunent or a cunent set by the optional slope resistor. When the voltage across the slope capacitor reaches the level of the second control signal (e.g., at time t2), the positive slope cunent source is turned off and the plateau begins. The level (HI) of the triangular timing wavefonn at time t2 is noted. When the falling portion of the triangular timing wavefonn crosses the noted level (e.g., at time t3), the falling edge begins to produce a symmetrical wave shape with respect to the positive peak of the triangular timing wavefonn. In one embodiment in which the profile signal controls a regulated cunent for powering a lamp, the first control signal and the second control signal can be independently adjusted to vary the brightness of the lamp. For example, the pulse width of the profile signal increases with increasing level of the first control signal, and the amplitude of the profile signal increases with increasing level of the second control signal. The graph 506 shows two relatively bigger pulses generated with the first control signal and the second control signal at one level followed by two relatively smaller pulses generated with the first control signal and the second control signal at lower levels. As discussed above, every two substantially identical cycles of the profile signal conesponds to one cycle of AC cunent through the lamp. Polarity reversing for every other cycle is accomplished in a polarity-switching network. The graphs 508, 510 show driving signals (A, B) to semiconductor switches in one embodiment of the polarity-switching network. The driving signals are alternately active and change states with overlapping "on" times between each cycle of the profile signal. For example, the first driving signal is active (high) while the second driving signal is inactive (or low) during the first cycle from time tl to time t4. The driving signals then change states before the next cycle. The inactive driving signal changes before the active driving signal to provide a null state between cycles with both driving signals active. In one embodiment, the inactive driving signal changes to an active driving state at about the negative peak of the triangular timing waveform (e.g., at time t5). The active driving state changes to an inactive driving state at about the start of the leading edge of the profile signal (e.g., at time t6). Figure 6 is a flow chart to illustrate the various states that one embodiment of the register state machine 402 cycles through to generate the profile signal. For example, the register state machine 402 repeatedly and sequentially goes through a zero state, a rising state, a holding state and a falling state. The zero state conesponds to a zero output of the profile signal, which occurs when the triangular timing wavefonn is less than the inverted first control signal. The driving signals for the polarity-switching network are configured to change during the zero state. The rising state conesponds to a rising edge of the profile signal. The rising state starts when a rising portion of the triangular timing waveform crosses the level of the inverted first control signal. The profile signal rises at a controllable rate and the slope capacitor charges at a predetermined rate during the rising state. The profile signal stops rising and the slope capacitor stops charging when the voltage across the slope capacitor reaches a level defined by the second control signal. The holding state begins when the slope capacitor stops charging. The holding state conesponds to a plateau of the profile signal in which the profile signal is held substantially constant. The level of the still rising triangular timing waveform is noted at the beginning of the holding state. When the triangular timing waveform crosses the noted level during a falling portion of the triangular timing waveform, the holding state stops. The falling state follows the holding state. The falling sate conesponds to the falling edge of the profile signal. The slope capacitor discharges while the level of the profile signal falls. The slope capacitor returns to its initial value and the profile signal is approximately zero at about the time the triangular timing waveform becomes less than the inverter first control signal. The next zero state begins. The profile signal can advantageously can be used to generate a lamp cunent with an arbitrary wave shape (e.g., a sine wave, a square wave, a trapezoidal wave, etc.), independent of lamp characteristics, to optimize luminous efficiency or to reduce EMI. In one embodiment, a square wave lamp cunent is applied to a lamp, resulting in a lamp cunent crest factor that approaches unity and improves luminous efficiency in comparison to a sine wave lamp cunent which has a lamp cunent crest factor of approximately 1.4. The low crest factor from the square wave lamp cunent and high efficiency of a closely- coupled transfonner in the cunent-mode inverter can provide more nits/watt than traditional sine wave lamp cunents. Correspondingly, fewer lamps in multi-lamp LCD backlight assemblies may be used to achieve about the same brightness. Programmable lamp cunent waveforms can also enable low EMI solutions, hi one embodiment, a trapezoidal cunent wavefonn with relatively slow rise and fall times drives the lamp, resulting in relatively low lamp cunent crest factor (e.g., 1.1-1.3). A square waveform is defined by steep leading and falling edges (or relatively fast rise and fall times of less than one microsecond for the profile signal or less than two microseconds for the lamp cunent). A trapezoidal waveform is defined by relatively slower rise and fall times (e.g., more than one microsecond for the profile signal and more than two microseconds for the lamp cunent). A triangular waveform is defined by substantially no plateau. Since the cunent-mode inverter operates in non-resonance, sine waveforms also need to be synthesized. In prior art synthesizers, a sine wavefonn is typically converted from a triangular waveform using a complicated anay of diodes and resistors to form a piecewise approximation. Because of the diodes, the conversion circuitry is quite temperature sensitive. Figure 7 illustrates a novel method to generate a sine wavefonn from a trapezoidal waveform. For example, a sine wavefonn can be approximated using a predefined trapezoidal waveform synthesized by the cunent profile generator 406. The trapezoidal wavefonn has a maximum allowable pulse width, a pulse height that is approximately 2/3 of the peak voltage of the triangular timing wavefonn, and substantially the same rise and fall slopes as the triangular timing waveform. A graph 700 illustrates the proposed trapezoidal wavefonn, which is approximately the triangular timing waveform clipped at about 2/3 of its peak height. By inverting and repeating this shape, the resulting trapezoidal waveform contains no third harmonics of the fundamental sine wave half-cycle. Thus,- a full cycle of a trapezoidal AC wavefonn containing no harmonics lower than a fifth harmonic is formed. The trapezoidal AC waveform can be filtered by small reactive components or by small reactances of other components to produce a sinusoidal AC waveform, shown as graph 702, with reduced harmonics or an acceptable level of THD. A graph 704 shows the difference between the trapezoidal AC waveform and the resulting sinusoidal AC wavefonn. Figure 8 is a simplified schematic of one embodiment of a cunent-mode driver that drives multiple loads using a time-sharing technique. The cunent-mode driver includes an input cunent regulator 800 and a time-sharing switching network 802. The input cunent regulator 800 shown in Figure 8 is substantially similar to the cunent regulators shown in previous figures with a cunent switch (e.g., P-FET) 812, a series inductor 818 and a catch diode 816. A controller 814 controls the cunent switch 812 to generate a regulated cunent for the time-sharing switching network 802. Other cunent regulator configurations that offer flexible compliance output voltages to accommodate changing loads may also be used. In one embodiment, the time-sharing switching network 802 includes a string of semiconductor switches 820, 822, 824, 826 coupled in series across an output of the input cunent regulator 800. Although the embodiment of Figure 8 shows four semiconductor switches, more or less semiconductor switches can be coupled to the input cunent regulator 800. The semiconductor switches 820, 822, 824, 826 are logically controlled to deliver power of substantially the same polarity to different loads (e.g., light sources in a backlight system) 804, 806, 808, 810 coupled across the respective semiconductor switches 820, 822, 824, 826. For example, each of the semiconductor switches 820, 822, 824, 826 can close to isolate (or bypass) its associated load or open to allow the associated load to conduct the regulated cunent. The semiconductor switches 820, 822, 824, 826 can have overlapping or under-lapping "on" times. In one embodiment, the semiconductor switches 820, 822, 824, 826 operate in a make-before-break action with overlapping switch closures. No power is provided to any of the loads when all of the semiconductor switches are shorted (or closed), hi one embodiment, the cunent-mode driver is used to power an anay of LEDs in a backlight system. The semiconductor switches 820, 822, 824, 826 selectively provide the regulated cunent to different portions of the anay. For example, each of the loads 804, 806, 808, 810 across the respective semiconductor switches 820, 822, 824, 826 includes a plurality of LEDs connected in series to form a horizontal row in the anay. As shown in Figure 8, each of the rows can have the same or a different number of LEDs. One horizontal row of LEDs is shorted at a time by closing the associated semiconductor switch in the time-sharing switching network 802. hi one embodiment, the closures proceed in sequence (e.g., from top to bottom) in synchronism with a vertical sweep of a LCD screen. The sequential blanking minimizes backlight for the portion of the screen that is in the process of changing, thereby decreasing motion artifact in the LCD. one embodiment, the regulated cunent is greater than the rated cunent of the LEDs. The semiconductor switches 820, 822, 824, 826 can be controlled by a PWM circuit to increase "on" duty cycles of the semiconductor switches 820, 822, 824, 826 to compensate for the increased regulated cunent. The regulated cunent is not provided to the load when the associated semiconductor switch is "on." For example, the LEDs can be run at 1.33 times their rated cunent for ³Λ of the time without exceeding average rated power. While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such fonns or modifications as would fall within the scope and spirit of the inventions.

Claims

WHAT IS CLAIMED IS: 1. A cunent-mode inverter comprising: a cunent regulator configured to accept a DC voltage and to output a regulated cunent; a non-resonant switching network configured to produce an AC driving cunent by periodically alternating conduction paths for the regulated cunent; and a closely-coupled output transfonner configured to conduct the AC driving cunent in a primary winding and a conesponding load cunent in a secondary winding

2. The cunent-mode inverter of Claim 1, wherein the load cunent has a substantially identical wave shape as the AC driving cunent.

3. The cunent-mode inverter of Claim 2, wherein the amplitude of the load cunent is proportional to the amplitude of the AC driving cunent.

4. The cunent-mode inverter of Claim 1, further comprising a feedback circuit coupled to the non-resonant switching network on the primary side of the closely-coupled output transformer to sense the AC driving cunent and to generate a feedback signal for the cunent regulator.

5. The cunent-mode inverter of Claim 1, wherein the cunent regulator is a switching cunent regulator using hysteretic pulse width modulation, a switching cunent regulator using clocked pulsed width modulation or a linear cunent regulator.

6. The cunent-mode inverter of Claim 1, wherein the non-resonant switching network uses a push-pull topology with semiconductor switches coupled to respective opposite ends of the primary winding and the regulated cunent applied to a center tap of the primary winding.

7. The cunent-mode inverter of Claim 2, wherein the non-resonant switching network uses a full-bridge topology.

8. The cunent-mode inverter of Claim 7, wherein the full-bridge topology comprises a pair of p-type semiconductor switches coupled between an output of the regulated cunent and respective opposite terminals of the primary winding and a pair of n- type semiconductor switches coupled between the respective opposite terminals of the primary winding and the feedback circuit.

9. The cunent-mode inverter of Claim 1, wherein semiconductor switches in the non-resonant switching network are closed to conduct a predetermined idle cunent when the load cunent is substantially zero.

10. The cunent-mode inverter of Claim 1, wherein a fluorescent lamp is coupled across the secondary winding, and the voltage across the secondary winding automatically increases to ignite the fluorescent lamp.

11. A method to operate an inverter in cunent mode, the method comprising the steps of: converting an input power source into a regulated cunent; periodically alternating conduction paths for the regulated cunent using a non-resonant switching structure to generate an AC cunent source; and coupling the AC cunent source to a lamp load with an output transfonner.

12. The method of Claim 11 , wherein the output transformer is a tightly-coupled transfonner with a magnetization inductance to leakage inductance ratio that is greater than 30:1.

13. The method of Claim 11, further comprising sensing the AC cunent source to generate a feedback signal for controlling brightness of the lamp load.

14. The method of Claim 11, wherein the lamp load comprises a plurality of cold cathode fluorescent lamps coupled in series across a secondary winding of the output transfonner.

15. The method of Claim 11, wherein the lamp load comprises a plurality of balancing transformers with primary windings coupled to different lamps to form parallel primary winding-lamp combinations across a secondary winding of the output transformer, and wherein secondary windings of the balancing transformers are coupled in series to form a closed loop.

16. The method of Claim 11, wherein the lamp load comprises one or more light sources for backlighting a liquid crystal display.

17. The method of Claim 11, wherein the inverter operates in a single continuous mode for striking and regulating power to the lamp load.

18. The method of Claim 11, wherein semiconductor switches in the non- resonant switching structure are closed to stop generating the AC cunent source if the lamp load is off, missing or faulty.

19. A current-mode inverter comprising: means for generating a regulated cunent source; means for periodically alternating conduction paths for the regulated cunent source with non-resonant switching to generate an AC driving cunent; and means for coupling the AC driving cunent to a lamp structure, wherein the lamp structure conducts a lamp cunent with a substantially identical wave shape and proportional amplitude as the AC driving cunent.

20. The cunent-mode inverter of Claim 19, wherein the lamp structure includes one or more fluorescent lamps used for backlighting a liquid crystal television, a desk top monitor, an automotive display, a notebook computer or a tablet computer.

21. The cunent-mode inverter of Claim 19, wherein the non-resonant switching is implemented by metal-oxide-semiconductor field-effect-transistors.

22. The cunent-mode inverter of Claim 19, wherein light intensity of the lamp structure is controlled by a combination of adjusting duty cycles or burst mode durations of the regulated cunent source and duty cycles or burst mode durations of the AC driving cunent.

23. The cunent-mode inverter of Claim 19, further comprising means for sensing the AC driving cunent to control brightness of the lamp structure by adjusting the regulated cunent source.

24. A multi-stage switching inverter comprising: a first switching stage configured to periodically couple an input cunent through a primary winding of a transformer in alternating sense to generate a primary AC driving cunent, wherein a secondary winding of the transformer conducts a secondary AC driving cunent with a proportional amplitude and a relatively high AC voltage; a rectifier circuit coupled across the secondary winding to generate a relatively high voltage and substantially DC cunent source; and a second switching stage coupled between the outputs of the rectifier circuit and inputs of a lamp load, wherein the semiconductor switches in the second switching stage are directly coupled to the lamp load and alternately conduct to generate an AC lamp cunent through the lamp load.

25. The multi-stage switching inverter of Claim 24, wherein the first switching stage is ananged in a push-pull configuration with the input cunent provided to a center tap of the transformer and a pair of semiconductor switches coupled to respective ends of the primary winding.

26. The multi-stage switching inverter of Claim 24, wherein the first switching stage is ananged in a full-bridge configuration.

27. The multi-stage switching inverter of Claim 26, wherein the full-bridge configuration comprises a pair of p-type transistors coupled between the input cunent and respective ends of the primary winding and a pair of n-type transistors coupled between the respective ends of the primary winding and a reference terminal.

28. The multi-stage switching inverter of Claim 24, wherein the rectifier circuit is a full-wave bridge rectifier comprising of at least four diodes.

29. The multi-stage switching inverter of Claim 24, wherein the rectifier circuit is a pair of half-wave voltage doublers, each of the half- wave voltage doublers comprising two diodes and two capacitors.

30. The multi-stage switching inverter of Claim 24, wherein the rectifier circuit is a pair of half-wave voltage doublers, each of the half-wave voltage doublers comprising two diodes and one capacitor.

31. The multi-stage switching inverter of Claim 24, wherein the second switching stage comprises a plurality of semiconductor transistors ananged in a full-bridge topology to periodically alternate conduction paths for the relatively high voltage and substantially DC cunent source through the lamp load to generate the AC lamp cunent.

32. The multi-stage switching inverter of Claim 24, wherein the operating frequency of the first switching stage is higher than the operating frequency of the second switching stage.

33. The multi-stage switching inverter of Claim 24, wherein the first switching stage and the second switching stage use non-resonant circuits.

34. The multi-stage switching inverter of Claim 24, wherein a ground reference is connected to one terminal of the secondary winding, one of the outputs of the rectifier circuit, or one of the inputs of the lamp load.

35. A method to drive a lamp using at least two switching stages, the method comprising the acts of: operating a first switching stage at relatively high frequency to produce a relatively high voltage AC cunent source, wherein the first switching stage is coupled to a primary winding of a transfonner and the relatively high voltage AC cunent source is generated in a secondary winding of the transformer; rectifying the relatively high voltage AC cunent source to a relatively high voltage DC cunent source; and operating a second switching stage at relatively low frequency to generate an AC lamp cunent through a lamp load, wherein the second switching stage is directly coupled across the lamp load.

36. The method of Claim 35, wherein the range of the relatively high frequency for the first switching stage is 100 kilohertz to 4 Megahertz.

37. The method of Claim 35, wherein the range of relatively low frequency for the second switching stage is 100 hertz to 4 kilohertz.

38. The method of Claim 35, wherein the first switching stage operates at approximately 2 Megahertz and the second switching stage operates at approximately 400 hertz.

39. The method of Claim 35, further comprising supplying a substantially DC input cunent to the first switching stage.

40. The method of Claim 35, further comprising grounding one terminal of the secondary winding to provide balanced connections to the lamp load.

41. The method of Claim 35, wherein the peak voltage of the relatively high voltage DC cunent source is approximately four times the pealc voltage of the relatively high voltage AC cunent source.

42. A multi-stage switching inverter comprising: means for generating a relatively high voltage AC cunent from a substantially DC cunent source, wherein the frequency of the relatively high voltage AC cunent is in a first range of frequencies; means for generating a relatively high voltage and substantially DC cunent from the relatively high voltage AC cunent; and means for directly coupling the relatively high voltage and substantially DC cunent across a lamp load in alternating sense to produce an AC lamp cunent through the lamp load, wherein the frequency of the AC lamp cunent is in a second range of frequencies that is lower than the first range of frequencies.

43. The multi-stage switching inverter of Claim 42, wherein the first range of frequencies is 100 kilohertz to 4 Megahertz.

44. The multi-stage switching inverter of Claim 42, wherein the second range of frequencies is 100 hertz to 4 kilohertz.

45. The multi-stage switching inverter of Claim 42, wherein the lamp load comprises a plurality of cold cathode fluorescent lamps.

46. A controller for a cunent-mode inverter comprising: a clock generator configured to output a periodic timing waveform; a cunent profile generator configured to produce a profile signal in a programmable waveform shape defined by at least a capacitor and two input control signals, wherein the profile signal is provided to a cunent regulator to generate a regulated cunent with the programmed waveform shape; and a register state machine configured to control the operations of the cunent profile generator with reference to the periodic timing wavefonn.

47. The controller of Claim 46, wherein the frequency of the periodic timing waveform is detennined by a resistor and a capacitor.

48. The controller of Claim 46, further comprising an attenuation circuit coupled between an output of the cunent profile generator and an input of the cunent regulator to reduce the amplitude range of the profile signal for comparison with a feedback signal.

49. The controller of Claim 46, further comprising a hysteretic pulse width modulation circuit configured to generate a control signal to the cunent regulator based on a comparison of the profile signal to a feedback signal representative of a load cunent.

50. The controller of Claim 46, wherein the regulated cunent is coupled to a fluorescent lamp using a non-resonant inverter, and the two input control signals to the cunent profile generator are independently adjustable to vary the brightness of the fluorescent lamp.

51. The controller of Claim 50, further comprising a pulse width modulation circuit configured to generate polarity switching signals for semiconductor switches in the non-resonant inverter with reference to the periodic timing waveform.

52. The controller of Claim 51, further comprising a fault processor configured to output a fault signal to shut down the pulse width modulation circuit upon detecting faulty conditions in the fluorescent lamp or in the non-resonant inverter, wherein the pulse width modulation circuit configures the polarity switching signals keep the semiconductor switches on continuously in response to the fault signal.

53. The controller of Claim 46, wherein the register state machine cycles through four states conesponding to zero, rising edges, plateaus, and falling edges of the profile signal.

54. A method to generate a cunent profile for a current regulator in a cunent- mode inverter, the method comprising the acts of: periodically setting the cunent profile to a reference level, wherein the period is determined by a periodic triangular waveform; comparing a first control input signal to the periodic triangular waveform to detennine an active duration of the cunent profile in each period, wherein the cunent profile increases at a programmable rising rate and a capacitor starts charging at about the beginning of the active duration; holding the cunent profile at a substantially constant level when the voltage across the capacitor is about equal to or above a predefined holding threshold, wherein the voltage of the periodic triangular waveform is noted at about the time the voltage across the capacitor crosses the predefined holding threshold and the capacitor stops charging; reducing the level of the cunent profile at a programmable falling rate and discharging the capacitor when the voltage of the periodic triangular waveform is approximately less than the noted voltage, wherein the cunent profile returns to the reference level by the end of the active duration.

55. The method of Claim 54, wherein the reference level is zero.

56. The method of Claim 54, wherein the cunent-mode inverter drives at least one fluorescent lamp and two substantially identical cycles of the cunent profile are generated for every cycle of cunent flowing through the fluorescent lamp.

57. The method of Claim 54, wherein the cunent profile pulse-width is determined by the first control input signal, and the cunent profile amplitude is determined by the predefined holding threshold.

58. The method of Claim 54, wherein the cunent profile is a periodic square wavefonn with rise and fall times of less than one microsecond.

59. The method of Claim 54, wherein the cunent profile is a periodic trapezoidal wavefonn with rise and fall times that are greater than one microsecond.

60. The method of Claim 54, wherein the cunent profile is a periodic trapezoidal waveform that is substantially identical to the periodic triangular wavefonn with its amplitude clipped at substantially 2/3 of the peak amplitude of the periodic triangular waveform.

61. The method of Claim 60, further comprising filtering the cunent profile to generate a sinusoidal waveform.

62. A controller for a cunent-mode inverter comprising: means for generating a periodic timing signal; means for defining a rising slope, a plateau, and a falling slope of a cunent profile signal with a capacitor and two input control signals, wherein the cunent profile signal determines the wave shape of a regulated current source; and means for generating a pair of substantially identical wave shapes for every two cycles of the periodic timing signal.

63. The inverter with a cunent-mode controller of Claim 62, further comprising a switching network that operates synchronously with the periodic timing signal to periodically alternate conduction paths for the regulated cunent source to produce an AC driving cunent.

64. The inverter with a cunent-mode controller of Claim 62, further comprising means for adding pre-emphasis to the cunent profile signal by providing an upslope to the plateau to compensate for magnetizing cunent in a transformer of the inverter.

65. The inverter with cunent-mode controller of Claim 62, further comprising means for adjusting amplitude range of the cunent profile signal to match amplitude range of a feedback signal.

66. A multi-load time sharing driver comprising: a cunent source configured to provide a regulated cunent; a network of semiconductor switches coupled in series; and a plurality of light sources in a backlight system, each light source associated with a semiconductor switch, wherein the semiconductor switch selectively opens to allow the associated light source to conduct the regulated cunent.

67. The multi-load time sharing driver of Claim 66, wherein the plurality of light sources backlight a liquid crystal display and the semiconductor switches periodically close in sequential order to minimize backlight in portions of the liquid crystal display that are cunently updating display images.

68. The multi-load time sharing driver of Claim 66, wherein the semiconductor switches are opened during different time intervals within a period to provide the regulated cunent to different sets of loads.

69. The multi-load time sharing driver of Claim 68, wherein the time intervals for different semiconductor switches partially overlap.

70. The multi-load time sharing driver of Claim 68, wherein the different time intervals do not overlap.

71. The multi-load time sharing driver of Claim 66, wherein the semiconductor switches are controlled by a pulse width modulator circuit, and the regulated cunent is greater than the operating cunents of the respective light sources by predetemύned percentages conesponding to decreased duty cycles in the open durations of the respective semiconductor switches.

72. The multi-load time sharing driver of Claim 66, wherein each light source comprises a plurality of light emitting diodes connected in series to form a row in an anay of light emitting diodes in the backlight system.

73. The multi-load time sharing driver of Claim 72, wherein the light emitting diodes conduct cunents that are 1.33 times of their rated cunents at 75% duty cycles.

74. A method to selectively power one or more light sources in a backlight system using a single power source, the method comprising the acts of: generating a regulated cunent; coupling the regulated cunent to a plurality of semiconductor switches connected in series; coupling a different light source across each of the semiconductor switches; and selectively opening the semiconductor switches to provide power to the respective light sources.

75. The method of Claim 74, wherein the plurality of semiconductor switches are periodically opened to provide power to all of the light sources, and the opened semiconductor switches are closed one at a time in sequential order.

76. The method of Claim 75, wherein the light sources are rows of light emitting diodes in the backlight system of a liquid crystal display, and the sequential closure of the semiconductor switches is synclironized with a vertical sweep of the liquid crystal display to minimize motion artifact in the liquid crystal display.

77. The method of Claim 74, wherein the semiconductor switches operate in a make-before-break action with overlapping switch closures.

78. A multi-load time sharing driver comprising: means for generating a regulated current; and means for using a string of semiconductor switches to selectively provide the regulated cunent to different portions of an anay of light emitting diodes in a backlight system.

79. The multi-load time sharing driver of Claim 78, wherein the light emitting diodes are coupled in series, each semiconductor switch is coupled across a different group of series-connected light emitting diodes conesponding to a different row in the anay, and the semiconductor switches are logically controlled to selectively short circuit the different groups of series-connected light emitting diodes for dimming.