WO2005066816A1 - Lane to lane deskewing via non-data symbol processing for a serial point to point link - Google Patents
Lane to lane deskewing via non-data symbol processing for a serial point to point link Download PDFInfo
- Publication number
- WO2005066816A1 WO2005066816A1 PCT/US2004/043526 US2004043526W WO2005066816A1 WO 2005066816 A1 WO2005066816 A1 WO 2005066816A1 US 2004043526 W US2004043526 W US 2004043526W WO 2005066816 A1 WO2005066816 A1 WO 2005066816A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data symbol
- symbol
- deskew
- instance
- data
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
Definitions
- An embodiment of the invention is generally related to serial, point to point interconnect technology suitable for communicatively coupling elements of an electronic system, and particularly to those which have certain aspects that are in accordance with the PCI Express Base Specification 1.0a (Errata dated 7 October 2003) ("PCI Express"). Other embodiments are also described.
- An electronic system is composed of several elements that are designed to communicate with one another over an input/ output (I/O) interconnect of the system.
- a modern computer system may include the following elements: a processor, main memory, and a system interface (also referred to as a system chipset).
- An element may include one or more integrated circuit (IC) devices.
- the system chipset may have a memory controller hub (MCH) device that allows the processor to communicate with system memory and a graphics element.
- MCH memory controller hub
- ICH I/O controller hub
- a separate, point to point link such as one defined by PCI Express may be used to allow bidirectional communication between a pair of devices, e.g. the processor and the MCH, the MCH and the graphics element, and the ICH and the mass storage device.
- a PCI Express point to point link may have one or more lanes that can operate simultaneously.
- Each lane has dual, unidirectional paths, which are also simultaneously operable.
- Each path may have a single set of transmitter and receiver pairs (e.g., a transmitter in a port of Device A, a receiver in a port of Device B).
- the transmitter and receiver may drive and sense a transmission medium such as a pair of metal traces in a printed wiring board that may traverse a board-to-board connector.
- other transmission media may be provided, such as optical fiber.
- a point to point link serves to transport various types of information between devices.
- communications between peers in two devices may be conducted using transactions.
- transactions For example, there are memory transactions that transfer data to or from a memory-mapped location.
- message transactions Under PCI Express, there are also message transactions that communicate miscellaneous messages and can be used for functions like interrupt signaling, error signaling, and power management.
- the first layer may be the Transaction Layer, which begins the process of turning a request or completion data coming from a device core into a data packet for a transaction.
- the second architectural build layer is called the Data Link Layer; it ensures that packets going back and forth across a link are received properly (via techniques such as error control coding).
- the third layer is called the Physical Layer. This layer is responsible for the actual transmitting and receiving of the packet across the link.
- the Physical Layer in a given device interacts with its Data Link Layer (in the same device) on one side, and with the metal traces, optical fiber, or other transmission medium that is part of the link, on another side.
- the Physical Layer may contain circuitry for the transmitters and receivers, parallel to serial and serial to parallel converters, frequency and phase control circuits, and impedance matching circuitry. It may also contain circuitry for logic functions needed for its initialization and maintenance.
- a layered architecture may permit easier upgrades by, for example, allowing reuse of essentially the same Transaction and Data Link Layers, while upgrading the Physical Layer (e.g., increasing transmit and receive clock frequencies).
- the Physical Layers on both Device A and Device B are responsible for initializing the link and making it ready for transactions. This initialization process may include determining how many lanes should be used for the link, and at what data rate the link should operate. Sometime after the link is properly initialized, a memory read request is initiated in Device A. Eventually, a packet that includes this read request arrives at Device A's Physical Layer, including headers, error control information, and sequence numbers added by the higher layers. The Physical Layer then takes this packet of data and transforms it into a serial data stream (perhaps after adding framing data to it), and transmits the stream using, for example, an electrical, differential signal having predefined timing rules.
- the Physical Layer in Device B samples the signal to recover the data stream, and builds the stream back into a data packet (e.g., after removing the framing).
- the packet is then passed up to the Data Link Layer in Device B, which strips the headers and checks for errors; if there are no errors, the packet is passed up to the Transaction Layer where the memory read request is extracted and then sent to the appropriate logic function to access the locations specified in the request.
- Fig.1 illustrates a pair of integrated circuit devices that are coupled to each other via a serial point to point link.
- Fig. 2 shows a block diagram of part of the link interface circuitry used to implement the serial point to point link in an integrated circuit device.
- Fig. 3 depicts a block diagram of deskew circuitry for servicing in this example a link having four lanes.
- Figs.4A-4B show a detailed block diagram of example deskew circuitry for a single lane.
- Fig. 5 is an example timing diagram that illustrates a deskew process.
- Figs. 6A-6B show an example timing diagram of another deskew process.
- Fig. 7 identifies the various elements of a multi-media desktop personal computer some of which are communicationally coupled to each other via PCI Express virtual channels (NCs).
- NCs PCI Express virtual channels
- Fig. 8 depicts a block diagram of an enterprise network.
- FIG. 1 illustrates a pair of integrated circuit devices that are coupled to each other via a serial point to point link.
- the IC devices 104 (Device A) and 108 (Device B) may be part of a computer system that contains a processor 112 and main memory 114.
- a serial point to point link 120 is used to communicatively couple the core of Device B with that of Device A.
- the link 120 has dual, unidirectional paths 122, with link interface 124 that serves to interface with the device core of each respective Device A and B.
- Device B is referred to as the root complex of the computer system and provides the processor 112 with I/O access to, for instance, a graphics element in Device A.
- the root complex may be partitioned into a graphics and memory controller hub (GMCH) and an I/O controller hub (ICH).
- GMCH graphics and memory controller hub
- ICH I/O controller hub
- the ICH would act as a further interface between the GMCH and other I/O devices of the system, including a non-volatile mass storage device, a pointing device such as a track pad or mouse, and a network interface controller (not shown).
- the point to point link 120 may be duplicated for communicatively coupling the Device B to the processor 112 and the main memory 114. Other platform architectures that feature the point to point link 120 are also possible.
- the interface 124 of Fig.1 may be viewed as implementing the multiple layer architecture (described above in the Background) for a serial point to point link. Some details of the interface 124 are illustrated in Fig.2.
- the interface 124 supports independent transmit and receive paths between the transmission medium 122 and the Data Link Layer of its respective device 104, 108.
- information in the form of data packets arrive from the Data Link Layer and are divided into symbols that are encoded by an encode block 208.
- a purpose of the encoding by block 208 is to embed a clock signal so that a separate clock signal need not be transmitted into the transmission medium 122.
- This encoding may be the well known 8B-10B where an eight bit quantity is converted into a 10 bit quantity; other encoding schemes are possible. In some cases, such as where a separate strobe or clock signal is transmitted in the medium 122, there may be no need for such encoding.
- the units of data are processed by a parallel to serial block 212 of an analog front end (AFE) transmit block 214 to yield a stream of bits.
- AFE analog front end
- a "bit” as used here may represent more than two different states, e.g. a binary bit, a ternary bit, etc.
- the term "bit” is used merely here for convenience and is not intended to be limited to a binary bit.
- the bit stream is then driven into the transmission medium 122. As explained above in the Background, this transmission medium may be a pair of metal traces formed in a printed wiring board. Other forms of the transmission medium 122 may alternatively be used, such as an optical fiber.
- the series of blocks 208-214 may serve a single lane of the point to point link 120 (Fig.1). In general, there may be more than one lane in the point to point link 120, so that a packet received from the Data Link Layer may be "striped" across multiple lanes for transmission.
- each lane has its associated AFE receive block 224, which serves to receive a stream of information from the transmission medium 122, by for example sampling a signal in the transmission medium 122.
- the AFE receive block 224 translates between signaling of the transmission medium 122 and signaling of the IC device 104 (e.g., on-chip, complementary metal oxide semiconductor, CMOS, logic signaling).
- the stream of information represents sequences of M-bit symbols (where M is an integer greater than 1) that have been transmitted by the Device B over the serial point to point link 120 (see Fig.1).
- the stream of bits provided by the AFE receive block 224 is fed to symbol alignment logic 228 which serves to align or lock onto the symbols that have been received.
- symbol alignment logic 228 will demarcate the correct symbol boundaries within the received bit stream, for use by subsequent sections of the Physical Layer in the device 104.
- the symbol-aligned bit stream may then be fed to decode block
- the EB 234 serves to compensate for any differences in the tolerance of the rate at which the symbols were transmitted in Device B and a local clock signal (local_clk) of Device A.
- the local_clk is used to unload symbols from the EB 234, as well as in some cases operate parts of lane to lane deskew circuitry 238 as explained below (in the case where the link 120 is composed of more than one lane).
- the decode block 232 (if provided) may be placed further downstream, e.g. at the output of the EB 234 or at the output of the deskew circuitry 238.
- the unload pointer of the EB 234 may be managed to avoid overflow and underflow conditions in the elastic buffer, using predefined, special or non-data sequences of symbols that have been inserted into a data sequence, by the Device B (see Fig.1). Briefly, to prevent underflow of the elastic buffer, the unload pointer may be stalled at an entry of the buffer that contains a non-data symbol, in response to detecting the non-data sequence. This is done while unloading the data sequence according to the changing unload pointer. This causes the load pointer to move away from the unload pointer and thereby avoid underflow.
- the unload pointer may be changed by more than one entry so that a non-data symbol of the non-data sequence (as it is presently loaded in the buffer) is skipped, while symbols are being unloaded from the buffer. Once again, this is done in response to detecting the non-data sequence. This causes the unload pointer to move away from the load pointer, again to avoid a collision.
- a symbol may be a "data" symbol that represents some payload that has been sourced by the Data Link Layer, Transaction Layer or some other higher layer such as the device core.
- a symbol may be a "non- data" symbol, e.g. a special symbol generated by one of the Physical, Data Link, or Transaction Layers, to achieve some type of control over the information that is being transmitted over the serial point to point link.
- PCI Express defines a number of special symbols that are added to the packets that are being communicated. For instance, special symbols may be added to mark the start and stop of a packet. This is done to let the receiving device know where one packet starts and where it ends. Different special symbols are added for packets that originate in the Transaction Layer than in the Data Link Layer. In addition, there is a special symbol called "SKP" (skip) which is to be used by the Physical Layer for compensating for small differences in the operating data rates of two communicating ports. There is also a special symbol called "COM" (comma) that is to be used for lane and link initialization by the Physical Layer.
- deskew is a problem because the "flight time" of information as it is transmitted from Device B and received at Device A may vary from lane to lane.
- a set of symbols may be transmitted simultaneously on a corresponding set of lanes by Device B, using the same transmit clock, they cannot be expected to arrive at Device A at essentially the same time, i.e. without lane to lane skew.
- a packet may be striped across multiple lanes, any lane to lane skew should be minimized to help ensure that the striped packet is received and processed correctly at the receiver device. Otherwise, if symbols that have been transmitted simultaneously arrive at the receiver at different times, and are then deserialized to reconstruct a packet of data, such a packet would be most likely completely incomprehensible to the Data Link layer. Under PCI Express, predefined, non-data sequences referred to as "TS1/TS2 Ordered-Sets" may be used to determine the amount of misalignment or skew between the lanes of a given link.
- Fig. 3 illustrates conceptually how four sets of a four-symbol sequence that were transmitted "simultaneously" arrive in parallel but at different times in the receiver, and are subsequently aligned by the deskew circuitry.
- lane to lane deskewing may be achieved via non-data symbol processing, as described below.
- First, two or more symbol sequences are received in parallel in Device A, where these sequences have been transmitted by Device B over the serial point to point link (see Fig.2).
- Each symbol sequence includes an instance of a first non-data symbol (e.g., the PCI Express COM).
- the symbol sequences are buffered to compensate for the tolerances allowed for the transmit clock of Device B and the receive clock of Device A. Referring again back to Fig. 2, such buffering may be accomplished by the elastic buffer (EB) 234.
- EB elastic buffer
- This buffering may also cause a change in the number of times an instance of a second non-data symbol (e.g., PCI Express SKP) occurs in a given symbol sequence.
- a second non-data symbol e.g., PCI Express SKP
- the action of the EB 234 may induce further lane to lane skew.
- An embodiment of the invention is directed to a two part deskew process.
- the first part aligns an instance of the first non-data symbol in every one of the buffered symbol sequences of the link. This process results in a certain adjustment in the delays that are presented to each sequence, by the buffering effect of the deskew logic.
- the second part may be invoked to equalize the number of instances of the second non-data symbol that follow an instance of the first non-data symbol (in every one of the symbol sequences).
- An example using special symbols defined under PCI Express will now be described. It should be noted that other types of non-data symbols, including different first and second non-data symbols, may be used to achieve the deskew described here.
- either of these first and second parts of the deskew process may be used separately, or in combination with other symbol processing, to achieve reliable multi-lane communications for a serial point to point link.
- FIG.3 shows a block diagram of deskew circuitry for servicing in this example a link having four lanes. Each is receiving 10-bit symbols from the EB 234 (see Fig. 2). Although these are shown as 10-bit symbols, the embodiment of Fig. 2 may actually provide 8-bit symbols because of the presence of the decode block 232. Other symbol sizes are alternatively possible.
- Each lane has its own lane deskew logic 304 which receives its respective symbol sequence.
- the lane deskew logic 304 receives control signals from a portion of a link initialization unit 308 that may act as a supervisor for the deskew process. These control signals include: a deskew enable control signal (per lane); and a control signal that indicates that the first non-data symbol has been detected on all lanes of the link (all_com_det).
- Each instance of the lane deskew logic 304 also provides at its output its respective, forwarded symbol sequence (with reduced skew).
- the lane deskew logic may be implemented by the hardware shown in Figs.4A-4B.
- a deskew buffer 404 (which may have a first in first out structure, also referred to as a queue) is provided with a depth of in this example seven entries (0, 1,...6).
- the depth of the buffer 404 should be selected in view of an upper limit on the allowable skew provided in a design specification for the link.
- the same buffer 404 may be used for both the first and second deskew processes.
- write pointer logic 408 is designed to load a buffered, symbol sequence into the deskew buffer 404.
- the value of the write pointer is changed or updated sequentially according to the local clock, lgclk, which is also used to read the buffered symbols out of the EB 234 (see Fig. 2).
- the write pointer may be incremented, that is changed by one entry, for each cycle of lgclk, under normal circumstances, as well as during the first part of the deskew process, even when the read pointer as described below has been stalled.
- the write pointer is controlled such that the second non-data symbol (e.g. SKP) may never be written into the buffer.
- the second non-data symbol is the one that is substituted when the read pointer is stalled (during the first part of the deskew process). Avoiding the actual writing of the second non-data symbol to the buffer (during the second part) helps avoid an eventual buffer overflow condition.
- Fig.4B shows read pointer logic 412 that provides a read pointer, to unload the buffered, symbol sequence from the deskew buffer 404.
- the read pointer is incremented according to each cycle of lgclk unless the first non-data symbol (e.g., COM) appears at the outlet of the buffer 404.
- the deskew circuitry shown in Fig.4B also includes control logic
- the logic may be activated once the enable control signal gi_gb_dskew_en (as well as perhaps an indication that symbol alignment has occurred, namely via gp_gi_kalignlck) has been asserted.
- the control logic 416 can stall the read pointer, in this example through selection of the "01" input of a multiplexer as shown.
- control logic 416 can generate an instance of the second non-data symbol (e.g., SKP) at an output of the lane deskew logic through which the buffered symbol sequence dskw_data[7:0] is forwarded.
- the control logic 416 may release the read pointer (and stop generating instances of the second non-data symbol) once the first non-data symbol has appeared at an output of the deskew buffer 404 in every lane of the link.
- FIG. 5 Operation of the first part of the deskew process, using the hardware of Figs.4A-4B as an example, is depicted in the timing diagram of Fig. 5.
- This timing diagram shows waveforms associated with two different lanes of the link where lane 0 may be the first one to receive the first non-data symbol COM and lane 1 is the last lane to receive a COM.
- the write pointer wrptr is incremented in each cycle of lgclk (and wraps around to 0 in cycle 8).
- the inlet of the buffer 404 is represented by ebuff_out[7:0] while its output is represented by FIFO_dataout.
- the indication dskew_char is a flag that also arrives at the inlet of the buffer 404 (from the EB 234, see Fig. 2). This flag is aligned with the arriving COM symbol as seen in cycle 2.
- lane 0 in cycle 6 forwards the buffered COM, rather than the generated SKP, at its output dskw_data[7:0].
- the signal gi_gp_dskewchar_all_detect when asserted, means that all lanes of the link have "seen” the first non-data symbol, such that the rdptr for each lane may now be released from its stall state.
- the write pointers for all lanes continue to be incremented in each cycle of lgclk, unless the second non-data signal (here, SKP) is detected at the inlet of the buffer 404.
- the process looks for the COM at the inlet of the buffer 404 where this COM is not that of a SKP Ordered-Set.
- the SKP Ordered-Set as explained above is an example of a non-data sequence that is defined under PCI Express as consisting of a single COM followed by a one to five instances of SKP.
- DATA 1, DATA 2, and DATA 3 (which are said to "follow" COM) are instead each an instance of the non-data symbol SKP.
- the first part of the deskew process also referred to as deskew using COM for the PCI Express embodiment, results in alignment of the COM in all lanes of a link, by inserting one or more instances of SKP preceding the COM. This can be seen in Fig. 5, by comparing the output deskewed data for lane 0 (dskw_data[7:0]) with the corresponding deskewed output for lane 1. Note how the COMs are aligned in cycle 6 of lgclk, achieved by inserting three instances of SKP that precede the COM, in clock cycles 3-5.
- the above described first part of the deskew process may be performed during training, prior to initialization of the link.
- the first part may be followed by the second part, an example of which is illustrated in Figs. 6A-6B.
- the second part of the deskew process is also referred to as deskew using SKP. This second part may be performed only when a link initialization unit or some other higher level symbol processing unit asserts a further enable symbol gi_gp_skpdskew_en (see Figs.4A-4B).
- the deskew logic circuitry as illustrated in Figs.4A-4B, for example, now watches for an indication of an instance of the first non-data symbol (e.g., COM) followed by an instance of the second non-data symbol (e.g., SKP).
- these two symbols are an example of the PCI Express SKP Ordered-Set, although in general other non-data sequences will also work.
- this indication is given by the assertion of eb_dskw_skpdet obtained from the EB 234. This indication may also set a flag indicating that an SKP Ordered-Set is being processed.
- Fig. 6B shows lane 1 which is in this case an example of a lane that has received no instances of SKP in what was an SKP Ordered-Set prior to the elastic buffer, EB 234 (Fig. 2).
- the non-data sequence in this case consists of a single instance of COM arriving from the elastic buffer (cycle 1). This symbol would nonetheless be considered an SKP Ordered-Set (because it is aligned with the corresponding sequence in lane 0). Accordingly, the ep_dskw_skpdet indication is also set when the COM is received in cycle 1.
- the skp_detect_vld indication is set as in cycle 2, signifying that there is at least one SKP that will need to be inserted for the output of lane 1. Accordingly, at the start of cycle 3, an instance of SKP is generated at the output (dskw_data). Additional instances of SKP will continue to be generated for lane 1, so long as the relevant deskew character, in this case the last instance of SKP in the longest Ordered-Set of the link, has not been detected at the inlet of a deskew buffer of any lane of the link. For the example of Figs.
- the gi_gp_dskewchar_all_detect flag is asserted beginning with cycle 5 indicating the end of the longest SKP Ordered-Set. This leads to the read pointer in lane 1 being released with cycle 5, such that the data symbol in the deskew buffer for lane 1 (here, DATA 1) is provided at the output for lane 1. It can be therefore seen that the sequence of symbols DATA 0, COM, SKP, SKP, DATA 1, DATA 2, DATA 3, ... are all aligned in lane 0 and in lane 1 (as dskw_data).
- this pointer may be activated, e.g. incremented according to lgclk, as soon as a training sequence has been initiated for the link.
- the write pointer may be incremented under all circumstances except the following (where the write pointer will hold or be stalled at its present value): a) the second non-data symbol (e.g., SKP) has been detected at the inlet of the corresponding deskew buffer; or b) the link is in the XI configuration, that is a single lane.
- the second non-data symbol e.g., SKP
- this pointer may be activated as soon as the write pointer has been activated.
- the following are conditions under which the read pointer may not be incremented, that is it is stalled: a) the read pointer is equal to the write pointer (also referred to as pointer collision meaning that the deskew process cannot be performed); b) an indication at the outlet of the deskew buffer that a deskew character or symbol (e.g., COM or SKP) has been detected, but that such a symbol has not been detected in all lanes of the link; or c) the link is in the single lane configuration.
- the signal gp_gi_dskewchar_detect (Figs. 5 and 6) is a single signal that may be used to indicate the presence of either type of deskewing character, e.g. either a COM or SKP.
- link interface circuitry and methodology may also be implemented in IC devices that are designed to communicate via a serial, point to point interconnect technology that provides isochronous support for multimedia.
- Isochronous support is a specific type of QoS (Quality of Service) guarantee that data is delivered using a deterministic and time- dependent method.
- QoS Quality of Service
- Platform-based isochronous support relies on a documented system design methodology that allows an application that requires a constant or dedicated level of access to system resources to gain the required bandwidth at a given time interval.
- FIG. 7 An example is that of watching an employee broadcast that originates from the company's CEO, on a desktop while working on a report, as shown in Fig. 7.
- Data is routed from the intranet into the desktop main memory where the application utilizes the data to create an audio stream sent to the user's headphones via an add-in card and a video stream sent to the display via a graphics controller.
- PC desktop personal computer
- the audio and video stream will be truly glitchless.
- Data is delivered on a "best effort" method only. The user may experience skips or stalls as applications compete for the same resources.
- Isochrony in PCI Express solves this problem by establishing a mechanism to guarantee that time-sensitive applications are able to secure adequate system resources. For example, in Fig. 7, the video time-sensitive data would be guaranteed adequate bandwidth to prevent skips at the expense of non-critical data such as email.
- the above-described link interface circuitry and methodology may also be implemented in IC devices that are designed to communicate via a serial point to point link technology that is used in communications equipment, from embedded applications to chassis-based switching systems. In advanced switching, mechanisms are provided to send packets peer-to-peer through the switch fabric. These markets also benefit from the server class hardware-based error detection that is available with PCI Express.
- Control plane refers to the control and configuration of the system.
- the serial link may be used as the interface to configure and control processors and cards within a large number of systems. Chassis-based building switches typically have various cards that can be inserted and used. Chassis-based switches may offer field-upgradeability.
- serial link technology could be used as a control plane interconnect to configure and monitor the different types of cards installed within the system.
- the enumeration and established configuration protocol within PCI Express lends itself to a low pin count, high bandwidth interface to configure cards and services.
- the data plane refers to the actual path that the data flows.
- an advanced switching extension may define mechanisms to encapsulate and send PCI Express data packets across peer-to-peer links through the switch fabric.
- the PCI Express core architecture may provide a solid foundation for meeting new interconnect needs.
- the Advanced Switching (AS) architecture overlays on this core and establishes an efficient, scalable, and extensible switch fabric through the use of a specific AS header inserted in front of the PCI Express data packet at the Transaction Layer.
- AS switches only examine the contents of the header that provide routing information (where to send the packet), traffic class ID (quality of service information), congestion avoidance (for preventing traffic jams), packet size, and protocol encapsulation. By separating the routing information, switch designs are simpler and cost- effective. Additionally, adding an external header to the packet enables the switch fabric to encapsulate any number of existing protocols.
- link interface circuitry and methodology may also be implemented in IC devices that are designed to communicate via a serial point to point interconnect technology that is used for network connections (in place of Gigabit Ethernet, for example).
- the network connection may be for corporate mobile and desktop computers for sharing files, sending emails, and browsing the Internet. Servers as well as communications equipment may be expected to implement such network connections.
- An example of such a network connection within the enterprise network is shown in Fig. 8.
- FIG. 5 Although the above examples may describe embodiments of the invention in the context of combinational and sequential logic circuits, other embodiments of the invention can be implemented by way of software.
- some embodiments may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process according to an embodiment of the invention.
- operations might be performed by specific hardware components that contain microcode, hardwired logic, or by any combination of programmed computer components and custom hardware components.
- a design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners.
- the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/ or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, data representing a hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine-readable medium. An optical or electrical wave modulated or otherwise generated to transmit such information, a memory, or a magnetic or optical storage such as a disc may be the machine readable medium.
- any of these mediums may "carry” or “indicate” the design or software information.
- an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or retransmission of the electrical signal is performed, a new copy is made.
- a communication provider or a network provider may make copies of an article (a carrier wave) that features an embodiment of the invention.
- serial point to point link as a chip to chip connection between two devices on a printed wiring board such as in a desktop, server, or notebook computer
- the deskewing technique may also be used with serial point to point links that are part of an external bus for connecting the computer to a peripheral such as a keyboard, monitor, external mass storage device, or camera.
- the point to point link may be used in not only computer systems, but also dedicated communications products such as mobile phone units, telecommunication switches, and data network routers.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112004002567T DE112004002567T5 (en) | 2003-12-31 | 2004-12-22 | Lane-to-Lane equalization over non-data symbol processing for a point-to-point serial connection |
CN2004800392712A CN1902613B (en) | 2003-12-31 | 2004-12-22 | Lane to lane deskewing via non-data symbol processing for a serial point to point link |
GB0608721A GB2423171B (en) | 2003-12-31 | 2004-12-22 | Lane to lane deskewing via non-data symbol processing for a serial point to point link |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/749,721 | 2003-12-31 | ||
US10/749,721 US7631118B2 (en) | 2003-12-31 | 2003-12-31 | Lane to lane deskewing via non-data symbol processing for a serial point to point link |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005066816A1 true WO2005066816A1 (en) | 2005-07-21 |
Family
ID=34701088
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/043526 WO2005066816A1 (en) | 2003-12-31 | 2004-12-22 | Lane to lane deskewing via non-data symbol processing for a serial point to point link |
Country Status (6)
Country | Link |
---|---|
US (3) | US7631118B2 (en) |
CN (1) | CN1902613B (en) |
DE (1) | DE112004002567T5 (en) |
GB (1) | GB2423171B (en) |
TW (1) | TWI320529B (en) |
WO (1) | WO2005066816A1 (en) |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI249681B (en) * | 2003-07-02 | 2006-02-21 | Via Tech Inc | Circuit and method for aligning data transmitting timing of a plurality of lanes |
US7930377B2 (en) | 2004-04-23 | 2011-04-19 | Qlogic, Corporation | Method and system for using boot servers in networks |
US7669190B2 (en) | 2004-05-18 | 2010-02-23 | Qlogic, Corporation | Method and system for efficiently recording processor events in host bus adapters |
US7500131B2 (en) * | 2004-09-07 | 2009-03-03 | Intel Corporation | Training pattern based de-skew mechanism and frame alignment |
US7577772B2 (en) * | 2004-09-08 | 2009-08-18 | Qlogic, Corporation | Method and system for optimizing DMA channel selection |
US20060064531A1 (en) * | 2004-09-23 | 2006-03-23 | Alston Jerald K | Method and system for optimizing data transfer in networks |
US7676611B2 (en) * | 2004-10-01 | 2010-03-09 | Qlogic, Corporation | Method and system for processing out of orders frames |
US20060146967A1 (en) * | 2004-12-31 | 2006-07-06 | Adarsh Panikkar | Keep-out asynchronous clock alignment scheme |
KR20060081522A (en) * | 2005-01-10 | 2006-07-13 | 삼성전자주식회사 | Method of compensating byte skew for pci express and pci express physical layer receiver for the same |
EP1856869B1 (en) * | 2005-01-20 | 2017-09-13 | Rambus Inc. | High-speed signaling systems with adaptable pre-emphasis and equalization |
US7392437B2 (en) * | 2005-01-20 | 2008-06-24 | Qlogic, Corporation | Method and system for testing host bus adapters |
US7281077B2 (en) * | 2005-04-06 | 2007-10-09 | Qlogic, Corporation | Elastic buffer module for PCI express devices |
US7929577B2 (en) * | 2005-10-13 | 2011-04-19 | Via Technologies, Inc. | Method and apparatus for packet error detection |
TWI290284B (en) * | 2005-10-13 | 2007-11-21 | Via Tech Inc | Method and electronic device of packet error detection on PCI express bus link |
PL1955470T3 (en) * | 2005-11-22 | 2015-02-27 | Ericsson Telefon Ab L M | Synchronized receiver |
JP5194014B2 (en) * | 2006-09-06 | 2013-05-08 | トムソン ライセンシング | Data word stream processing device |
US8199782B2 (en) | 2009-02-20 | 2012-06-12 | Altera Canada Co. | Method of multiple lane distribution (MLD) deskew |
JP5266164B2 (en) * | 2009-08-25 | 2013-08-21 | ルネサスエレクトロニクス株式会社 | Data receiver |
JP5426326B2 (en) * | 2009-11-09 | 2014-02-26 | ルネサスエレクトロニクス株式会社 | Data receiving apparatus, data receiving method, and program |
US9531646B1 (en) * | 2009-12-07 | 2016-12-27 | Altera Corporation | Multi-protocol configurable transceiver including configurable deskew in an integrated circuit |
US8358658B2 (en) * | 2010-03-19 | 2013-01-22 | International Business Machines Corporation | Implementing ordered and reliable transfer of packets while spraying packets over multiple links |
TW201142613A (en) * | 2010-05-31 | 2011-12-01 | Jmicron Technology Corp | Timing aligning circuit and timing aligning method for aligning data transmitting timing of a plurality of lanes |
CN102270011A (en) * | 2010-06-04 | 2011-12-07 | 智微科技股份有限公司 | Time sequence calibration circuit and method for calibrating data transmission time sequences of multiple data channels |
US20120030438A1 (en) * | 2010-07-29 | 2012-02-02 | Sarance Technologies Inc. | Method and Apparatus for Performing Skew Removal in the Receiver of a Multi-Lane Communication Link |
US8488729B1 (en) * | 2010-09-10 | 2013-07-16 | Altera Corporation | Deskew across high speed data lanes |
CN102111329A (en) * | 2010-12-24 | 2011-06-29 | 合肥昊特信息科技有限公司 | Calibration logical system based on embedded-type high-speed transceiver |
US8886856B1 (en) * | 2011-06-21 | 2014-11-11 | Altera Corporation | Methods and apparatus for communicating low-latency word category over multi-lane link |
KR101876418B1 (en) * | 2012-04-05 | 2018-07-10 | 한국전자통신연구원 | Apparatus and method deskew on peripheral component interconnect express |
US8437343B1 (en) | 2012-05-22 | 2013-05-07 | Intel Corporation | Optimized link training and management mechanism |
US8549205B1 (en) | 2012-05-22 | 2013-10-01 | Intel Corporation | Providing a consolidated sideband communication channel between devices |
US8446903B1 (en) * | 2012-05-22 | 2013-05-21 | Intel Corporation | Providing a load/store communication protocol with a low power physical unit |
US8972640B2 (en) | 2012-06-27 | 2015-03-03 | Intel Corporation | Controlling a physical link of a first protocol using an extended capability structure of a second protocol |
US8913705B2 (en) * | 2012-08-27 | 2014-12-16 | Oracle International Corporation | Dynamic skew correction in a multi-lane communication link |
KR101772037B1 (en) | 2012-10-22 | 2017-08-28 | 인텔 코포레이션 | High performance interconnect physical layer |
US9600431B2 (en) | 2012-10-22 | 2017-03-21 | Intel Corporation | High performance interconnect physical layer |
US10348821B2 (en) * | 2012-12-21 | 2019-07-09 | Dropbox, Inc. | Prioritizing structural operations and distributing changes in a synced online content management system |
US9261934B2 (en) | 2013-03-15 | 2016-02-16 | Intel Corporation | Dynamic response improvement of hybrid power boost technology |
US9118457B2 (en) | 2013-03-15 | 2015-08-25 | Qualcomm Incorporated | Multi-wire single-ended push-pull link with data symbol transition based clocking |
JP6221328B2 (en) * | 2013-04-30 | 2017-11-01 | 富士通株式会社 | Receiving device, information processing device, and data receiving method |
US10031547B2 (en) * | 2013-12-18 | 2018-07-24 | Qualcomm Incorporated | CCIe receiver logic register write only with receiver clock |
US9426082B2 (en) | 2014-01-03 | 2016-08-23 | Qualcomm Incorporated | Low-voltage differential signaling or 2-wire differential link with symbol transition clocking |
US9612643B2 (en) | 2014-03-29 | 2017-04-04 | Intel Corporation | Controlling the CPU slew rates based on the battery state of charge |
US9331724B2 (en) * | 2014-09-15 | 2016-05-03 | Xilinx, Inc. | Lane-to-lane de-skew for transmitters |
US9710406B2 (en) | 2014-12-15 | 2017-07-18 | Intel Corporation | Data transmission using PCIe protocol via USB port |
US9946683B2 (en) * | 2014-12-24 | 2018-04-17 | Intel Corporation | Reducing precision timing measurement uncertainty |
US9720439B2 (en) | 2015-09-26 | 2017-08-01 | Intel Corporation | Methods, apparatuses, and systems for deskewing link splits |
CN105933244B (en) * | 2016-04-14 | 2018-11-27 | 浪潮电子信息产业股份有限公司 | A kind of device and method that deflection is gone in channel alignment |
CN105955915B (en) * | 2016-04-21 | 2018-10-26 | 浪潮电子信息产业股份有限公司 | A kind of parallel data goes the method, apparatus and system of deflection |
US20180329855A1 (en) | 2017-05-12 | 2018-11-15 | Intel Corporation | Alternate protocol negotiation in a high performance interconnect |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020138675A1 (en) * | 2001-03-23 | 2002-09-26 | International Business Machines Corporation | Processor for determining physical lane skew order |
US20030099260A1 (en) * | 2001-11-19 | 2003-05-29 | Bunton William P. | Time-division multiplexed link for use in a service area network |
US6654824B1 (en) * | 2001-08-28 | 2003-11-25 | Crossroads Systems, Inc. | High-speed dynamic multi-lane deskewer |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6009488A (en) | 1997-11-07 | 1999-12-28 | Microlinc, Llc | Computer having packet-based interconnect channel |
JP3403076B2 (en) | 1998-06-30 | 2003-05-06 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US6326667B1 (en) | 1999-09-09 | 2001-12-04 | Kabushiki Kaisha Toshiba | Semiconductor devices and methods for producing semiconductor devices |
US6766464B2 (en) * | 2001-02-13 | 2004-07-20 | Sun Microsystems, Inc. | Method and apparatus for deskewing multiple incoming signals |
US20030112827A1 (en) * | 2001-12-13 | 2003-06-19 | International Business Machines Corporation | Method and apparatus for deskewing parallel serial data channels using asynchronous elastic buffers |
TWI249681B (en) * | 2003-07-02 | 2006-02-21 | Via Tech Inc | Circuit and method for aligning data transmitting timing of a plurality of lanes |
US7295639B1 (en) * | 2003-07-18 | 2007-11-13 | Xilinx, Inc. | Distributed adaptive channel bonding control for improved tolerance of inter-channel skew |
-
2003
- 2003-12-31 US US10/749,721 patent/US7631118B2/en not_active Expired - Fee Related
-
2004
- 2004-12-22 GB GB0608721A patent/GB2423171B/en not_active Expired - Fee Related
- 2004-12-22 WO PCT/US2004/043526 patent/WO2005066816A1/en active Application Filing
- 2004-12-22 DE DE112004002567T patent/DE112004002567T5/en not_active Withdrawn
- 2004-12-22 CN CN2004800392712A patent/CN1902613B/en not_active Expired - Fee Related
- 2004-12-27 TW TW093140768A patent/TWI320529B/en not_active IP Right Cessation
-
2009
- 2009-08-19 US US12/544,178 patent/US7913001B2/en not_active Expired - Fee Related
-
2010
- 2010-11-17 US US12/948,103 patent/US7979608B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020138675A1 (en) * | 2001-03-23 | 2002-09-26 | International Business Machines Corporation | Processor for determining physical lane skew order |
US6654824B1 (en) * | 2001-08-28 | 2003-11-25 | Crossroads Systems, Inc. | High-speed dynamic multi-lane deskewer |
US20030099260A1 (en) * | 2001-11-19 | 2003-05-29 | Bunton William P. | Time-division multiplexed link for use in a service area network |
Also Published As
Publication number | Publication date |
---|---|
US20090307394A1 (en) | 2009-12-10 |
GB2423171A (en) | 2006-08-16 |
TW200532457A (en) | 2005-10-01 |
US7631118B2 (en) | 2009-12-08 |
GB2423171B (en) | 2007-07-25 |
GB0608721D0 (en) | 2006-06-14 |
CN1902613B (en) | 2011-03-09 |
US7913001B2 (en) | 2011-03-22 |
US20110066771A1 (en) | 2011-03-17 |
TWI320529B (en) | 2010-02-11 |
US20050141661A1 (en) | 2005-06-30 |
CN1902613A (en) | 2007-01-24 |
DE112004002567T5 (en) | 2006-12-14 |
US7979608B2 (en) | 2011-07-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7979608B2 (en) | Lane to lane deskewing via non-data symbol processing for a serial point to point link | |
US7444558B2 (en) | Programmable measurement mode for a serial point to point link | |
US10552358B2 (en) | Interface for bridging out-of-band information from a downstream communication link to an upstream communication link | |
US7613959B2 (en) | Data receiving apparatus of a PCI express device | |
KR101419292B1 (en) | Redriver with two reference clocks and method of operation thereof | |
US20050144341A1 (en) | Buffer management via non-data symbol processing for a point to point link | |
US8913705B2 (en) | Dynamic skew correction in a multi-lane communication link | |
US7152136B1 (en) | Implementation of PCI express | |
JP4279672B2 (en) | Parallel data communication with data valid indicator and skew intolerant data group | |
US6757348B1 (en) | High-speed coordinated multi-channel elastic buffer | |
JP2004520778A (en) | Parallel data communication with skew-tolerant data groups | |
US8572300B2 (en) | Physical coding sublayer (PCS) architecture for synchronizing data between different reference clocks | |
US7339995B2 (en) | Receiver symbol alignment for a serial point to point link | |
JP2007502570A (en) | Automatic realignment of multiple serial byte lanes | |
US11424905B1 (en) | Retimer with mesochronous intra-lane path controllers | |
US7321613B2 (en) | Automatic impedance matching compensation for a serial point to point link | |
KR102518285B1 (en) | PCIe INTERFACE AND INTERFACE SYSTEM |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200480039271.2 Country of ref document: CN |
|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 0608721.7 Country of ref document: GB Ref document number: 0608721 Country of ref document: GB |
|
RET | De translation (de og part 6b) |
Ref document number: 112004002567 Country of ref document: DE Date of ref document: 20061214 Kind code of ref document: P |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112004002567 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase | ||
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8607 |