WO2005069260A2 - Display device, data driving circuit, and display panel driving method - Google Patents

Display device, data driving circuit, and display panel driving method Download PDF

Info

Publication number
WO2005069260A2
WO2005069260A2 PCT/JP2005/000731 JP2005000731W WO2005069260A2 WO 2005069260 A2 WO2005069260 A2 WO 2005069260A2 JP 2005000731 W JP2005000731 W JP 2005000731W WO 2005069260 A2 WO2005069260 A2 WO 2005069260A2
Authority
WO
WIPO (PCT)
Prior art keywords
current
voltage
lines
selection
transistor
Prior art date
Application number
PCT/JP2005/000731
Other languages
French (fr)
Other versions
WO2005069260A3 (en
Inventor
Tomoyuki Shirasaki
Kazuhito Sato
Original Assignee
Casio Computer Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=34747204&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2005069260(A2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Casio Computer Co., Ltd. filed Critical Casio Computer Co., Ltd.
Priority to EP05703959A priority Critical patent/EP1714266A2/en
Publication of WO2005069260A2 publication Critical patent/WO2005069260A2/en
Publication of WO2005069260A3 publication Critical patent/WO2005069260A3/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G09G2310/0256—Control of polarity reversal in general, other than for liquid crystal displays with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to a display panel driving method of driving a display panel including a light-emitting element for each pixel, a data driving circuit for driving the display panel, and a display device including the display panel, the data driving circuit, and a selection scan driver.
  • liquid crystal displays are classified into active matrix driving type liquid crystal displays and simple matrix driving type liquid crystal displays.
  • the active matrix driving type liquid crystal displays display images having contrast and resolution higher than those displayed by the simple matrix driving type liquid crystal displays.
  • a liquid crystal element which also functions as a capacitor, and a transistor which functions as a pixel switching element are formed for each pixel.
  • the active matrix driving system when a voltage at a level representing luminance is applied to a current line by a data driver while a scan line is selected by a scan driver serving as a shift register, this voltage is applied to the liquid crystal element via the transistor. Even when the transistor is turned off in a period after the selection of the scan line is complete and before the scan line is selected again, the liquid crystal element functions as a capacitor, so the voltage level is held in this period. As described above, the light transmittance of the liquid crystal element is refreshed while the scan line is selected, and light from a backlight is transmitted through the liquid crystal element having the refreshed light transmittance. In this manner, the liquid crystal display expresses a tone.
  • Displays using organic EL (ElecctroLuminescent ) elements as self-light-emitting elements require no such a backlight as used in the liquid crystal displays, and hence are optimum for flat display devices.
  • the viewing angle is not limited unlike in the liquid crystal display. Therefore, these organic EL displays are increasingly expected to be put into practical use as next-generation display devices.
  • active matrix driving type organic EL displays are developed similarly to the liquid crystal displays. For example, in the conventional active matrix driving type organic EL display described in Jpn. Pat. Appln. KOKAI Publication No. 2000-221942, a pixel circuit (referred to as an organic EL element driving circuit in patent reference 1) is formed for each pixel.
  • This pixel circuit includes an organic EL element, driving TFT, first switching element, switching TFT, and the like.
  • a current source driver applies a voltage as luminance data to the gate of the driving TFT. Consequently, the driving TFT is turned on, and a driving current having a current value corresponding to the level of the gate voltage flows from a power supply line to the driving TFT via the organic EL element, so the organic EL element emits light at luminance corresponding to the current value of the electric current.
  • the gate voltage of the driving TFT is held by the first switching element, so the emission of the organic EL element is also held.
  • the gate voltage of the driving TFT decreases to turn it off, and the organic EL element is also turned off to complete one frame period.
  • the channel resistance of a transistor changes in accordance with a change in ambient temperature, or changes when the transistor is used for a long time.
  • the gate threshold voltage changes with time, or differs from one transistor to another.
  • an object of the present invention to provide a display device, data driving circuit, and display panel driving method capable of displaying high-quality images.
  • a display device comprises, a plurality of selection scan lines; a plurality of current lines; a selection scan driver which sequentially selects the plurality of selection scan lines in each selection period; a data driving circuit which applies a reset voltage to the plurality of current lines in a first part of the selection period, and supplies a designating current having a current value corresponding to an image signal to the plurality of current lines in a second part of the selection period after applying the reset voltage in the selection period; and a plurality of pixel circuits which are connected to the plurality of selection scan lines and the plurality of current lines, and supply a driving current having a current value corresponding to the current value of the designating current which flows through the plurality of current lines.
  • a display device comprises, a plurality of selection scan lines; a plurality of current lines; a plurality of light-emitting elements which are arranged at intersections of the plurality of selection scan lines and the plurality of current lines, and emit light at luminance corresponding to a current value of a driving current; a selection scan driver which sequentially select the plurality of selection scan lines in each selection period; a data driving circuit which applies a reset voltage to the plurality of current lines in a first part of the selection period, and supplies a designating current having a current value corresponding to an image signal to the plurality of current lines in a second part of the selection period after applying the reset voltage in the selection period; and a plurality of pixel circuits which are connected to the plurality of selection scan lines and the plurality of current lines, and electrically connect the plurality of current lines and the plurality of light-emitting elements to each other in the selection period.
  • a data driving circuit comprises, a plurality of light-emitting elements connected to a plurality of selection scan lines and a plurality of current lines, a selection scan driver which sequentially selects the plurality of selection scan lines in each selection period, and a plurality of pixel circuits connected to the plurality of light-emitting elements, wherein a reset voltage is applied to the plurality of current lines in a first part of the selection period, and a designating current having a current value corresponding to an image signal is supplied to the plurality of current lines in a second part of the selection period after the first part of the selection period.
  • a display panel driving method comprises, a selection step of sequentially selecting a plurality of selection scan lines of a display panel comprising a plurality of pixel circuits connected to the plurality of selection scan lines and a plurality of current lines, and a plurality of light-emitting elements which are arranged at intersections of the plurality of selection scan lines and the plurality of current lines, each of the light-emitting elements emits light at luminance corresponding to a current value of a current flowing the current line; and a reset step of applying a reset voltage to the plurality of current lines in an initial part of a period in which each of the plurality of selection scan lines is selected.
  • FIG. 1 is a block diagram of an organic electroluminescent display 1 according to the first embodiment of the present invention
  • FIG. 2 is a plan view of a pixel Pj_,j of the organic electroluminescent display 1
  • FIG. 3 is an equivalent circuit diagram of four adjacent pixels Pj.,j, p i+l,j' p i,j +l» and p i+l,j+l of the organic electroluminescent display 1;
  • FIG. 1 is a block diagram of an organic electroluminescent display 1 according to the first embodiment of the present invention
  • FIG. 2 is a plan view of a pixel Pj_,j of the organic electroluminescent display 1
  • FIG. 3 is an equivalent circuit diagram of four adjacent pixels Pj.,j, p i+l,j' p i,j +l» and p i+l,j+l of the organic electroluminescent display 1
  • FIG. 1 is a block diagram of an organic electroluminescent display 1 according to the first embodiment of
  • FIG. 4 is a timing chart showing the levels of signals in the organic electroluminescent display 1;
  • FIG. 5 is a graph showing the current-voltage characteristics of an N-channel field-effect transistor;
  • FIG. 6 shows an equivalent circuit diagram of two adjacent pixels Pj_,j and Pj ⁇ j+i in the ith row, and the states of electric currents and voltages in a reset period TR of the ith row;
  • FIG. 7 shows the equivalent circuit diagram of the two adjacent pixels P_ j and Pj_ j+i in the ith row, and the states of electric currents and voltages after the reset period Tp> in a selection period Tgg °f the ith row;
  • FIG. 8 shows the equivalent circuit diagrams of the two adjacent pixels p i,j and Pj .
  • FIG. 9 is a timing chart showing the levels of electric currents and voltages pertaining to the pixel Pi,j;
  • FIG. 10 is a block diagram of an organic electroluminescent display according to the second embodiment of the present invention;
  • FIG. 11 is a block diagram of an organic electroluminescent display according to the third embodiment of the present invention;
  • FIG. 12 is a block diagram of an organic electroluminescent display according to the fourth embodiment of the present invention. Best Mode for Carrying Out the Invention Best modes for carrying out the invention will be described below with reference to the accompanying drawings.
  • FIG. 1 is a block diagram showing an organic electroluminescent display 1 according to the first embodiment to which the organic electroluminescent display of the present invention is applied.
  • the organic electroluminescent display 1 includes, as its basic configuration, an organic electroluminescent display panel 2 having m selection scan lines X ] _ to X m , m voltage supply lines Z]_ to Z m , n current lines Y to Y n , and pixels P]_ to P m n .
  • the display 1 further includes, a scan driving circuit 9 for linearly scanning the organic electroluminescent display panel 2 in the longitudinal direction, and a data driving circuit 7 for supplying a tone designating current IoATA to the current lines Y to Y n in cooperation with the scan driving circuit 9.
  • each of m and n is a natural number of 2 or more.
  • the can driving circuit 9 has a selection scan driver 5 for sequentially selecting the selection scan lines X ] _ to X m , and a voltage supply driver 6 for sequentially selecting the voltage supply lines Z to Z n in synchronism with the sequential selection of the selection scan lines X ⁇ to X m by the selection scan driver 5.
  • the data driving circuit 7 has a current source driver 3.
  • the driver 3 includes n current terminals CT ] _ to CT n and allows the tone designating current IoATA to flow through the current terminals CT ] _ to CT n , and switches S to S n interposed between the current terminals CT]_ to CT n and current lines Yi to Y n .
  • the organic electroluminescent display panel 2 has a structure in which a display unit 4 for practically displaying images is formed on a transparent substrate.
  • the selection scan driver 5, voltage supply driver 6, current source driver 3, and switches S]_ to S n are arranged around the display unit 4.
  • Portions or the whole of the selection scan driver 5, the voltage supply driver 6, the current source driver 3, and at least one of the switches S]_ to S n can be integrated with the organic electroluminescent display panel 2 as they are formed on the transparent substrate, or can be formed around the organic electroluminescent display panel 2 as they are formed into a chip different from the organic electroluminescent display panel 2.
  • the display unit 4 may also be formed on a flexible sheet such as a resin sheet, instead of the transparent substrate.
  • the (m x n) pixels P_ to P m n are formed in a matrix on the transparent substrate such that m pixels are arranged in the longitudinal direction, i.e., the column direction, and n pixels are arranged in the lateral direction, i.e., the row direction.
  • a pixel which is an ith pixel (i.e., a pixel in the ith row) from above and a jth pixel (i.e., a pixel in the jth column) from left is a pixel p i,j»
  • i is a given natural number from 1 to m
  • the m selec- tion scan lines to X m running in the row direction are formed parallel to each other on the transparent substrate.
  • the m voltage supply lines Z to Z m running in the row direction are formed parallel to each other on the transparent substrate in one-to-one correspondence with the selection scan lines X]_ to X m .
  • the voltage supply line Zj ⁇ (1 ⁇ k ⁇ m - 1) is positioned between the selection scan lines Xj ⁇ and X ⁇ +1 / and the selection scan line X m is positioned between the voltage supply lines Z m _ ⁇ and Z m .
  • the n current lines Y to Y n running in the column direction are formed parallel to each other on the upper side of the transparent substrate.
  • the selection scan lines to X m , voltage supply lines to Z m , and current lines Y to Y n are insulated from each other as they are separated by insulating films or the like interposed between them.
  • the n pixels Pj_ to Pi n arranged along the row direction are connected to the selection scan line Xj_ and voltage supply line Zj_ in the ith row.
  • the m pixels Pi j to P m j arranged along the column direction are connected to the current line Yj in the jth column.
  • the pixel p i,j is positioned at the intersection of the selection scan line Xj_ and current line Yj .
  • the selection scan lines Xl to X m are connected to output terminals of the selection scan driver 5.
  • the voltage supply lines to Z m are connected to output terminals of the voltage supply driver 6.
  • the pixels P ] _ l to P m n will be explained below with reference to FIGS. 2 and 3.
  • FIG. 2 is a plan view showing the pixel i,j- FIG.
  • FIG - 2 is an equivalent circuit diagram showing, e.g., four adjacent pixels p i,j' p i+l,j> p i,j+l' and p i+l,j+l-
  • FIG - 2 principally shows the electrodes in the pixel p i,j to allow better understanding.
  • the pixel Pj_ j includes an organic electroluminescent element Ej_ j as a self-light-emitting element which emits light in accordance with the value of an electric current, and a pixel circuit D-j_ j which is formed around the organic electroluminescent element Ej_ j, and drives it. Note that the organic electroluminescent element will be referred to as an organic EL element hereinafter.
  • the organic EL element Ej_ j has a stacked structure in which a pixel electrode 51, organic EL layer 52, and common electrode are stacked in this order on the transparent substrate.
  • the pixel electrode 51 functions as an anode.
  • the organic EL layer 52 functions as a light-emitting layer in a broad sense, i.e., transports holes and electrons injected by an electric field, recombines the transported holes and electrons, and emits light by excitons produced by the recombination.
  • the common electrode functions as a cathode. Although the common electrode is formed to cover the entire pixel, the it is not shown in FIG. 2 so that the pixel electrode 51, organic EL layer 52, pixel circuit Dj_ and the like are readily seen.
  • the pixel electrode 51 is patterned for each of the pixels P]_ l to P m n in each of regions surrounded by the current lines Y ] _ to Y n , selection scan lines X]_ to X m , and voltage supply lines Z_ to Z m .
  • the pixel electrode 51 is a transparent electrode.
  • the pixel electrode 51 has both conductivity and transparency to visible light. Also, the pixel electrode 51 preferably has a relatively high work function, and efficiently injects holes into the organic EL layer 52.
  • main components of the pixel electrode 51 are tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In2 ⁇ 3), tin oxide (Sn ⁇ 2), zinc oxide (ZnO), and cadmium-tin oxide (CTO) .
  • the organic EL layer 52 is formed on each pixel electrode 51. The organic EL layer 52 is also patterned for each of the pixels ? ⁇ ]_ to P m n .
  • the organic EL layer 52 contains a light-emitting material (phosphor) as an organic compound.
  • This light-emitting material can be either a high- or low-molecular material.
  • the organic EL layer 52 has a two-layered structure in which a hole transporting layer and a light-emitting layer in a narrow sense are stacked in this order on the pixel electrode 51.
  • the hole transporting layer is made of a PEDOT
  • the light-emitting layer in a narrow sense is made of a polyfluorene-based, light-emitting material.
  • the organic EL layer 52 may also have a three-layered structure having a hole transporting layer, a light-emitting layer in a narrow sense, and an electron transporting layer stacked in this order on the pixel electrode 51, or a single-layered structure having only a light-emitting layer in a narrow sense, instead of the two-layered structure.
  • the organic EL display panel 2 can display full-color images or multicolor images.
  • the organic EL layer 52 of each of the pixels P]_ to P m n is a light-emitting layer in a broad sense which has a function of emitting red, green, or blue light. That is, the organic EL layers 52 which emit red light, green light, and blue light are regularly arranged, and the display unit 4 displays images in a color tone obtained by properly synthesizing these colors.
  • the organic EL layer 52 is desirably made of an organic compound which is neutral with respect of electrons.
  • an electron transporting substance and hole transporting substance may also be properly mixed in the light-emitting layer in a narrow sense. It is also possible to cause a charge transporting layer which is an electron or hole transporting layer to function as a recombination region which recombines electrons and holes, and to emit light by mixing a phosphor in this charge transporting layer.
  • the common electrode formed on the organic EL layers 52 is formed for all the pixels P]_ _ to P m n .
  • this common electrode formed for all the pixels P]_ to P m n it is also possible to use a plurality of divided electrodes, e.g., a plurality of stripe electrodes divided for individual columns, or a plurality of stripe electrodes divided for individual rows.
  • the organic EL layers 52 which emit different colors are made of different materials, and the light emission characteristics with respect to the current density depend upon the material. To adjust the luminance balance between different emission colors, therefore, pixels which emit the same color can be connected together in order to set the value of an electric current for each emission color of the organic EL layer 52.
  • the emission color balance can be adjusted by supplying, to the second-emission-color pixel, a tone electric current which is larger than that of the first-emission-color pixel.
  • the common electrode is electrically insulated from the selection scan lines X_ to X m , current lines Yl to Y n , and voltage supply lines Z to Z m .
  • the common electrode is made of a material having a low work function.
  • the common electrode is made of indium, magnesium, calcium, lithium, barium, a rare earth metal, or an alloy containing at least one of these elements.
  • the common electrode can have a stacked structure in which layers of the various materials described above are stacked, or a stacked structure in which a metal layer is deposited in addition to these layers of the various materials.
  • Practical examples are a stacked structure including a low-work-function, high-purity barium layer formed in the interface in contact with the organic EL layer 52, and an aluminum layer which covers this barium layer, and a stacked structure having a lithium layer as a lower layer and an aluminum layer as an upper layer.
  • the common electrode When the pixel electrode 51 is a transparent electrode and light emitted from the organic EL layer 52 is output from the transparent substrate through the pixel electrode 51, the common electrode preferably has light-shielding properties with respect to the light emitted from the organic EL layer 52, and more preferably has a high reflectance to the light emitted from the organic EL layer 52.
  • a forward bias voltage by which the voltage of the pixel electrode 51 becomes higher than that of the common electrode
  • holes are injected into the organic EL layer 52 from the pixel electrode 51, and electrons are injected into the organic EL layer 52 from the common electrode.
  • the organic EL layer 52 transports these holes and electrons, and recombines them to produce excitons. Since these excitons excite the organic EL layer 52, the organic EL layer 52 emits light.
  • the luminance of the organic EL element Ej_ j depends on the current value of an electric current which flows through the organic EL element E_ j ; the larger the electric current which flows through the organic EL element Ej_ j , the higher the luminance of the organic EL element Ej_ j. That is, if deterioration of the organic EL element Ej_ j is not taken into consideration, the luminance of the organic EL element Ej_ j is uniquely determined when the current value of the electric current which flows through the organic EL element Ej_ j is determined.
  • Each of the pixel circuits D]_ to D m n includes three thin-film transistors (to be simply referred to as transistors hereinafter) 21, 22, and 23, and a capacitor 24. Each of the transistors 21, 22, and 23 is an
  • N-channel MOS field-effect transistor having a gate, drain, source, semiconductor layer 44, impurity-dosed semiconductor layer, and gate insulating film.
  • Each transistor is particularly an a-Si transistor in which the semiconductor layer 44 (channel region) is made of amorphous silicon.
  • each transistor may also be a p-Si transistor in which the semiconductor layer 44 is made of polysilicon.
  • the transistors 21, 22, and 23 are N-channel field-effect transistors, and can have either an inverted stagger structure or a coplanar structure. Also, the transistors 21, 22, and 23 can be simultaneously formed in the same process.
  • the compositions of the gates, drains, sources, semiconductor layers 44, impurity-dosed semiconductor layers, and gate insulating films of the transistors 21, 22, and 23 are the same, and the shapes, sizes, dimensions, channel widths, and channel lengths of the transistors 21, 22, and 23 are different from each other in accordance with the functions of the transistors 21, 22, and 23.
  • the transistors 21, 22, and 23 will be referred to as a first transistor 21, second transistor 22, and driving transistor 23, respectively, hereinafter.
  • the capacitor 24 has a first electrode 24A connected to a gate 23g of the driving transistor 23, a second electrode 24B connected to a source 23s of the transistor 23, and a gate insulating film (dielectric film) interposed between these two electrodes.
  • the capacitor 24 has a function of storing electric charges between the gate 23g and source 23s of the driving transistor 23.
  • a gate 22g is connected to the selection scan line Xj_ in the ith row, and a drain 22d is connected to the voltage supply line Zj_ in the ith row.
  • a drain 23d is connected to the voltage supply line Zj_ in the ith row through a contact hole 26.
  • a gate 21g is connected to the selection scan line Xj_ in the ith row.
  • a source 21s is connected to the current line Yj in the jth column.
  • a source 22s of the second transistor 22 is connected to the gate 23g of the driving transistor 23 through a contact hole 25, and to one electrode of the capacitor 24.
  • the source 23s of the driving transistor 23 is connected to the other electrode of the capacitor 24, and to a drain 21d of the first transistor 21.
  • the source 23s of the driving transistor 23, the other electrode of the capacitor 24, and the drain 21d of the first transistor 21 are connected to the pixel electrode 51.
  • the voltage of the common electrode of the organic EL elements E]_ l to E m n is held at a predetermined reference voltage Vgg.
  • the reference voltage Vgs is set at 0 [V] by grounding the common electrode of the organic EL elements E_ t° Em,n #
  • the pixel electrodes 51 are divided by patterning for individual pixels surrounded by regions surrounded by the current lines Y to Y n , selection scan lines X]_ to X m , and voltage supply lines to Z m .
  • each pixel electrode 51 is covered with an interlayer dielectric film made of silicon nitride or silicon oxide which covers the three transistors 21, 22, and 23 of each pixel circuit, and the upper surface of the center of the pixel electrode 51 is exposed through a contact hole 55 formed in this interlayer dielectric film.
  • the interlayer dielectric film can have a first layer made of silicon nitride or silicon oxide, and a second layer formed on the first layer by using an insulating film made of, e.g., polyimide.
  • a protective film 44A is formed by patterning the same film as the semiconductor layer 44 of each of the transistors 21 to 23, in addition to the gate insulating film. Note that in order to protect the surface, which serves as a channel, of the semiconductor layer 44 of each of the transistors 21, 22, and 23 from being roughened by an etchant used in patterning, a blocking insulating layer made of silicon nitride or the like may also be formed except for the two end portions of the semiconductor layer 44.
  • a protective film may be formed by patterning the same film as the blocking insulating layer between the selection scan line Xj_ and current line Yj , and between the voltage supply line Zj_ and current line Yj .
  • This protective film and the protective film 44A may also be overlapped.
  • FIG. 4 is a timing chart showing, from above, the voltage of the selection scan line X ] _, the voltage of the voltage supply line Z ⁇ , the voltage of the selection scan line X2, the voltage of the voltage supply line Z2, the voltage of the selection scan line X3, the voltage of the voltage supply line Z3, the voltage of the selection scan line X m , the voltage of the voltage supply line Z m , the level (voltage value) of a switching signal inv. ⁇ , the level of a switching signal ⁇ , the voltage of the current line Yj , the voltage of the pixel electrode 51 of the organic EL element E ] _ j , the luminance of the organic EL element E ] _ j, the voltage of the pixel electrode 51 of the organic EL element E2,j' and the luminance of the organic EL element E2,j- Referring to FIG.
  • the selection scan driver 5 is a so-called shift register, and has an arrangement in which m flip-flop circuits and the like are connected in series. That is, the selection scan driver 5 sequentially selects the selection scan lines X]_ to X m by sequentially outputting selection signals in order from the selection scan line X ⁇ to the selection scan line X m (the selection scan line X m is followed by the selection scan line X ⁇ ) , thereby sequentially selecting the first and second transistors 21 and 22 in these rows connected to the selection scan lines X ⁇ to X m . More specifically, as shown in FIG.
  • the selection scan driver 5 individually applies, to the selection scan lines to X m , a high-level (ON-level) ON voltage V Q N (much higher than the reference voltage Vgg) as a selection signal or a low-level OFF voltage v OFF (equal to or lower than the reference voltage Vgg) as a non-selection signal, thereby sequentially selecting the selection scan lines X ⁇ to X m . That is, when the selection scan driver 5 applies the ON voltage V Q N to the selection scan line Xj_, the selection scan line Xj_ in the ith row is selected.
  • a period in which the selection scan driver 5 applies the ON voltage V Q N to the selection scan line Xj_ in the ith row and thereby selects the selection scan line X ⁇ in the ith row is called a selection period Tgg of the ith row.
  • the selection scan driver 5 applies the OFF voltage VQFF to the other selection scan lines X]_ to X m (except for the selection scan line Xj_) . Accordingly, the selection periods Tgj of the selection scan lines X ] _ to X m do not overlap each other.
  • the selection scan driver 5 applies the ON voltage V Q N to the selection scan line Xj_ in the ith row, the first and second transistors 21 and 22 are turned on in each of the pixel circuits Dj_ ⁇ to Dj_ ?n connected to the selection scan line Xj_ in the ith row. Since the first transistors 21 are turned on, an electric current which flows through the current lines Y]_ to Y n can flow through the pixel circuits Dj_ to Di, n . After the selection period Tgg in which the selection scan line X_ in the ith row is selected, the selection scan driver 5 applies the OFF voltage VQFF to the selection scan line X_ to cancel the selection of the selection scan line Xj_ .
  • the first and second transistors 21 and 22 are turned off. Since the first transistors 21 are turned off, the electric current which flows through the current lines Y ] _ to Y n cannot flow through the pixel circuits Dj_ l to Dj_ n any longer.
  • a period in which the selection scan driver 5 applies the OFF voltage V Q F to the selection scan line X ⁇ in the ith row and thereby keeps the selection scan line Xj_ in the ith row unselected is called a non-selection period T ⁇ gg of the ith row.
  • a period represented by TgE + TNSE T SC' i.e., a period from the start time of the selection period Tg j of the selection scan line Xj_ in the ith row to the start time of the next selection period TgE °f the selection scan line Xj_ in the ith row, is one frame period of the ith row.
  • the voltage supply driver 6 is a so-called shift register, and has an arrangement in which m flip-flop circuits are connected in series.
  • the voltage supply driver 6 sequentially selects the voltage supply lines Z ⁇ to Z m by sequentially outputting selection signals in order from the voltage supply line Z to the voltage supply line Z m (the voltage supply line Z m is followed by the voltage supply line Z ] _) , thereby sequentially selecting the driving transistors 23 in these rows connected to the voltage supply lines Z]_ to Z m . More specifically, as shown in FIG.
  • the voltage supply driver 6 individually supplies, to the voltage supply lines to Z m , a low-level tone designating current reference voltage VLQW (which is equal to or lower than the reference voltage Vgs) as a selection signal or a high-level driving current reference voltage V ⁇ IQH (which is higher than both the reference voltage Vgs and tone designating current reference voltage VLQ ) as a non-selection signal, thereby sequentially selecting the voltage supply lines Z]_ to Z m .
  • VLQW low-level tone designating current reference voltage
  • V ⁇ IQH which is higher than both the reference voltage Vgs and tone designating current reference voltage VLQ
  • the voltage supply driver 6 applies the tone designating current reference voltage VJ ⁇ Q to the voltage supply line Zj_ in the ith row, thereby selecting the voltage supply line Zj_ in the ith row. While applying the tone designating current reference voltage VLQW to the voltage supply line Zj_, the voltage supply driver 6 applies the driving current reference voltage V H GH to the other voltage supply lines Z]_ to Z m (except for the voltage supply line Zj_) .
  • the voltage supply driver 6 applies the driving current reference voltage V ⁇ JQ ⁇ to the voltage supply line Zj_ to cancel the selection of the voltage supply line Zj_ in the ith row. Since the driving current reference voltage V ⁇ J Q H is higher than the reference voltage Vgg, an electric current flows from the voltage supply line Zj_ to the organic EL element Ej_ j if the driving transistor 23 is ON and the transistor 21 is OFF.
  • the tone designating current reference voltage v LOW applied by the voltage supply driver 6 is equal to or lower than the reference voltage Vgg.
  • the driving current reference voltage V ⁇ JQ ⁇ i- s so set that a source-to-drain voltage V of the driving transistor 23 is in a saturated region. Accordingly, when the driving transistors 23 are ON in the non-selection period T ⁇ SE' a forward bias voltage is applied to the organic EL elements E]_ ]_ to E m n . In the non-selection period T ⁇ gg, therefore, an electric current flows through the organic EL elements E]_ ]_ to E m n , and the organic EL elements E]_ to E m n emit light.
  • the driving current reference voltage V ⁇ JQ ⁇ will be explained below.
  • FIG. 5 is a graph showing the current-voltage characteristics of the N-channel field-effect transistor. Referring to FIG.
  • the abscissa indicates the divided voltage of the driving transistor and the divided voltage of the organic EL element connected in series to the driving transistor, and the ordinate indicates the current value of an electric current in the drain-to-source path.
  • the drain saturated threshold voltage V ⁇ H is a function of a gate-to-source voltage Vgg, and is uniquely determined by the gate-to-source voltage Vgg if the gate-to-source voltage Vg is determined
  • a drain-to-source current Ir j g increases as the source-to-drain voltage Vpg increases.
  • gate-to-source voltages Vggi to V GSMAX have the relationship 0 [V] ⁇ V GS1 ⁇ V GS2 ⁇ V GS3 ⁇ ⁇ GS4 ⁇ VGSMAX- That is, as is apparent from FIG.
  • the drain-to-source current Irjg increases in both the unsaturated and saturated regions as the gate-to-source voltage V G g increases.
  • the drain saturated threshold voltage V ⁇ H increases as the gate-to-source voltage V G g increases. From the foregoing, in the unsaturated region, the drain-to-source current Irjg changes if the source-to-drain voltage Vp slightly changes while the gate-to-source voltage V G g is constant. In the saturated region, however, the drain-to-source current Ir j g is uniquely determined by the gate-to-source voltage V G g.
  • the drain-to-source current Ipg when the maximum gate-to-source voltage V G g ⁇ AX is applied to the driving transistor 23 is set to be an electric current which flows between the common electrode and the pixel electrode 51 of the organic EL element Ej_ ⁇ j which emits light at the maximum luminance. Also, the following equation is met so that the driving transistor 23 maintains the saturated region in the selection period Tg j ? even when the gate-to-source voltage V G g of the driving transistor 23 is the maximum voltage V G g ⁇ [A ⁇ in the non-selection period.
  • V HIGH _V E - V SS V THMAX
  • Vg is the anode-to-cathode voltage which the organic EL element Ej_ j requires to emit light at the maximum luminance in the light emission life period
  • VTH AX i s the source-to-drain saturated voltage level of the driving transistor 23 when the voltage is V G M ⁇ .
  • the driving current reference voltage V ⁇ J Q J-J is set to satisfy the above equation.
  • the source-to-drain voltage Vpg of the driving transistor 23 decreases by the divided voltage of the organic EL element Ej_ j connected in series to the driving transistor 23, the source-to-drain voltage Vrjg always falls within the range of the saturated state, so the drain-to-source current Irjg is uniquely determined by the gate-to-source voltage V G g.
  • the current lines Y]_ to Y n are connected to the current terminals CT]_ to
  • the current source driver 3 controls the current value of the tone designating current IQATA a t the current terminals CT_ to CT n in accordance with the image signal for each selection period T g of each row, and holds the current value of the tone designating current IQATA constant in a period from the end of each reset period TR to the end of the corresponding selection period Tgg.
  • the current source driver 3 supplies the tone designating current iDATA from the current lines Y]_ to Y n to the current terminals CT ] _ to CT n via the switches S]_ to S n .
  • the switches S]_ to S n are connected to the current lines Y]_ to Y n , and the current terminals CT]_ to CT n of the current source driver 3 are connected to the switches S]_ to S n .
  • the switches S j. to S n are connected to a reset input terminal 41, and a reset voltage VR is applied to the switches S ] _ to S n via the reset input terminal 41.
  • the switches S to S n are also connected to a switching signal input terminal 42, and a switching signal ⁇ is input to the switches S_ to S n via the switching signal input terminal 42.
  • the switches S]_ to S n are connected to a switching signal input terminal 43, and a switching signal inv.
  • the reset voltage VR is constant and has the same level (voltage value) as the tone designating current reference voltage VLQW- More specifically, the reset voltage VR is set at 0 [V] by grounding the reset input terminal 41. Especially when the reset voltage VR of the ith row is made equal to the voltage of the voltage supply line Zj_ in the ith row in the selection period Tgg, the voltages of the electrodes 24A and 24B of the capacitor 24 become equal to each other. Consequently, the capacitor 24 is discharged, so the gate-to-source voltage of the driving transistor 23 is set at 0V.
  • the switch S j (which is interposed between the current line Y j in the jth column and the current terminal CT j in the jth column) switches the state in which the current source driver 3 supplies the tone designating current IQATA to the current line Yj , and the state in which the reset voltage VR is applied to the current line Y j . That is, as shown in FIG.
  • the switch Sj shuts off the electric current of the current terminal CTj , and applies the reset voltage VR to the current line Yj , the drain 21d of the first transistor 21, the electrode 24B of the capacitor 24, the source 23s of the driving transistor 23, and the pixel electrode 51 of the organic EL element E x? j (1 ⁇ x ⁇ m), thereby discharging the electric charge stored in these components in the preceding selection period Tgg.
  • the switch Sj allows the electric current of the current terminal CTj to flow through the current line Yj , and shuts down the application of the reset voltage VR to the current line Yj .
  • the cycle of the switching signals ⁇ and inv. ⁇ will be explained below. As shown in FIG. 4, the cycle of the switching signals ⁇ and inv. ⁇ is the same as the selection period Tgg.
  • the selection scan driver 5 starts applying the ON voltage V Q N to one of the selection scan lines X ] _ to X m (i.e., when the selection period Tgg of each row starts)
  • the switching signal ⁇ changes from high level to low level
  • the switching signal inv. ⁇ changes from low level to high level
  • the selection scan driver 5 is applying the ON voltage V Q N to one of the selection scan lines Xl to X m (i.e., in the selection period Tgg of each row)
  • the switching signal ⁇ changes from low level to high level
  • the switching signal inv. ⁇ changes from high level to low level.
  • a period in which the switching signal ⁇ is at high level and the switching signal inv.
  • the switch Sj is made up of first and second N-channel field-effect transistors 31 and 32.
  • the gate of the first transistor 31 is connected to the switching signal input terminal 43, and thus the switching signal inv. ⁇ is input to the gate of the transistor 31.
  • the gate of the second transistor 32 is connected to the switching signal input terminal 42, and thus the switching signal ⁇ is input to the gate of the transistor 32.
  • the drain of the first transistor 31 is connected to the current line Yj , and the source of the transistor 31 is connected to the current terminal CTj .
  • the drain of the transistor 32 is connected to the current line Yj .
  • the source of the transistor 32 is connected to the reset input terminal 41, and the reset voltage VR which is a constant voltage is applied to the source of the transistor 32.
  • the transistor 32 when the switching signal ⁇ is at high level and the switching signal inv. ⁇ is at low level, the transistor 32 is turned on, and the transistor 31 is turned off.
  • the transistor 31 is turned on, and the transistor 32 is turned off.
  • the transistors 31 and 32 can be fabricated in the same steps as the transistors 21 to 23 of the pixel circuits D]_ to D m n .
  • FIG. 6 is a circuit diagram showing the states of the voltages in the reset period TR of the selection period Tg j r of the ith row.
  • the selection scan driver 5 applies the ON voltage V Q N to the selection scan line Xj_
  • the voltage supply driver 6 applies the tone designating current reference voltage VLQW to the voltage supply line Zj_.
  • the switches S to S n apply the reset voltage VR to the current lines Y to Y n .
  • the first transistors 21 of the pixel circuits Dj_ 1 to Dj_ n are ON. Consequently, as shown in FIG. 4, the voltages of the pixel electrodes 51 of the organic EL elements Ej_ i to Ej_ n , the drains 21d of the first transistors 21 in the ith row, the electrodes 24B of the capacitors 24 in the ith row, the sources 23s of the driving transistors 23 in the ith row, and the current lines Y]_ to Y n are set in a steady state by the reset voltage VR, thereby discharging the electric charge stored by these parasitic capacitances in the preceding selection period Tgg.
  • the tone designating current IoATA having a steady current value can be rapidly written in the next selection period Tgg.
  • the parasitic capacitances of the organic EL elements Ej_ l to Ej_ n are particularly large. Therefore, when the tone designating current IoATA having a low current value is written, it takes a long time to make the current value steady by resetting the electric charge written in the organic EL element in the preceding frame period Tg G if the reset voltage VR is not applied in the selection period Tgg.
  • the reset voltage VR is forcedly applied in the selection period T g, so the parasitic capacitance of the organic EL element can be rapidly discharged. Also, when the reset voltage VR of the ith row, which is applied in the selection period T g is made equal to that of the voltage supply line Zj_ in the ith row, the voltages of the electrodes 24A and 24B of the capacitor 24 become equal to each other, so the electric charges written in the capacitor 24 in the preceding frame period Tg G are removed.
  • FIG. 7 is a circuit diagram showing the states of the electric currents and voltages after the reset period TR in the selection period Tgg of the ith row. As shown in FIG.
  • the selection scan driver 5 keeps applying the ON voltage V Q N to the selection scan line Xj_
  • the voltage supply driver 6 keeps applying the tone designating current reference voltage L Q W to the voltage supply line Zj_.
  • the current source driver 3 controls the switches S]_ to S n to supply the tone designating current IQATA f rom the current lines Y]_ to Y n to the current terminals CT ⁇ to CT n .
  • the second transistors 22 of the pixel circuits Dj_ l to D_ n in the ith row are ON.
  • the voltage is also applied to the gates 23g of the driving transistors 23 of the pixel circuits Dj_ _ to Dj_ n , so the driving transistors 23 of the pixel circuits Dj_ j_ to Dj_ n are turned on. Furthermore, since the first transistors 21 of the pixel circuits Dj_ 1 to Dj_ n are also ON, the first transistors 21 of the pixel circuits Dj_ l to Dj_ n supply the tone designating current I ATA f ro the voltage supply line Z_ to the current lines Y ⁇ to Y n via the drains 23d and sources 23s of the driving transistors 23.
  • the voltage of the current line Yj drops until the tone designating current I ATA becomes steady. Also, although the driving transistors 23 of the pixel circuits Dj_ l to Dj_ n are ON, the low-level tone designating current reference voltage ILOW i s applied to the voltage supply line Z_, so no electric current flows from the voltage supply line Z to the organic
  • the current value of the tone designating current ID A TA flowing through the current lines Y to Y n becomes equal to the current value of the electric current Irjg between the drain 23d and source 23s of the driving transistor 23.
  • the level of the voltage between the gate 23g and source 23s of the driving transistor 23 follows the current value of the tone designating current ID A TA which flows from the drain 23d to the source 23s. Accordingly, the driving transistor 23 converts the current value of the tone designating current IDATA into the level of the voltage between the gate 23g and source 23s, and electric charges corresponding to the level of the voltage between the gate 23g and source 23s of the driving transistor 23 are held in the capacitor 24.
  • the gate 23g and drain 23d of the driving transistor 23 are connected via the second transistor 22, and the ON resistance of the second transistor 22 upon selection is negligibly low. Therefore, the voltage applied to the gate 23g and the voltage applied to the drain 23d of the driving transistor 23 are substantially equal, so the tone designating current IoATA becomes the electric current Ir j g which changes on the broken line VTH shown in FIG. 5. That is, when the voltages of the gate 23g and drain 23d of the driving transistor 23 are equal, the voltage Vr j g between the source 23s and drain 23d is equal to the threshold voltage V ⁇ H between the unsaturated and saturated regions.
  • FIG. 8 is a circuit diagram showing the states of the electric currents and voltages in the non-selection period T ⁇ jgE °f the ith row.
  • the selection scan driver 5 applies the OFF voltage VQFF to the selection scan line Xj_
  • the voltage supply driver 6 applies the driving current reference voltage V ⁇ Q ⁇ to the voltage supply line Z j _.
  • the first transistors 21 of the pixel circuits Dj_ ]_ to D j _ n are OFF.
  • the first transistors 21 of the pixel circuits Dj_ 1 to Dj_ n shut off the tone designating current IoATA flowing through the current lines Y]_ to Y n , thereby preventing an electric current from flowing from the voltage supply line Zj_ to the current lines Y]_ to Y n via the driving transistors 23.
  • the second transistor 22 of each of the pixel circuits Dj_ to Dj_ n in the ith row is turned off, the second transistor 22 confines the electric charges in the capacitor 24. In this manner, the second transistor 22 holds the level of the converted voltage between the gate 23g and source 23s of the driving transistor 23, thereby storing the current value of the electric current which flows through the source-to-drain path of the driving transistor 23.
  • the high-level driving current reference voltage VHIGH by which the source-to-drain voltage Vr j g of the driving transistor 23 maintains the saturated region is applied to the voltage supply line Zj_, and the driving transistor
  • each driving transistor 23 of each of the pixel circuits Dj_ 1 to Dj_ n is ON. Accordingly, each driving transistor 23 supplies the driving current from the voltage supply line Zj_ to a corresponding one of the organic EL elements Ej_ l to Ej_ n to allow it to emit light at luminance corresponding to the current value of the driving current.
  • the level of the converted voltage between the gate 23g and source 23s of the driving transistor 23 of each of the pixel circuits D j _ l to Dj_ n is held by the capacitor 24 so as to be equal to the level of the voltage when the tone designating current IQATA flows through a corresponding one of the current lines Y to Y n in the second half of the selection period TgE- As shown in FIG.
  • a divided voltage VE of each of the organic EL elements E-j_ l to Ej_ n in the non-selection period T ⁇ gE is obtained by subtracting, from the driving current reference voltage VJ ⁇ JQH, the voltage Vpg on the EL load border line indicated by the alternate long and short dashed line, which is obtained when a driving current (equivalent to Irjg shown in FIG. 5) having a current value equal to that of the tone designating current IoATA flows. That is, the voltage difference on the right side of the EL load border line is the divided voltage of one organic EL element. As described above, the divided voltage V of the organic EL elements Ej_ to Ej_ n rises as the luminance tone rises.
  • the driving current reference voltage V ⁇ Q ⁇ is set higher than a voltage obtained by adding the divided voltage VEL when the luminance tone of the organic EL elements Ej_ ]_ to E_ n is a minimum to the ON resistance Vpg between the drain 23d and source 23s of the driving transistor at that time, and higher than a voltage obtained by adding the divided voltage VEL when the luminance tone of the organic EL elements Ej_ ]_ to E j _ n is a maximum to the ON resistance V ⁇ between the drain 23d and source 23s of the driving transistor at that time.
  • the voltage of the source 23s of the driving transistor 23 rises as the voltage V G g between the gate 23g and source 23s, which is held in the selection period T E rises.
  • the capacitor 24 changes the electric charge in the electrode 24B connected to the source 23s accordingly, the voltage V G g between the gate 23g and source 23s is held constant by equally changing the electric charge in the electrode 24A. As shown in FIG.
  • the luminance (the unit is nit.) of the organic EL elements Ej_ l to Ej_ n is uniquely determined by the current value of the tone designating current Io TA which flows through the pixel circuits Dj_ l to Dj_ n in the selection period TgE-
  • a method of driving the organic EL display panel 2 by the current source driver 3, selection scan driver 5, voltage supply driver 6, and switches S ⁇ to S n , and the display operation of the organic EL display 1 will be described below. As shown in FIG.
  • the selection scan driver 5 applies the ON voltage V Q N in order from the selection scan line X]_ in the first row to the selection scan line X m in the mth row (the selection scan line X m in the mth row is followed by the selection scan line X ⁇ in the first row) , thereby selecting these selection scan lines.
  • the voltage supply driver 6 applies the tone designating current reference voltage VLOW i n order from the voltage supply line in the first row to the voltage supply line Z m in the mth row (the voltage supply line Z m in the mth row is followed by the voltage supply line Z in the first row) , thereby selecting these voltage supply lines.
  • the current source driver 3 controls the current terminals CT ⁇ to CT n to generate the tone designating current IQATA having a current value corresponding to the image signal. Also, at the start of the selection period TgE of each row (at the end of the selection period TgE of the preceding row) , the switching signal ⁇ changes from low level to high level, the switching signal inv. ⁇ changes from high level to low level, and the reset voltage VR which removes the electric charges stored in the current lines Y_ to Y n and the electric charges stored in the pixel electrodes 51 via the first transistors 21 is applied.
  • the switching signal ⁇ changes from high level to low level
  • the switching signal inv. ⁇ changes from low level to high level.
  • the switches S]_ to S n allow the tone designating current IQATA to flow between the current terminals CT]_ to CT n and current lines Y_ to Y n , and shut down the application of the reset voltage VR to the current lines Y ⁇ to Y n .
  • the switches S ⁇ to S n shut off the flow of the electric current between the current terminals CT ] _ to CT n and current lines Y]_ to Y n , and allow the application of the reset voltage VR to the current lines Y ] _ to Y n .
  • the current value of the tone designating current IDAT A decreases as the luminance tone lowers.
  • the voltages of the current lines Y]_ to Y n and pixel electrodes 51 approximate to the tone designating current reference voltage VLOW' i.e., to the reset voltage VR.
  • the tone designating current " [D A T A having a large current value flows in the selection period TgE of the preceding row or of the preceding frame period Tg ⁇ , the voltage of the pixel electrodes 51 become much lower than the reset voltage VR via the current lines Yi to Y n and first transistors 21.
  • the amount of electric charges to be modulated is large because the electric charges of the current lines Y ⁇ to Y n , which are stored in accordance with the tone designating current IQATA having a large current value in the selection period T E of the (i - l)th row are held in the parasitic capacitances of the current lines Y ⁇ to Y n .
  • FIG. 9 is a timing chart showing, from above, the voltage of the selection scan line X_, the voltage of the voltage supply line Z]_, the switching signal inv. ⁇ , the switching signal ⁇ , the current value of the current terminal CTj, the current value of an electric current which flows through the driving transistor 23 of the pixel circuit Dj .
  • the abscissa represents the common time.
  • the selection scan driver 5 applies the ON voltage V Q N to the selection scan line Xj_ in the ith row (i.e., in the selection period TgE of the ith row) , the OFF voltage VQ F i s applied to the other selection scan lines X]_ to X m (except for X-j_) .
  • the first and second transistors 21 and 22 of the pixel circuits Dj_ l to D-j_ n in the ith row are ON, and the first and second transistors 21 and 22 of the pixel circuits ⁇ > ⁇ to D m n (except for Dj_ ]_ to Dj_ n ) in the other rows are OFF.
  • the tone designating current reference voltage V O is applied to the voltage supply line Zj_, and the second transistors 22 of the pixel circuits Dj_ l to Dj_ n in the ith row are ON.
  • the voltage is also applied to the gates 23g of the driving transistors 23 of the pixel circuits D_ ⁇ to Dj_ n. in the ith row, so the driving transistors 23 are turned on.
  • the transistors 32 of the switches S ⁇ to S n are turned on. Therefore, the voltage supply line Zj_ is electrically connected to the reset input terminal 41 via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ to Dj_ n and the current lines Y to Y n . In this state, the voltage applied from the voltage supply line Zj_ to the reset input terminal 41 via the driving transistors
  • the voltage of the pixel electrodes 51 of the organic EL elements Ej_ ] _ to Ej_ n is also equal to the reset voltage VR.
  • the reset voltage VR is applied to the current lines Y]_ to Y n , the electric charges stored in the parasitic capacitances of the current lines Y]_ to Y n and the electric charges stored in the parasitic capacitances of the pixel circuits Dj_ to Dj_ n including the pixel electrodes 51 are removed, so the voltage of these components becomes equal to the reset voltage VR.
  • the organic EL elements Ej_ l to E_ n stop emitting light immediately after the start of the reset period TR of the ith row. As shown in FIGS.
  • the ON voltage VQN is applied to the selection scan line Xj_ in the ith row, and the tone designating current reference voltage VLOW is applied to the voltage supply line Zj_ in the ith row. Therefore, the first transistors 21, second transistors 22, and driving transistors 23 of the pixel circuits Dj_ ]_ to D- n in the ith row are ON.
  • the transistors 31 of the switches S to S n are turned on, so the switches S ⁇ to S n allow an electric current to flow between the current terminals CT]_ to CT n and current lines Y- ⁇ _ to Y n .
  • the current terminals CT_ to CT n are electrically connected to the voltage supply line Zj_ in the ith row.
  • the current source driver 3 supplies the tone designating current ] " DATA from the voltage supply line Zj_ to the current terminals CT ⁇ to CT n via the driving transistors 23 and first transistors 21 of the pixel circuits D ⁇ to D i n' the current lines Y to Y n , and the switches S ⁇ to S n .
  • the current source driver 3 controls the current value of the tone designating current IQATA supplied to the current lines Y to Y n such that the current value is held constant in accordance with the image signal.
  • the tone designating current IDAT flows along the voltage supply line Zj_ — > the path between the drain 23d and source 23s of the driving transistor 23 of each of the pixel circuits Dj_ ] _ to Dj_ n - the path between the drain 21d and source 21s of the first transistor 21 of each of the pixel circuits D-j_ ]_ to D i n ⁇ * the current lines Y_ to Y n —» the transistors 31 of the switches S]_ to S n — * ⁇ the current terminals CT ] _ to CT n of the current source driver 3.
  • the current value of the tone designating current IQATA which flows through the driving transistor 23 of each of the pixel circuits Dj_ 1 to Dj_ n in the ith row is converted into the level of the voltage between the gate 23g and source 23s of the driving transistor 23.
  • the reset voltage VR is applied to the current lines Y]_ to Y n .
  • the voltage applied from the voltage supply line Zj_ to the reset input terminal 41 via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ l to Dj_ n and the current lines Y]_ to Y n can be made steady. Accordingly, even if a weak tone designating current IDATA flows through the current lines Y ⁇ to Y n after the reset period TR of the ith row, electric charges corresponding to the tone designating current IQATA can ⁇ e rapidly held in the capacitors 24 of the pixel circuits Dj_ ⁇ to Dj_ n .
  • the current value of the electric current which flows between the drain 23d and source 23s of the driving transistor 23 of each of the pixel circuits Dj_ to Dj_ n in the ith row and the level of the voltage between the source 23s and gate 23g are overwritten from those of the preceding frame period Tg G .
  • the selection period T E of the ith row therefore, the magnitude of the electric charges which are held in the capacitor 24 of each of the pixel circuits Dj_ l to Dj_ n in the ith row is overwritten from that of the preceding frame period Tgr j .
  • the potential at arbitrary points in the paths from the driving transistors 23 of the pixel circuits Dj_ l to Dj_ n to the current lines Y]_ to Y n via the first transistors 21 changes in accordance with, e.g., the internal resistances of the transistors 21, 22, and 23, which change with time.
  • the current source driver 3 forcedly supplies the tone designating current IoATA rom the driving transistors 23 of the pixel circuits Dj_ to Dj_ n to the current lines Y to Y n via the first transistors 21. Therefore, even if the internal resistances of the transistors 21, 22, and 23 change with time, the tone designating current IQATA takes a desired current value.
  • the common electrode of the organic EL elements Ej_ to E j _ n in the ith row is at the reference voltage Vgg, and the voltage supply line Zj_ is at the tone designating current reference voltage VLOW which is equal to or lower than the reference voltage Vgg.
  • a reverse bias voltage is applied to the organic EL elements Ej_ to Ej_ n in the ith row. Accordingly, no electric current flows through the organic EL elements Ej_ to Ej_ n in the ith row, so the organic EL elements Ej_ to Ej_ n do not emit light Subsequently, as shown in FIGS.
  • a signal output from the selection scan driver 5 to the selection scan line X_ changes from the high-level ON voltage VQN to the low-level OFF voltage VQFF- That is, the selection scan driver 5 applies the OFF voltage VQFF to the gate 21g of the first transistor 21 and the gate 22g of the second transistor 22 of each of the pixel circuits Dj_ to Dj_ n in the ith row.
  • the first transistors 21 of the pixel circuits Dj_ l to Dj_ n in the ith row are turned off to prevent the electric current from flowing from the voltage supply line Z _ to the current lines Y]_ to Y n .
  • the second transistors 22 of the pixel circuits D_ l to Dj_ n in the ith row are turned off, the electric charges held in the capacitors 24 in the immediately preceding selection period Tg of the ith row are confined by the second transistors 22.
  • the driving transistor 23 of each of the pixel circuits D_ l to Dj_ n in the ith row is kept ON in the non-selection period T ⁇ gE- That is, in each of the pixel circuits D_ l to D_ n in the ith row, the voltage Vgg between the gate 23g and source 23s of the driving transistor 23 in the non-selection period T ⁇ E becomes equal to the voltage Vg between the gate 23g and source 23s of the driving transistor 23 in the immediately preceding selection period Tgg, i.e., the capacitor 24 in which the electric charges on the side of the electrode 24A are held by the second transistor 22 holds the voltage Vg between the gate 23g and source 23s of the driving transistor 23.
  • the voltage supply driver 6 applies the driving current reference voltage VJUGH to the voltage supply line Zj_ in the ith row.
  • the common electrode of the organic EL elements Ej_ l to Ej_ n in the ith row is at the reference voltage Vgg
  • the voltage supply line Zj_ in the ith row is at the driving current reference voltage VJ-IJGH which is higher than the reference voltage Vgg, so the driving transistors 23 of the pixel circuits Dj_ l to Dj_ n in the ith row are ON.
  • a forward bias voltage is applied to the organic EL elements Ej_ to Ej_ n .
  • a driving current flows from the voltage supply line Zj_ to the organic EL elements Ej_ l to Ej_ n via the driving transistors 23, and thus the organic EL elements Ej_ to Ej_ n emit light.
  • the first transistor 21 electrically shuts off the path between the current line Yj and driving transistor 23, and the second transistor 22 confines the electric charges in the capacitor 24.
  • the level of the voltage, which is converted in the selection period T E, between the gate 23g and source 23s of the driving transistor 23 is held, and a driving current having a current value corresponding to the level of this voltage held between the gate 23g and source 23s is supplied to the organic EL element Ej ⁇ by the driving transistor 23.
  • the current value of the driving current which flows through the organic EL elements Ej_ 1 to Ej_ n in the selection period TgE of the ith row is equal to the current value of the electric current which flows through the driving transistors 23 of the pixel circuits Dj_ ] _ to Dj_ n , and therefore equal to the current value of the tone designating current I Q ⁇ TA which flows through the driving transistors 23 of the pixel circuits D_ to D_ n in the selection period T E-
  • the current value of the tone designating current IDATA which flows through the driving transistors 23 of the pixel circuits D_ to Dj_ n is a desired current value.
  • a driving current having a desired current value can be supplied to the organic EL elements Ej_ ]_ to Ej_ n , so the organic EL elements Ej_ l to Ej_ n can emit light at a desired tone luminance.
  • the transistors 31 of the switches S ⁇ to S n are turned off, and the transistors 32 of the switches S ] _ to S n are turned on.
  • the tone designating current I TA does not flow through any of the current lines Y ] _ to Y n , but the reset voltage VR is applied to all the current lines Y- ] _ to Y n , the pixel electrodes 51 in the (i + l)th row, the electrodes 24B of the capacitors 24 in the (I + l)th row, and the sources 23s of the driving transistors 23 in the (i + l)th row.
  • the selection scan driver 5 selects the selection scan line X + ⁇ in the (i + l)th row, so the tone designating current IQATA flows from the voltage supply line Z to the current terminals CT ] _ to CT n via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ _ to D j _ n , the current lines Y]_ to Y n , and the switches Dj_ - ⁇ to D i/n .
  • the reset voltage VR is forcedly applied to, e.g., the current lines Y to Y n and the pixel electrodes 51. Therefore, the charge amount of the parasitic capaci- tances of the current lines Y to Y n and the like approximates to the charge amount in a steady state in which a small electric current flows. Accordingly, even when the electric current which flows through the current lines Y to Y n after the reset period TR of the (i + l)th row is weak, a steady state can be immediately obtained.
  • the current value of the driving current which flows through the organic EL elements E to E m n in the non-selection period T ⁇ gE is represented by the current value of the tone designating current IQATA after the reset period TR of the selection period TgE- Therefore, even when variations are produced in characteristics of the driving transistors 23 of the pixel circuits D ⁇ to D m n , no variations are produced in luminance of the organic EL elements E ⁇ to E m n if the current value of the tone designating current IQATA r g ins the same for all the pixel circuits O to D m n .
  • this embodiment can suppress planar variations by which pixels have different luminance values even though luminance tone signals having the same level are output to these pixels. Accordingly, the organic EL display 1 of this embodiment can display high-quality images.
  • the tone designating current IQATA i er y weak because it is equal to the current value of the electric current which flows through the organic EL elements E_ to E m n in accordance with the luminance of the organic EL elements E]_ to E m n which emit light.
  • the wiring capacitances of the current lines Y]_ to Y n delay the tone designating current IQATA which flows through the current lines Y]_ to Y n . If the selection period TgE is short, therefore, electric charges corresponding to the tone designating current . " DATA cannot be held in the gate-to-source path of the driving transistor 23. In this embodiment, however, the reset voltage VR is forcedly applied to the current lines Y- ⁇ _ to Y n in the reset period TR of each row.
  • the data driving circuit 7 applies the reset voltage VR to the current lines Y ] _ to Y n in the selection period Tg - Therefore, the first transistor 21 has both the function of a switching element which loads the reset voltage VR into each of the pixel circuits D]_ to D m n , and the function of a switching element which loads the tone designating current IQATA into each of the pixel circuits D]_ to D m n .
  • FIG. 10 is a block diagram showing an organic EL display 101 according to the second embodiment to which the organic EL display of the present invention is applied.
  • the same reference numerals and symbols as in the organic EL display 1 of the first embodiment denote the same parts in the organic EL display 101, and an explanation thereof will be omitted.
  • the organic EL display 101 includes an organic EL display panel 2, scan driving circuit 9, and data driving circuit 107.
  • the organic EL display panel 2 and scan driving circuit 9 are the same as the organic EL display panel 2 and scan driving circuit 9 of the first embodiment.
  • the data driving circuit 107 is different from the data driving circuit 7 of the first embodiment .
  • the data driving circuit 107 includes n current terminals DT ] _ to DT n , a current control driver 103 which supplies a pull current ILI to the current terminals DT ] _ to DT n , first current mirror circuits M]_]_ to M n] _ and second current mirror circuits M ⁇ 2 to M n 2 which convert the pull current ILI flowing through the current terminals DT]_ to DT n into a tone designating current IQATA' and switches T]_ to T n interposed between current lines Y_ to Y n , the first current mirror circuits ] _ ⁇ to M n ]_, and the second current mirror circuits M]_2 to M n 2.
  • An 8-bit digital tone image signal is input to the current control driver 103.
  • This digital tone image signal loaded into the current control driver 103 is converted into an analog signal by an internal D/A converter of the current control driver 103.
  • the driver 103 generates the pull current ILI having a current value corresponding to the analog image signal at the current terminals DT_ to DT n .
  • the driver 103 supplies the pull current ILI fr m the first current mirror circuits ]__ to M n _ formed for individual rows to the current terminals DT]_ to DT n .
  • the current control driver 103 supplies the tone designating current IQATA from driving transistors 23 in the individual rows to the second current mirror circuits M]_2 to n 2 via the current lines Y]_ to Y n .
  • the operation timings of the current control driver 103 are the same as those of the current source driver 3 of the first embodiment.
  • the current control driver 103 controls the current value of the pull current ILI at the current terminals DT]_ to DT n in each selection period T E of each row in accordance with the image signal, and makes the current value of the pull current ILI steady in a period from the end of each reset period TR to the end of the corresponding selection period T E-
  • the pull current ILI supplied by the current control driver 103 is larger than and proportional to the tone designating current IDATA supplied by the current source driver 3 of the first embodiment.
  • the first current mirror circuits M]_]_ to M n ]_ and second current mirror circuits M]_2 to n 2 convert the pull current ILI which flows through the current terminals DT]_ to DT n into the tone designating current iD A T A at a predetermined conversion ratio.
  • Each of the first current mirror circuits M ⁇ to M n ⁇ is made up of two P-channel MOS transistors 61 and 62.
  • the transistors 61 and 62 can be fabricated by the same steps as the transistors 21 to 23 of each of pixel circuits D]_ ]_ to D m n .
  • Each of the second current mirror circuits M ⁇ 2 to M n 2 is made up of two N-channel MOS transistors 63 and 64.
  • the transistors 63 and 64 can be partially fabricated by the same steps as the transistors 21 to 23 of each of the pixel circuits D ⁇ _ to D m , n .
  • the gates and drains of the transistors 61 and the gates of the transistors 62 are connected to the current terminals DT]_ to DT n .
  • the sources of the transistors 61 and 62 are connected to a reset input terminal 41 which outputs a reset voltage VR as a ground voltage.
  • the gates and drains of the transistors 63 and the gates of the transistors 64 are connected together to the drains of the transistors 62.
  • the sources of the transistors 63 and 64 are connected to a constant-voltage input terminal 45 to which a negative voltage is applied, and the drains of the transistors 64 are connected to the sources of transistors 34 of the switches T]_ to T n (to be described later) .
  • the channel resistance of the transistor 61 is lower than that of the transistor 62.
  • the channel resistance of the transistor 63 is lower than that of the transistor 64.
  • Each of the switches T]_ to T n has an N-channel MOS transistor 33 and the N-channel MOS transistor 34.
  • the transistors 33 and 34 can be fabricated by the same steps as the transistors 21 to 23 of each of the pixel circuits D_ to D m ⁇ n .
  • An example of the switch Tj will be explained below.
  • the gate of the transistor 34 of the switch Tj is connected to a switching signal input terminal 43, and thus a switching signal inv. ⁇ is input to the gate of the transistor 34.
  • the gate of the transistor 33 is connected to a switching signal input terminal 42, and thus a switching signal ⁇ is input to the gate of the transistor 33.
  • the drains of the transistors 33 and 34 are connected to the current line Yj , the source of the transistor 33 is connected to the source of the transistor 61 of the first current mirror circuit M- and the reset input terminal 41, and the source of the transistor 34 is connected to the drain of the transistor 64 of the second current mirror circuit j_2 •
  • the switching signal ⁇ is at high level and the switching signal inv. ⁇ is at low level, the transistor 33 is turned on, and the transistor 34 is turned off.
  • the switching signals ⁇ and inv. ⁇ have the same waveforms as in FIG. 4 of the first embodiment.
  • the switches T]_ to T n switch the state in which the tone designating current IDATA obtained by modulating the current value of the pull current ILI by the first current mirror circuits Mii to M n ⁇ and second current mirror circuits M12 to M n 2 is supplied to the driving transistors 23 and current lines Yi to Y n , and the state in which the reset voltage VR is applied to the current lines Yi to Y n .
  • an electric current which flows through the drain-to-source path of the transistor 62 in the first current mirror circuit Mj 1 has a value obtained by multiplying the ratio of the channel resistance of the transistor 62 to that of the transistor 61 by the current value of the pull current ILI R the drain-to-source path of the transistor 61.
  • an electric current which flows through the drain-to-source path of the transistor 64 has a value obtained by multiplying the ratio of the channel resistance of the transistor 64 to that of the transistor 63 by the current value of an electric current in the drain-to-source path of the transistor 63.
  • the current value of the electric current in the drain-to-source path of the transistor 63 matches the electric current which flows through the drain-to-source path of the transistor 62. Therefore, the current value of the tone designating current iDATA i obtained by multiplying the ratio of the channel resistance of the transistor 64 to that of the transistor 63 by the value which is obtained by multiplying the ratio of the channel resistance of the transistor 62 to that of the transistor 61 by the current value of the pull current ILI i n the drain-to-source path of the transistor 61.
  • the first current mirror circuits Mn to M n ⁇ and second current mirror circuits M12 to n 2 convert the pull current ILI which flows through the current terminals DTi to DT n into the tone designating current IDATA * Since the tone designating current IoATA flows through the output sides of the second current mirror circuits M 2 to M n 2, i.e., the drains of the transistors 64, these drains of the transistors 64 of the second current mirror circuits M12 to M n 2 are equivalent to the current terminal CTj of the current source driver 3 of the first embodiment.
  • the reset voltage VR is at the same level as the tone designating current reference voltage VLOW- l n the second embodiment, however, the reset voltage VR is set at 0 [V] . Therefore, when a voltage Vgg is set at the ground voltage, no voltage difference is produced between pixel electrodes 51 as the anodes of the organic EL elements Ei l to E m n and the common electrode as the cathode. As a consequence, electric charges stored in the pixel electrodes 51 can be easily removed.
  • the switching signal ⁇ is input to the switching signal input terminal 42, and the switching signal inv. ⁇ is input to the switching signal input terminal 43.
  • the relationship between the timings of the switching signals ⁇ and inv. ⁇ and the selection timings of a selection scan driver 5 and voltage supply driver 6 is the same as in the first embodiment. Also, the operation timings of the selection scan driver 5 and voltage supply driver 6 in the second embodiment are the same as in the first embodiment.
  • the transistors 33 of the switches Ti to T n are turned on, so a voltage supply line Zj_ is electrically connected to the reset input terminal 41 via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ i to Di n and the current lines Yi to Y n .
  • the reset voltage VR is applied to the current lines Yi to Y n and pixel electrodes 51, so the electric charges stored in the parasitic capacitances of the current lines Yi to Y n and the electric charges stored in the parasitic capacitances of the pixel electrodes 51 can be rapidly removed.
  • the current value of a driving current which flows through the organic EL elements Ei to E m n is represented by the current value of the tone designating current IQATA after the reset period TR of each selection period T E- Therefore, even if variations are produced in characteristics of the driving transistors 23 of the pixel circuits Di i to D m n , no variations are produced in driving current because the tone designating current IDATA i s forcedly supplied to the driving transistors 23. As a consequence, no variations are produced in luminance of the organic EL elements E]_ ]_ to E m n .
  • the current value of the tone designating current I ⁇ A TA or" the current lines Y]_ to Y n is proportional to and smaller than the pull current
  • the tone designating current I T A °f the current lines Yl to Y n does not largely reduce. That is, even a decrease in output from the current control drive 103 caused by a current leak has no large influence on the tone designating current Io A T A °f the current lines Yi to Y n , so the luminance of the organic EL elements Ei i to E m n does not largely decrease.
  • the data driving circuit 107 can well generate the tone designating current IQATA even when the current control driver 103 cannot generate a weak electric current close to the tone designating current IDATA matching the light emission characteristics of the organic EL elements.
  • the data driving circuit 107 applies the reset voltage VR to the current lines Yi to Y n in the selection period Tgg in the second embodiment as well. Therefore, the first transistor 21 has both the function of a switching element which loads the reset voltage VR into each of the pixel circuits Di i to D m n , and the function of a switching element which loads the tone designating current IDATA into each of the pixel circuits Di i to D m n .
  • the number of transistors necessary for the pixel circuits Di l to D m n does not increase.
  • the organic EL elements Ei l to E m n are formed on the same surface as the pixel circuits Di i to D m n , therefore, the aperture ratio of the pixels Pi i to P m n does not decrease.
  • FIG. 11 is a block diagram showing an organic EL display 201 according to the third embodiment to which the organic EL display of the present invention is applied.
  • the same reference numerals and symbols as in the organic EL display 1 of the first embodiment denote the same parts in the organic EL display 201, and an explanation thereof will be omitted. Similar to the organic EL display 1, the organic
  • EL display 201 includes an organic EL display panel 2, scan driving circuit 9, and data driving circuit 207.
  • the organic EL display panel 2 and scan driving circuit 9 are the same as the organic EL display panel 2 and scan driving circuit 9 of the first embodiment.
  • the data driving circuit 207 is different from the data driving circuit 7 of the first embodiment.
  • the data driving circuit 207 includes a current control driver 203 which has n current terminals FT]_ to FT n and supplies a push current I 2 to the current terminals FTi to FT n , current mirror circuits i to M n for converting the push current IL2 flowing through the current terminals FTi to FT n , and switches Si to S n interposed between current lines Yi to Y n and the current mirror circuits Mi to M n .
  • the current control driver 103 supplies the pull current ILI from the current mirror circuits i to M n to the current terminals DTi to DT n .
  • the current control driver 203 supplies the push current IL2 from the current terminals FTi to FT n to the current mirror circuits i to M n .
  • Each of the current mirror circuits Mi to M n is made up of two N-channel MOS transistors 161 and 162.
  • the transistors 161 and 162 can be fabricated by the same steps as transistors 21 to 23 of pixel circuits O l f l to D m , n .
  • the gate and drain of the transistor 161 and the gate of the transistor 162 are connected together, and the sources of the transistors 161 and 162 are connected to a constant-voltage input terminal 45.
  • a constant voltage V QQ is applied to the constant-voltage input terminal 45.
  • the level of the constant voltage V QQ is lower than a tone designating current reference voltage VLO and reference voltage Vgg.
  • the constant voltage VQQ is a negative voltage.
  • An example of the switch S j will be explained below.
  • the switch S j is made up of ⁇ -channel field-effect transistors 31 and 32. The gate of the transistor 31 is connected to a switching signal input terminal 43, and thus a switching signal inv. ⁇ is input to the gate of the transistor 31.
  • the gate of the transistor 32 is connected to a switching signal input terminal 42, and thus a switching signal ⁇ is input to the gate of the transistor 32.
  • the drain of the transistor 31 is connected to the current line Yj , and the source of the transistor 31 is connected to the drain of the transistor 162.
  • the drain of the transistor 32 is connected to the current line Y j .
  • the source of the transistor 32 is connected to a reset input terminal 41, and thus a reset voltage VR as a constant voltage is applied to the source of the transistor 32.
  • the transistor 31 When the switching signal ⁇ is at low level and the switching signal inv. ⁇ is at high level, the transistor 31 is turned on, and the transistor 32 is turned off.
  • the transistors 31 and 32 can be fabricated by the same steps as the transistors 21 to 23 of the pixel circuits D]_ i to D m n .
  • the reset voltage VR is preferably 0 [V] in order to completely discharge, e.g., the electric charges stored in the parasitic capacitances of the current lines Y ] _ to Y n and the electric charges stored in the parasitic capacitances of pixel electrodes 51.
  • the current control driver 203 controls the current value of the push current IL2 at the current terminals FTj . to FT n in accordance with the image signal in each selection period TgE of each row, and holds the magnitude of the push current IL2 constant in a period from the end of each reset period TR to the end of the corresponding selection period gE-
  • the push current IL2 supplied by the current control driver 203 is larger than and proportional to the tone designating current IoATA supplied by the current source driver 3 of the first embodiment.
  • the channel resistance of the transistor 161 is lower than that of the transistor 162. Therefore, the current mirror circuits Mi to M n convert the push current IL2 which flows through the current terminals FTi to FT n into a tone designating current IoATA- Tne current value of the tone designating current IDATA i s substantially a value obtained by multiplying the ratio of the cannel resistance of the transistor 161 to that of the transistor 162 by the current value of the push current IL2 in the drain-to-source path of the transistor 161.
  • the tone designating current IDATA flows through the output sides of the current mirror circuits Mi to M n , i.e., the drains of the transistors 162, these drains of the transistors 162 of the current mirror circuits Mi to M n are equivalent to the current terminals CTi to CT n of the current source driver 3 of the first embodiment. That is, an arrangement obtained by combining the current mirror circuits Mi to M n and current control driver 203 is equivalent to the current source driver 3 of the first embodiment .
  • the relationship between the timings of the switching signals ⁇ and inv. ⁇ and the selection timings of the selection scan driver 5 and voltage supply driver 6 in this embodiment is the same as in the first embodiment.
  • the operation timings of the selection scan driver 5 and voltage supply driver 6 in the third embodiment are the same as in the first embodiment. Therefore, in the reset period TR of the ith row, the first transistors 21 of the pixel circuits D l,l to D m ⁇ n are ON in the third embodiment as well.
  • the voltages of the pixel electrodes 51 of organic EL elements Ei i to Ei n , drains 21d of the first transistors 21 in the ith row, electrodes 24B of capacitors 24 in the ith row, sources 23s of the driving transistors 23 in the ith row, and the current lines Y ] _ to Y n are set in a steady state, thereby removing the electric charges stored in these parasitic capacitances in the preceding selection period TgE- Consequently, the tone designating current IQATA can be rapidly and accurately written in the next selection period TgE-
  • the data driving circuit 207 applies the reset voltage VR to the current lines Yi to Y n in the selection period TgE in the third embodiment as well.
  • the first transistor 21 has both the function of a switching element which loads the reset voltage VR into each of the pixel circuits D ] _ to D m n , and the function of a switching element which loads the tone designating current IQATA into each of the pixel circuits Di i to D m n . Accordingly, the number of transistors necessary for the pixel circuits Di l to D m n does not increase. When the organic EL elements Ei to E m n are formed on the same surface as the pixel circuits Di i to D m n , therefore, the aperture ratio of the pixels Pi l to P m n does not decrease. [Fourth Embodiment] FIG.
  • FIG. 12 is a block diagram showing an organic EL display 301 according to the fourth embodiment to which the organic EL display of the present invention is applied.
  • the same reference numerals and symbols as in the organic EL display 1 of the first embodiment denote the same parts in the organic EL display 301, and an explanation thereof will be omitted. Similar to the organic EL display 1, the organic
  • the EL display 301 includes an organic EL display panel 2, scan driving circuit 9, and data driving circuit 307.
  • the organic EL display panel 2 and scan driving circuit 9 are the same as the organic EL display panel 2 and scan driving circuit 9 of the third embodiment.
  • the data driving circuit 307 is different from the data driving circuit 7 of the first embodiment.
  • the data driving circuit 307 includes a current control driver 303, current mirror circuits Mi to M n , switching elements Ki to K n , and switching elements Wi to W n as switches.
  • the current control driver 303 has n current terminals GTi to GT n .
  • An 8-bit digital tone image signal is input to the current control driver 303.
  • This digital tone image signal loaded into the current control driver 303 is converted into an analog signal by an internal D/A converter of the current control driver 303.
  • the current control driver 303 generates a push current IL3 having a current value corresponding to the analog image signal at the current terminals GTi to GT n .
  • the current control driver 303 controls the current value of the push current IL3 at the current terminals GTi to GT n in each selection period T E of each row in accordance with the image signal, and holds the current value of the push current IL3 constant in a period from the end of each reset period TR to the end of the corresponding selection period Tg -
  • the push current IL3 supplied by the current control driver 303 is larger than the tone designating current IoAT A supplied by the current source driver 3 of the first embodiment, and proportional to a tone designating current IQATA which flows through a transistor 362 (to be described later) .
  • the current mirror circuits Mi to Mi convert the push current IL3 which flows through the current terminals GTi to GT n into the tone designating current IDATA-
  • Each of the current mirror circuits Mi to M n has two transistors 361 and 362.
  • the gate of the transistor 361 is connected to the gate of the transistor 362, and the drain of the transistor 361 is connected to the current terminal and to the gates of the transistors 361 and 362.
  • the drain of the transistor 362 is connected to a current line Y j .
  • the sources of the transistors 361 and 362 are connected to a common voltage terminal 344. A constant voltage V QQ is applied to the voltage terminal 344.
  • the level of the constant voltage VQQ is lower than a tone designating current reference voltage VLOW and reference voltage Vgg.
  • the constant voltage V Q O is a negative voltage.
  • the current value of the tone designating current IDATA is substantially a value obtained by multiplying the ratio of the cannel resistance of the transistor 362 to that of the transistor 361 by the current value of the push current IL3 in the drain-to-source path of the transistor 361. That is, an arrangement obtained by combining the current mirror circuits Mi to M n and current control driver 303 is equivalent to the current source driver.
  • the drains of the transistors or switching elements W ] _ to W n are connected to the current terminals GT_ to GT n and to the drains and gates of the transistors 361 of the current mirror circuits Mi to M n .
  • the sources of the switching elements W]_ to W n are connected to the voltage terminal 344.
  • the gates of the switching elements W ] _ to W n are connected to a switching signal input terminal 42.
  • the switching elements Wi to W n switch the application of the constant voltage V QQ to the drains of the transistors 361 of the current mirror circuits Mi to M n . Note that the switching elements Wi to W n may also be incorporated into the current control driver 303.
  • the driver 5 and voltage supply driver 6 in this embodiment is the same as in the first embodiment.
  • the transistors i to W n are turned on, so the voltages of the sources and drains of the transistors 361 become equal to each other. Accordingly, after the reset period TR of the selection period TgE, the influence of the parasitic capacitances of the current mirror circuits Mi to M n on the current lines Yi to Y n can be removed.
  • each of switching elements Ki to K n one of the drain and source is connected to a reset input terminal 41, the other of the drain and source is connected to a corresponding one of the current lines Yi to Y n , and the gate is connected to the switching signal input terminal 42.
  • the switching elements Ki to K n switch the application of the reset voltage VR to the current lines Yi to Y n .
  • the reset voltage VR is set at 0 [V] .
  • the other of the drain and source of a corresponding one of the switching elements Ki to K n may also be connected to a corresponding one of the current lines Yi to Y n , and the switching elements Ki to K n may also be formed on the organic EL display panel 2.
  • the switching elements Ki to K n are turned on, so pixel electrodes 51 and the current lines Yi to Y n electrically conduct to the reset input terminal 41 to apply the grounded reset voltage VR.
  • the tone designating current I Q ATA having a very small current value can be accurately and rapidly supplied.
  • the switching elements Ki to K n and Wi to W n are turned off, and an electric current having a current value corresponding to the tone flows through the current terminals GTi to GT n of the current control driver 303. Consequently, the tone designating current ID TA modulated by the current mirror circuits Mi to M n flow through the current lines Yi to Y n and driving transistor 23.
  • the data driving circuit 307 applies the reset voltage VR to the current lines Yi to Y n in the selection period TgE in the fourth embodiment as well.
  • a first transistor 21 has both the function of a switching element which loads the reset voltage VR into each of the pixel circuits Di i to D m n , and the function of a switching element which loads the tone designating current IpATA into each of the pixel circuits Di i to D m n . Accordingly, the number of transistors necessary for the pixel circuits Di i to D m n does not increase. When organic EL elements Ei i to E m n are formed on the same surface as the pixel circuits Di i to D m n , therefore, the aperture ratio of the pixels Pi l to P m n does not decrease.
  • an organic EL element is used as a light-emitting element in each of the above embodiments.
  • another light-emitting element having rectification characteristics may also be used. That is, it is also possible to use a light-emitting element in which no electric current flows if a reverse bias voltage is applied and an electric current flows if a forward bias voltage is applied, and which emits light at luminance corresponding to the current value of the flowing electric current.
  • An example of the light-emitting element having rectification characteristics is an LED (Light-Emitting Diode) .
  • the tone designating current reference voltage VLOW of the voltage supply driver 6 may also be positioned on the right side of the EL load border line corresponding to the maximum luminance tone shown in FIG. 4, provided that a portion or the whole of the tone designating current IoATA does not flow through the organic EL elements in the selection period Tgg.

Abstract

A display device includes a plurality of selection scan lines, a plurality of current lines, a selection scan driver which sequentially selects the plurality of selection scan lines in each selection period, a data driving circuit which applies a reset voltage to the plurality of current lines in the selection period and supplies a designating current having a current value corresponding to an image signal to the plurality of current lines after applying the reset voltage, and a plurality of pixel circuits which are connected to the plurality of selection scan lines and the plurality of current lines, and supply a driving current having a current value corresponding to the current value of the designating current which flows through the plurality of current lines.

Description

D E S C R I P T I O N
DISPLAY DEVICE, DATA DRIVING CIRCUIT, AND DISPLAY PANEL DRIVING METHOD
Technical Field The present invention relates to a display panel driving method of driving a display panel including a light-emitting element for each pixel, a data driving circuit for driving the display panel, and a display device including the display panel, the data driving circuit, and a selection scan driver. Background Art Generally, liquid crystal displays are classified into active matrix driving type liquid crystal displays and simple matrix driving type liquid crystal displays. The active matrix driving type liquid crystal displays display images having contrast and resolution higher than those displayed by the simple matrix driving type liquid crystal displays. In the active matrix driving type liquid crystal display, a liquid crystal element which also functions as a capacitor, and a transistor which functions as a pixel switching element are formed for each pixel. In the active matrix driving system, when a voltage at a level representing luminance is applied to a current line by a data driver while a scan line is selected by a scan driver serving as a shift register, this voltage is applied to the liquid crystal element via the transistor. Even when the transistor is turned off in a period after the selection of the scan line is complete and before the scan line is selected again, the liquid crystal element functions as a capacitor, so the voltage level is held in this period. As described above, the light transmittance of the liquid crystal element is refreshed while the scan line is selected, and light from a backlight is transmitted through the liquid crystal element having the refreshed light transmittance. In this manner, the liquid crystal display expresses a tone. Displays using organic EL (ElecctroLuminescent ) elements as self-light-emitting elements require no such a backlight as used in the liquid crystal displays, and hence are optimum for flat display devices. In addition, the viewing angle is not limited unlike in the liquid crystal display. Therefore, these organic EL displays are increasingly expected to be put into practical use as next-generation display devices. From the viewpoints of high luminance, high contrast, and high resolution, active matrix driving type organic EL displays are developed similarly to the liquid crystal displays. For example, in the conventional active matrix driving type organic EL display described in Jpn. Pat. Appln. KOKAI Publication No. 2000-221942, a pixel circuit (referred to as an organic EL element driving circuit in patent reference 1) is formed for each pixel. This pixel circuit includes an organic EL element, driving TFT, first switching element, switching TFT, and the like. When a control line is selected, a current source driver applies a voltage as luminance data to the gate of the driving TFT. Consequently, the driving TFT is turned on, and a driving current having a current value corresponding to the level of the gate voltage flows from a power supply line to the driving TFT via the organic EL element, so the organic EL element emits light at luminance corresponding to the current value of the electric current. When the selection of the control line is complete, the gate voltage of the driving TFT is held by the first switching element, so the emission of the organic EL element is also held. When a blanking signal is input to the gate of the switching TFT after that, the gate voltage of the driving TFT decreases to turn it off, and the organic EL element is also turned off to complete one frame period. Generally, the channel resistance of a transistor changes in accordance with a change in ambient temperature, or changes when the transistor is used for a long time. As a consequence, the gate threshold voltage changes with time, or differs from one transistor to another. Therefore, in the conventional voltage-controlled, active matrix driving type organic EL display in which the luminance and tone are controlled by the signal voltage, it is difficult to uniquely designate the current value of an electric current which flows through the organic EL element by the level of the gate voltage of the driving TFT, even if the current value of the electric current which flows through the organic EL element is changed by changing the level of the gate voltage of the driving TFT by using the signal voltage from the current line. That is, even when the gate voltage having the same level is applied to the driving TFTs of a plurality of pixels, the luminance of the organic EL element changes from one pixel to another. This produces variations in luminance on the display screen. Also, since the driving TFT deteriorates with time, the same gate voltage as the initial gate voltage cannot generate a driving current having the same current value as the initial current value. This also varies the luminance of the organic EL elements. Disclosure of Invention It is, therefore, an object of the present invention to provide a display device, data driving circuit, and display panel driving method capable of displaying high-quality images. A display device according to an aspect of the present invention comprises, a plurality of selection scan lines; a plurality of current lines; a selection scan driver which sequentially selects the plurality of selection scan lines in each selection period; a data driving circuit which applies a reset voltage to the plurality of current lines in a first part of the selection period, and supplies a designating current having a current value corresponding to an image signal to the plurality of current lines in a second part of the selection period after applying the reset voltage in the selection period; and a plurality of pixel circuits which are connected to the plurality of selection scan lines and the plurality of current lines, and supply a driving current having a current value corresponding to the current value of the designating current which flows through the plurality of current lines. A display device according to another aspect of the present invention comprises, a plurality of selection scan lines; a plurality of current lines; a plurality of light-emitting elements which are arranged at intersections of the plurality of selection scan lines and the plurality of current lines, and emit light at luminance corresponding to a current value of a driving current; a selection scan driver which sequentially select the plurality of selection scan lines in each selection period; a data driving circuit which applies a reset voltage to the plurality of current lines in a first part of the selection period, and supplies a designating current having a current value corresponding to an image signal to the plurality of current lines in a second part of the selection period after applying the reset voltage in the selection period; and a plurality of pixel circuits which are connected to the plurality of selection scan lines and the plurality of current lines, and electrically connect the plurality of current lines and the plurality of light-emitting elements to each other in the selection period. A data driving circuit according to still another aspect of the present invention comprises, a plurality of light-emitting elements connected to a plurality of selection scan lines and a plurality of current lines, a selection scan driver which sequentially selects the plurality of selection scan lines in each selection period, and a plurality of pixel circuits connected to the plurality of light-emitting elements, wherein a reset voltage is applied to the plurality of current lines in a first part of the selection period, and a designating current having a current value corresponding to an image signal is supplied to the plurality of current lines in a second part of the selection period after the first part of the selection period. A display panel driving method according to still another aspect of the present invention comprises, a selection step of sequentially selecting a plurality of selection scan lines of a display panel comprising a plurality of pixel circuits connected to the plurality of selection scan lines and a plurality of current lines, and a plurality of light-emitting elements which are arranged at intersections of the plurality of selection scan lines and the plurality of current lines, each of the light-emitting elements emits light at luminance corresponding to a current value of a current flowing the current line; and a reset step of applying a reset voltage to the plurality of current lines in an initial part of a period in which each of the plurality of selection scan lines is selected. In the present invention, it is possible not only to discharge the parasitic capacitance of a current line by applying a reset voltage in a selection period, but also to discharge the parasitic capacitance of a pixel circuit or the parasitic capacitance of a light-emitting element. Brief Description of Drawings FIG. 1 is a block diagram of an organic electroluminescent display 1 according to the first embodiment of the present invention; FIG. 2 is a plan view of a pixel Pj_,j of the organic electroluminescent display 1; FIG. 3 is an equivalent circuit diagram of four adjacent pixels Pj.,j, pi+l,j' pi,j +l» and pi+l,j+l of the organic electroluminescent display 1; FIG. 4 is a timing chart showing the levels of signals in the organic electroluminescent display 1; FIG. 5 is a graph showing the current-voltage characteristics of an N-channel field-effect transistor; FIG. 6 shows an equivalent circuit diagram of two adjacent pixels Pj_,j and Pj^j+i in the ith row, and the states of electric currents and voltages in a reset period TR of the ith row; FIG. 7 shows the equivalent circuit diagram of the two adjacent pixels P_ j and Pj_ j+i in the ith row, and the states of electric currents and voltages after the reset period Tp> in a selection period Tgg °f the ith row; FIG. 8 shows the equivalent circuit diagrams of the two adjacent pixels pi,j and Pj. j+i in the ith row, and the states of electric currents and voltages in a non-selection period TjqgE of the ith row; FIG. 9 is a timing chart showing the levels of electric currents and voltages pertaining to the pixel Pi,j; FIG. 10 is a block diagram of an organic electroluminescent display according to the second embodiment of the present invention; FIG. 11 is a block diagram of an organic electroluminescent display according to the third embodiment of the present invention; and FIG. 12 is a block diagram of an organic electroluminescent display according to the fourth embodiment of the present invention. Best Mode for Carrying Out the Invention Best modes for carrying out the invention will be described below with reference to the accompanying drawings. Various technically preferred limitations are imposed on the following embodiments in order to carry out the present invention. However, the scope of the invention is not limited to the embodiments and examples shown in the drawing. [First Embodiment] FIG. 1 is a block diagram showing an organic electroluminescent display 1 according to the first embodiment to which the organic electroluminescent display of the present invention is applied. As shown in FIG. 1, the organic electroluminescent display 1 includes, as its basic configuration, an organic electroluminescent display panel 2 having m selection scan lines X]_ to Xm, m voltage supply lines Z]_ to Zm, n current lines Y to Yn, and pixels P]_ to Pm n. The display 1 further includes, a scan driving circuit 9 for linearly scanning the organic electroluminescent display panel 2 in the longitudinal direction, and a data driving circuit 7 for supplying a tone designating current IoATA to the current lines Y to Yn in cooperation with the scan driving circuit 9. Here, each of m and n is a natural number of 2 or more. The can driving circuit 9 has a selection scan driver 5 for sequentially selecting the selection scan lines X]_ to Xm, and a voltage supply driver 6 for sequentially selecting the voltage supply lines Z to Zn in synchronism with the sequential selection of the selection scan lines X^ to Xm by the selection scan driver 5. The data driving circuit 7 has a current source driver 3. The driver 3 includes n current terminals CT]_ to CTn and allows the tone designating current IoATA to flow through the current terminals CT]_ to CTn, and switches S to Sn interposed between the current terminals CT]_ to CTn and current lines Yi to Yn. The organic electroluminescent display panel 2 has a structure in which a display unit 4 for practically displaying images is formed on a transparent substrate. The selection scan driver 5, voltage supply driver 6, current source driver 3, and switches S]_ to Sn are arranged around the display unit 4. Portions or the whole of the selection scan driver 5, the voltage supply driver 6, the current source driver 3, and at least one of the switches S]_ to Sn can be integrated with the organic electroluminescent display panel 2 as they are formed on the transparent substrate, or can be formed around the organic electroluminescent display panel 2 as they are formed into a chip different from the organic electroluminescent display panel 2. Note that the display unit 4 may also be formed on a flexible sheet such as a resin sheet, instead of the transparent substrate. In the display unit 4, the (m x n) pixels P_ to Pm n are formed in a matrix on the transparent substrate such that m pixels are arranged in the longitudinal direction, i.e., the column direction, and n pixels are arranged in the lateral direction, i.e., the row direction. A pixel which is an ith pixel (i.e., a pixel in the ith row) from above and a jth pixel (i.e., a pixel in the jth column) from left is a pixel pi,j» Note that i is a given natural number from 1 to m, and is a given natural number from 1 to n. Accordingly, in the display unit 4, the m selec- tion scan lines to Xm running in the row direction are formed parallel to each other on the transparent substrate. The m voltage supply lines Z to Zm running in the row direction are formed parallel to each other on the transparent substrate in one-to-one correspondence with the selection scan lines X]_ to Xm. The voltage supply line Zjς (1 ≤ k ≤ m - 1) is positioned between the selection scan lines Xj^ and Xκ+1/ and the selection scan line Xm is positioned between the voltage supply lines Zm_^ and Zm. Also, the n current lines Y to Yn running in the column direction are formed parallel to each other on the upper side of the transparent substrate. The selection scan lines to Xm, voltage supply lines to Zm, and current lines Y to Yn are insulated from each other as they are separated by insulating films or the like interposed between them. The n pixels Pj_ to Pi n arranged along the row direction are connected to the selection scan line Xj_ and voltage supply line Zj_ in the ith row. The m pixels Pi j to Pm j arranged along the column direction are connected to the current line Yj in the jth column. The pixel pi,j is positioned at the intersection of the selection scan line Xj_ and current line Yj . The selection scan lines Xl to Xm are connected to output terminals of the selection scan driver 5. The voltage supply lines to Zm are connected to output terminals of the voltage supply driver 6. The pixels P]_ l to Pm n will be explained below with reference to FIGS. 2 and 3. FIG. 2 is a plan view showing the pixel i,j- FIG. 3 is an equivalent circuit diagram showing, e.g., four adjacent pixels pi,j' pi+l,j> pi,j+l' and pi+l,j+l- FIG- 2 principally shows the electrodes in the pixel pi,j to allow better understanding. The pixel Pj_ j includes an organic electroluminescent element Ej_ j as a self-light-emitting element which emits light in accordance with the value of an electric current, and a pixel circuit D-j_ j which is formed around the organic electroluminescent element Ej_ j, and drives it. Note that the organic electroluminescent element will be referred to as an organic EL element hereinafter. The organic EL element Ej_ j has a stacked structure in which a pixel electrode 51, organic EL layer 52, and common electrode are stacked in this order on the transparent substrate. The pixel electrode 51 functions as an anode. The organic EL layer 52 functions as a light-emitting layer in a broad sense, i.e., transports holes and electrons injected by an electric field, recombines the transported holes and electrons, and emits light by excitons produced by the recombination. The common electrode functions as a cathode. Although the common electrode is formed to cover the entire pixel, the it is not shown in FIG. 2 so that the pixel electrode 51, organic EL layer 52, pixel circuit Dj_ and the like are readily seen. The pixel electrode 51 is patterned for each of the pixels P]_ l to Pm n in each of regions surrounded by the current lines Y]_ to Yn, selection scan lines X]_ to Xm, and voltage supply lines Z_ to Zm. The pixel electrode 51 is a transparent electrode.
That is, the pixel electrode 51 has both conductivity and transparency to visible light. Also, the pixel electrode 51 preferably has a relatively high work function, and efficiently injects holes into the organic EL layer 52. Examples of main components of the pixel electrode 51 are tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In2θ3), tin oxide (Snθ2), zinc oxide (ZnO), and cadmium-tin oxide (CTO) . The organic EL layer 52 is formed on each pixel electrode 51. The organic EL layer 52 is also patterned for each of the pixels ?ι ]_ to Pm n. The organic EL layer 52 contains a light-emitting material (phosphor) as an organic compound. This light-emitting material can be either a high- or low-molecular material. In particular, the organic EL layer 52 has a two-layered structure in which a hole transporting layer and a light-emitting layer in a narrow sense are stacked in this order on the pixel electrode 51. The hole transporting layer is made of a PEDOT
(polythiophene) as a conductive polymer, and PSS (polystyrene sulfonic acid) as a dopant. The light-emitting layer in a narrow sense is made of a polyfluorene-based, light-emitting material. Note that the organic EL layer 52 may also have a three-layered structure having a hole transporting layer, a light-emitting layer in a narrow sense, and an electron transporting layer stacked in this order on the pixel electrode 51, or a single-layered structure having only a light-emitting layer in a narrow sense, instead of the two-layered structure. An electron or hole injecting layer may also be interposed between appropriate layers in any of these layered structures, and some other stacked structure may also be used. The organic EL display panel 2 can display full-color images or multicolor images. The organic EL layer 52 of each of the pixels P]_ to Pm n is a light-emitting layer in a broad sense which has a function of emitting red, green, or blue light. That is, the organic EL layers 52 which emit red light, green light, and blue light are regularly arranged, and the display unit 4 displays images in a color tone obtained by properly synthesizing these colors. The organic EL layer 52 is desirably made of an organic compound which is neutral with respect of electrons. This allows balanced injection and transportation of holes and electrons in the organic EL layer 52. One or both of an electron transporting substance and hole transporting substance may also be properly mixed in the light-emitting layer in a narrow sense. It is also possible to cause a charge transporting layer which is an electron or hole transporting layer to function as a recombination region which recombines electrons and holes, and to emit light by mixing a phosphor in this charge transporting layer. The common electrode formed on the organic EL layers 52 is formed for all the pixels P]_ _ to Pm n. Note that instead of this common electrode formed for all the pixels P]_ to Pm n, it is also possible to use a plurality of divided electrodes, e.g., a plurality of stripe electrodes divided for individual columns, or a plurality of stripe electrodes divided for individual rows. Generally, the organic EL layers 52 which emit different colors are made of different materials, and the light emission characteristics with respect to the current density depend upon the material. To adjust the luminance balance between different emission colors, therefore, pixels which emit the same color can be connected together in order to set the value of an electric current for each emission color of the organic EL layer 52. That is, assuming that a first-emission-color pixel emits a predetermined luminance at a relatively low current density, and a second-emission-color pixel requires a high current density in order to emit the same luminance as the first-emission-color pixel, the emission color balance can be adjusted by supplying, to the second-emission-color pixel, a tone electric current which is larger than that of the first-emission-color pixel. The common electrode is electrically insulated from the selection scan lines X_ to Xm, current lines Yl to Yn, and voltage supply lines Z to Zm. The common electrode is made of a material having a low work function. For example, the common electrode is made of indium, magnesium, calcium, lithium, barium, a rare earth metal, or an alloy containing at least one of these elements. Also, the common electrode can have a stacked structure in which layers of the various materials described above are stacked, or a stacked structure in which a metal layer is deposited in addition to these layers of the various materials. Practical examples are a stacked structure including a low-work-function, high-purity barium layer formed in the interface in contact with the organic EL layer 52, and an aluminum layer which covers this barium layer, and a stacked structure having a lithium layer as a lower layer and an aluminum layer as an upper layer. When the pixel electrode 51 is a transparent electrode and light emitted from the organic EL layer 52 is output from the transparent substrate through the pixel electrode 51, the common electrode preferably has light-shielding properties with respect to the light emitted from the organic EL layer 52, and more preferably has a high reflectance to the light emitted from the organic EL layer 52. When a forward bias voltage (by which the voltage of the pixel electrode 51 becomes higher than that of the common electrode) is applied between the pixel electrode 51 and common electrode in the organic EL element Ej_ ^ having the stacked structure as described above, holes are injected into the organic EL layer 52 from the pixel electrode 51, and electrons are injected into the organic EL layer 52 from the common electrode. The organic EL layer 52 transports these holes and electrons, and recombines them to produce excitons. Since these excitons excite the organic EL layer 52, the organic EL layer 52 emits light. The luminance of the organic EL element Ej_ j depends on the current value of an electric current which flows through the organic EL element E_ j ; the larger the electric current which flows through the organic EL element Ej_ j , the higher the luminance of the organic EL element Ej_ j. That is, if deterioration of the organic EL element Ej_ j is not taken into consideration, the luminance of the organic EL element Ej_ j is uniquely determined when the current value of the electric current which flows through the organic EL element Ej_ j is determined. Each of the pixel circuits D]_ to Dm n includes three thin-film transistors (to be simply referred to as transistors hereinafter) 21, 22, and 23, and a capacitor 24. Each of the transistors 21, 22, and 23 is an
N-channel MOS field-effect transistor having a gate, drain, source, semiconductor layer 44, impurity-dosed semiconductor layer, and gate insulating film. Each transistor is particularly an a-Si transistor in which the semiconductor layer 44 (channel region) is made of amorphous silicon. However, each transistor may also be a p-Si transistor in which the semiconductor layer 44 is made of polysilicon. In either case, the transistors 21, 22, and 23 are N-channel field-effect transistors, and can have either an inverted stagger structure or a coplanar structure. Also, the transistors 21, 22, and 23 can be simultaneously formed in the same process. In this case, the compositions of the gates, drains, sources, semiconductor layers 44, impurity-dosed semiconductor layers, and gate insulating films of the transistors 21, 22, and 23 are the same, and the shapes, sizes, dimensions, channel widths, and channel lengths of the transistors 21, 22, and 23 are different from each other in accordance with the functions of the transistors 21, 22, and 23. Note that the transistors 21, 22, and 23 will be referred to as a first transistor 21, second transistor 22, and driving transistor 23, respectively, hereinafter. The capacitor 24 has a first electrode 24A connected to a gate 23g of the driving transistor 23, a second electrode 24B connected to a source 23s of the transistor 23, and a gate insulating film (dielectric film) interposed between these two electrodes. The capacitor 24 has a function of storing electric charges between the gate 23g and source 23s of the driving transistor 23. In the second transistor 22 of each of the pixel circuits Dj_ l to Dj_ n in the ith row, a gate 22g is connected to the selection scan line Xj_ in the ith row, and a drain 22d is connected to the voltage supply line Zj_ in the ith row. In the driving transistor 23 of each of the pixel circuits Dj_ 1 to Dj_ n in the ith row, a drain 23d is connected to the voltage supply line Zj_ in the ith row through a contact hole 26. In the first transistor 21 of each of the pixel circuits Dj_ to Dj_ n in the ith row, a gate 21g is connected to the selection scan line Xj_ in the ith row. In the first transistor 21 of each of the pixel circuits D_ to Dm j in the jth column, a source 21s is connected to the current line Yj in the jth column. In each of the pixels P^ to Pm n, a source 22s of the second transistor 22 is connected to the gate 23g of the driving transistor 23 through a contact hole 25, and to one electrode of the capacitor 24. The source 23s of the driving transistor 23 is connected to the other electrode of the capacitor 24, and to a drain 21d of the first transistor 21. The source 23s of the driving transistor 23, the other electrode of the capacitor 24, and the drain 21d of the first transistor 21 are connected to the pixel electrode 51. The voltage of the common electrode of the organic EL elements E]_ l to Em n is held at a predetermined reference voltage Vgg. In this embodiment, the reference voltage Vgs is set at 0 [V] by grounding the common electrode of the organic EL elements E_ t° Em,n# The pixel electrodes 51 are divided by patterning for individual pixels surrounded by regions surrounded by the current lines Y to Yn, selection scan lines X]_ to Xm, and voltage supply lines to Zm. In addition, the edges of each pixel electrode 51 are covered with an interlayer dielectric film made of silicon nitride or silicon oxide which covers the three transistors 21, 22, and 23 of each pixel circuit, and the upper surface of the center of the pixel electrode 51 is exposed through a contact hole 55 formed in this interlayer dielectric film. Note that the interlayer dielectric film can have a first layer made of silicon nitride or silicon oxide, and a second layer formed on the first layer by using an insulating film made of, e.g., polyimide. Between the selection scan line Xj_ and current line Yj , and between the voltage supply line Zj_ and current line Yj , a protective film 44A is formed by patterning the same film as the semiconductor layer 44 of each of the transistors 21 to 23, in addition to the gate insulating film. Note that in order to protect the surface, which serves as a channel, of the semiconductor layer 44 of each of the transistors 21, 22, and 23 from being roughened by an etchant used in patterning, a blocking insulating layer made of silicon nitride or the like may also be formed except for the two end portions of the semiconductor layer 44. In this case, a protective film may be formed by patterning the same film as the blocking insulating layer between the selection scan line Xj_ and current line Yj , and between the voltage supply line Zj_ and current line Yj . This protective film and the protective film 44A may also be overlapped. The selection scan driver 5, voltage supply driver
6, switches S]_ to Sn, and current source driver 3 will be described below with reference to FIG. 4. FIG. 4 is a timing chart showing, from above, the voltage of the selection scan line X]_, the voltage of the voltage supply line Z\ , the voltage of the selection scan line X2, the voltage of the voltage supply line Z2, the voltage of the selection scan line X3, the voltage of the voltage supply line Z3, the voltage of the selection scan line Xm, the voltage of the voltage supply line Zm, the level (voltage value) of a switching signal inv.Φ, the level of a switching signal Φ, the voltage of the current line Yj , the voltage of the pixel electrode 51 of the organic EL element E]_ j , the luminance of the organic EL element E]_ j, the voltage of the pixel electrode 51 of the organic EL element E2,j' and the luminance of the organic EL element E2,j- Referring to FIG. 4, the abscissa represents the common time. The selection scan driver 5 is a so-called shift register, and has an arrangement in which m flip-flop circuits and the like are connected in series. That is, the selection scan driver 5 sequentially selects the selection scan lines X]_ to Xm by sequentially outputting selection signals in order from the selection scan line X^ to the selection scan line Xm (the selection scan line Xm is followed by the selection scan line X^) , thereby sequentially selecting the first and second transistors 21 and 22 in these rows connected to the selection scan lines X^ to Xm. More specifically, as shown in FIG. 4, the selection scan driver 5 individually applies, to the selection scan lines to Xm, a high-level (ON-level) ON voltage VQN (much higher than the reference voltage Vgg) as a selection signal or a low-level OFF voltage vOFF (equal to or lower than the reference voltage Vgg) as a non-selection signal, thereby sequentially selecting the selection scan lines X^ to Xm. That is, when the selection scan driver 5 applies the ON voltage VQN to the selection scan line Xj_, the selection scan line Xj_ in the ith row is selected. A period in which the selection scan driver 5 applies the ON voltage VQN to the selection scan line Xj_ in the ith row and thereby selects the selection scan line X^ in the ith row is called a selection period Tgg of the ith row. Note that while applying the ON voltage VQN to the selection scan line Xj_, the selection scan driver 5 applies the OFF voltage VQFF to the other selection scan lines X]_ to Xm (except for the selection scan line Xj_) . Accordingly, the selection periods Tgj of the selection scan lines X]_ to Xm do not overlap each other. When the selection scan driver 5 applies the ON voltage VQN to the selection scan line Xj_ in the ith row, the first and second transistors 21 and 22 are turned on in each of the pixel circuits Dj_ ι to Dj_?n connected to the selection scan line Xj_ in the ith row. Since the first transistors 21 are turned on, an electric current which flows through the current lines Y]_ to Yn can flow through the pixel circuits Dj_ to Di,n. After the selection period Tgg in which the selection scan line X_ in the ith row is selected, the selection scan driver 5 applies the OFF voltage VQFF to the selection scan line X_ to cancel the selection of the selection scan line Xj_ . As a consequence, in each of the pixel circuits Dj_ l to Dj_ n connected to the selection scan line Xj_ in the ith row, the first and second transistors 21 and 22 are turned off. Since the first transistors 21 are turned off, the electric current which flows through the current lines Y]_ to Yn cannot flow through the pixel circuits Dj_ l to Dj_ n any longer. Note that a period in which the selection scan driver 5 applies the OFF voltage VQ F to the selection scan line X^ in the ith row and thereby keeps the selection scan line Xj_ in the ith row unselected is called a non-selection period T^gg of the ith row.
In this case, a period represented by TgE + TNSE = TSC' i.e., a period from the start time of the selection period Tgj of the selection scan line Xj_ in the ith row to the start time of the next selection period TgE °f the selection scan line Xj_ in the ith row, is one frame period of the ith row. The voltage supply driver 6 is a so-called shift register, and has an arrangement in which m flip-flop circuits are connected in series. That is, in synchronism with the selection scan driver 5, the voltage supply driver 6 sequentially selects the voltage supply lines Z \ to Zm by sequentially outputting selection signals in order from the voltage supply line Z to the voltage supply line Zm (the voltage supply line Zm is followed by the voltage supply line Z]_) , thereby sequentially selecting the driving transistors 23 in these rows connected to the voltage supply lines Z]_ to Zm. More specifically, as shown in FIG. 4, the voltage supply driver 6 individually supplies, to the voltage supply lines to Zm, a low-level tone designating current reference voltage VLQW (which is equal to or lower than the reference voltage Vgs) as a selection signal or a high-level driving current reference voltage V^IQH (which is higher than both the reference voltage Vgs and tone designating current reference voltage VLQ ) as a non-selection signal, thereby sequentially selecting the voltage supply lines Z]_ to Zm. That is, in the selection period Tgg in which the selection scan line Xj_ in the ith row is selected, the voltage supply driver 6 applies the tone designating current reference voltage VJ^Q to the voltage supply line Zj_ in the ith row, thereby selecting the voltage supply line Zj_ in the ith row. While applying the tone designating current reference voltage VLQW to the voltage supply line Zj_, the voltage supply driver 6 applies the driving current reference voltage VH GH to the other voltage supply lines Z]_ to Zm (except for the voltage supply line Zj_) . On the other hand, in the non-selection period TNSE in which the selection scan line Xi in the ith row is not selected, the voltage supply driver 6 applies the driving current reference voltage V^JQ^ to the voltage supply line Zj_ to cancel the selection of the voltage supply line Zj_ in the ith row. Since the driving current reference voltage V^JQH is higher than the reference voltage Vgg, an electric current flows from the voltage supply line Zj_ to the organic EL element Ej_ j if the driving transistor 23 is ON and the transistor 21 is OFF. The tone designating current reference voltage vLOW applied by the voltage supply driver 6 is equal to or lower than the reference voltage Vgg. Therefore, even when the driving transistor 23 of each of the pixels P]_ l to Pm n is turned on in the selection period Tgjr, a zero voltage or reverse bias voltage is applied between the anode and cathode of each of the organic EL elements E]_ ]_ to Em n. Accordingly, no electric current flows through the organic EL elements E]_ l to Em n in the selection period Tgg, so the organic EL elements E_ to Em n do not emit light. On the other hand, the driving current reference voltage VHIGH applied by the voltage supply driver 6 is higher than the reference voltage Vgg. As shown in FIG. 5, the driving current reference voltage V^JQ^ i-s so set that a source-to-drain voltage V of the driving transistor 23 is in a saturated region. Accordingly, when the driving transistors 23 are ON in the non-selection period T^SE' a forward bias voltage is applied to the organic EL elements E]_ ]_ to Em n. In the non-selection period T^gg, therefore, an electric current flows through the organic EL elements E]_ ]_ to Em n, and the organic EL elements E]_ to Em n emit light. The driving current reference voltage V^JQ^ will be explained below. FIG. 5 is a graph showing the current-voltage characteristics of the N-channel field-effect transistor. Referring to FIG. 5, the abscissa indicates the divided voltage of the driving transistor and the divided voltage of the organic EL element connected in series to the driving transistor, and the ordinate indicates the current value of an electric current in the drain-to-source path. In an unsaturated region (a region where source-to-drain voltage Vpg < drain saturated threshold voltage V^: the drain saturated threshold voltage V^H is a function of a gate-to-source voltage Vgg, and is uniquely determined by the gate-to-source voltage Vgg if the gate-to-source voltage Vg is determined) shown in FIG. 5, if the gate-to-source voltage Vgg is constant, a drain-to-source current Irjg increases as the source-to-drain voltage Vpg increases. In addition, in a saturated region (in which source-to-drain voltage Vβg ≥ drain saturated threshold voltage V^) shown in FIG. 5, if the gate-to-source voltage VGg is constant, the drain-to-source current Ipg is substantially constant even when the source-to-drain voltage Vgg increases. Also, in FIG. 5, gate-to-source voltages Vggi to VGSMAX have the relationship 0 [V] < VGS1 < VGS2 < VGS3 < ^GS4 < VGSMAX- That is, as is apparent from FIG. 5, if the source-to-drain voltage Vrjg is constant, the drain-to-source current Irjg increases in both the unsaturated and saturated regions as the gate-to-source voltage VGg increases. In addition, the drain saturated threshold voltage V^H increases as the gate-to-source voltage VGg increases. From the foregoing, in the unsaturated region, the drain-to-source current Irjg changes if the source-to-drain voltage Vp slightly changes while the gate-to-source voltage VGg is constant. In the saturated region, however, the drain-to-source current Irjg is uniquely determined by the gate-to-source voltage VGg. The drain-to-source current Ipg when the maximum gate-to-source voltage VGg^AX is applied to the driving transistor 23 is set to be an electric current which flows between the common electrode and the pixel electrode 51 of the organic EL element Ej_ ^ j which emits light at the maximum luminance. Also, the following equation is met so that the driving transistor 23 maintains the saturated region in the selection period Tgj? even when the gate-to-source voltage VGg of the driving transistor 23 is the maximum voltage VGgι[Aχ in the non-selection period. vLOW = VHIGH _VE - VSS = VTHMAX where Vg is the anode-to-cathode voltage which the organic EL element Ej_ j requires to emit light at the maximum luminance in the light emission life period, and VTH AX is the source-to-drain saturated voltage level of the driving transistor 23 when the voltage is VG M^χ. The driving current reference voltage V^JQJ-J is set to satisfy the above equation. Accordingly, even when the source-to-drain voltage Vpg of the driving transistor 23 decreases by the divided voltage of the organic EL element Ej_ j connected in series to the driving transistor 23, the source-to-drain voltage Vrjg always falls within the range of the saturated state, so the drain-to-source current Irjg is uniquely determined by the gate-to-source voltage VGg. As shown in FIGS. 1 and 3, the current lines Y]_ to Yn are connected to the current terminals CT]_ to
CTn of the current source driver 3 via the switches S]_ to Sn. An 8-bit digital tone image signal is input to the current source driver 3. This digital tone image signal input to the current source driver 3 is converted into an analog signal by an internal D/A converter of the current source driver 3. The current source driver 3 generates, at the current terminals
CT;L to CTn, a tone designating current IpAT having a current value corresponding to the converted analog signal. As shown in FIG. 4, the current source driver 3 controls the current value of the tone designating current IQATA at the current terminals CT_ to CTn in accordance with the image signal for each selection period T g of each row, and holds the current value of the tone designating current IQATA constant in a period from the end of each reset period TR to the end of the corresponding selection period Tgg. The current source driver 3 supplies the tone designating current iDATA from the current lines Y]_ to Yn to the current terminals CT]_ to CTn via the switches S]_ to Sn. As shown in FIGS. 1 and 3, the switches S]_ to Sn are connected to the current lines Y]_ to Yn, and the current terminals CT]_ to CTn of the current source driver 3 are connected to the switches S]_ to Sn. In addition, the switches Sj. to Sn are connected to a reset input terminal 41, and a reset voltage VR is applied to the switches S]_ to Sn via the reset input terminal 41. The switches S to Sn are also connected to a switching signal input terminal 42, and a switching signal Φ is input to the switches S_ to Sn via the switching signal input terminal 42. Furthermore, the switches S]_ to Sn are connected to a switching signal input terminal 43, and a switching signal inv. Φ obtained by inverting the switching signal Φ is input to the switches S]_ to Sn via the switching signal input terminal 43. The reset voltage VR is constant and has the same level (voltage value) as the tone designating current reference voltage VLQW- More specifically, the reset voltage VR is set at 0 [V] by grounding the reset input terminal 41. Especially when the reset voltage VR of the ith row is made equal to the voltage of the voltage supply line Zj_ in the ith row in the selection period Tgg, the voltages of the electrodes 24A and 24B of the capacitor 24 become equal to each other. Consequently, the capacitor 24 is discharged, so the gate-to-source voltage of the driving transistor 23 is set at 0V. The switch Sj (which is interposed between the current line Yj in the jth column and the current terminal CTj in the jth column) switches the state in which the current source driver 3 supplies the tone designating current IQATA to the current line Yj , and the state in which the reset voltage VR is applied to the current line Yj . That is, as shown in FIG. 4, if the switching signal Φ is at high level and the switching signal inv.Φ is at low level, the switch Sj shuts off the electric current of the current terminal CTj , and applies the reset voltage VR to the current line Yj , the drain 21d of the first transistor 21, the electrode 24B of the capacitor 24, the source 23s of the driving transistor 23, and the pixel electrode 51 of the organic EL element Ex?j (1 ≤ x ≤ m), thereby discharging the electric charge stored in these components in the preceding selection period Tgg. On the other hand, if the switching signal Φ is at low level and the switching signal inv.Φ is at high level, the switch Sj allows the electric current of the current terminal CTj to flow through the current line Yj , and shuts down the application of the reset voltage VR to the current line Yj . The cycle of the switching signals Φ and inv.Φ will be explained below. As shown in FIG. 4, the cycle of the switching signals Φ and inv. Φ is the same as the selection period Tgg. That is, when the selection scan driver 5 starts applying the ON voltage VQN to one of the selection scan lines X]_ to Xm (i.e., when the selection period Tgg of each row starts) , the switching signal Φ changes from high level to low level, and the switching signal inv. Φ changes from low level to high level. While the selection scan driver 5 is applying the ON voltage VQN to one of the selection scan lines Xl to Xm (i.e., in the selection period Tgg of each row) , the switching signal Φ changes from low level to high level, and the switching signal inv.Φ changes from high level to low level. A period in which the switching signal Φ is at high level and the switching signal inv. Φ is at low level in the selection period Tgg of the selection scan line Xj_ in the ith row is called the reset period TR of the ith row. An example of the switch Sj will be explained below. The switch Sj is made up of first and second N-channel field-effect transistors 31 and 32. The gate of the first transistor 31 is connected to the switching signal input terminal 43, and thus the switching signal inv.Φ is input to the gate of the transistor 31. Also, the gate of the second transistor 32 is connected to the switching signal input terminal 42, and thus the switching signal Φ is input to the gate of the transistor 32. The drain of the first transistor 31 is connected to the current line Yj , and the source of the transistor 31 is connected to the current terminal CTj . The drain of the transistor 32 is connected to the current line Yj . The source of the transistor 32 is connected to the reset input terminal 41, and the reset voltage VR which is a constant voltage is applied to the source of the transistor 32. In this arrangement, when the switching signal Φ is at high level and the switching signal inv.Φ is at low level, the transistor 32 is turned on, and the transistor 31 is turned off. When the switching signal Φ is at low level and the switching signal inv.Φ is at high level, the transistor 31 is turned on, and the transistor 32 is turned off. The transistors 31 and 32 can be fabricated in the same steps as the transistors 21 to 23 of the pixel circuits D]_ to Dm n. The functions of the pixel circuits D]_ to Dm n will be described below with reference to FIGS. 6 to 8. In FIGS. 6 to 8, the flows of electric currents are indicated by arrows. FIG. 6 is a circuit diagram showing the states of the voltages in the reset period TR of the selection period Tgjr of the ith row. As shown in FIG. 6, in the reset period TR of the ith row, the selection scan driver 5 applies the ON voltage VQN to the selection scan line Xj_, and the voltage supply driver 6 applies the tone designating current reference voltage VLQW to the voltage supply line Zj_. In addition, in the reset period TR of the ith row, the switches S to Sn apply the reset voltage VR to the current lines Y to Yn. In the reset period TR of the ith row, therefore, the first transistors 21 of the pixel circuits Dj_ 1 to Dj_ n are ON. Consequently, as shown in FIG. 4, the voltages of the pixel electrodes 51 of the organic EL elements Ej_ i to Ej_ n, the drains 21d of the first transistors 21 in the ith row, the electrodes 24B of the capacitors 24 in the ith row, the sources 23s of the driving transistors 23 in the ith row, and the current lines Y]_ to Yn are set in a steady state by the reset voltage VR, thereby discharging the electric charge stored by these parasitic capacitances in the preceding selection period Tgg. Accordingly, the tone designating current IoATA having a steady current value can be rapidly written in the next selection period Tgg. The parasitic capacitances of the organic EL elements Ej_ l to Ej_ n are particularly large. Therefore, when the tone designating current IoATA having a low current value is written, it takes a long time to make the current value steady by resetting the electric charge written in the organic EL element in the preceding frame period TgG if the reset voltage VR is not applied in the selection period Tgg.
However, the reset voltage VR is forcedly applied in the selection period T g, so the parasitic capacitance of the organic EL element can be rapidly discharged. Also, when the reset voltage VR of the ith row, which is applied in the selection period T g is made equal to that of the voltage supply line Zj_ in the ith row, the voltages of the electrodes 24A and 24B of the capacitor 24 become equal to each other, so the electric charges written in the capacitor 24 in the preceding frame period TgG are removed. In addition, although the second transistors 22 and driving transistors 23 of the pixel circuits D_ to Dj_ n are ON, the tone designating current reference voltage VLQ equal to or lower than the reference voltage Vgg is applied to the voltage supply line Z_, so the tone designating current IQ^TA which flows from the voltage supply line Zj_ to the driving transistors 23 does not flow through the organic EL elements Ej_ ]_ to Ei,n. FIG. 7 is a circuit diagram showing the states of the electric currents and voltages after the reset period TR in the selection period Tgg of the ith row. As shown in FIG. 7, after the reset period TR in the selection period Tgg of the ith row, the selection scan driver 5 keeps applying the ON voltage VQN to the selection scan line Xj_, and the voltage supply driver 6 keeps applying the tone designating current reference voltage LQW to the voltage supply line Zj_. In addition, after the reset period TR in the selection period Tgg of the ith row, the current source driver 3 controls the switches S]_ to Sn to supply the tone designating current IQATA from the current lines Y]_ to Yn to the current terminals CT^ to CTn. In the selection period Tgg of the ith row, the second transistors 22 of the pixel circuits Dj_ l to D_ n in the ith row are ON. Since the second transistors 22 of the pixel circuits Dj_ 1 to Dj_ n are ON, the voltage is also applied to the gates 23g of the driving transistors 23 of the pixel circuits Dj_ _ to Dj_ n, so the driving transistors 23 of the pixel circuits Dj_ j_ to Dj_ n are turned on. Furthermore, since the first transistors 21 of the pixel circuits Dj_ 1 to Dj_ n are also ON, the first transistors 21 of the pixel circuits Dj_ l to Dj_ n supply the tone designating current I ATA fro the voltage supply line Z_ to the current lines Y^ to Yn via the drains 23d and sources 23s of the driving transistors 23. In this state, as shown in FIG. 4, the voltage of the current line Yj drops until the tone designating current I ATA becomes steady. Also, although the driving transistors 23 of the pixel circuits Dj_ l to Dj_ n are ON, the low-level tone designating current reference voltage ILOW is applied to the voltage supply line Z_, so no electric current flows from the voltage supply line Z to the organic
EL elements Ej_ -_ to Ej_ n. Therefore, the current value of the tone designating current IDATA flowing through the current lines Y to Yn becomes equal to the current value of the electric current Irjg between the drain 23d and source 23s of the driving transistor 23. In addition, the level of the voltage between the gate 23g and source 23s of the driving transistor 23 follows the current value of the tone designating current IDATA which flows from the drain 23d to the source 23s. Accordingly, the driving transistor 23 converts the current value of the tone designating current IDATA into the level of the voltage between the gate 23g and source 23s, and electric charges corresponding to the level of the voltage between the gate 23g and source 23s of the driving transistor 23 are held in the capacitor 24. Note that the gate 23g and drain 23d of the driving transistor 23 are connected via the second transistor 22, and the ON resistance of the second transistor 22 upon selection is negligibly low. Therefore, the voltage applied to the gate 23g and the voltage applied to the drain 23d of the driving transistor 23 are substantially equal, so the tone designating current IoATA becomes the electric current Irjg which changes on the broken line VTH shown in FIG. 5. That is, when the voltages of the gate 23g and drain 23d of the driving transistor 23 are equal, the voltage Vrjg between the source 23s and drain 23d is equal to the threshold voltage V^H between the unsaturated and saturated regions. FIG. 8 is a circuit diagram showing the states of the electric currents and voltages in the non-selection period T^jgE °f the ith row. As shown in FIG. 8, in the non-selection period T^ E of the ith row, the selection scan driver 5 applies the OFF voltage VQFF to the selection scan line Xj_, and the voltage supply driver 6 applies the driving current reference voltage V^ Q^ to the voltage supply line Zj_. In the non-selection period T^g of the ith row, the first transistors 21 of the pixel circuits Dj_ ]_ to Dj_ n are OFF. Therefore, the first transistors 21 of the pixel circuits Dj_ 1 to Dj_ n shut off the tone designating current IoATA flowing through the current lines Y]_ to Yn, thereby preventing an electric current from flowing from the voltage supply line Zj_ to the current lines Y]_ to Yn via the driving transistors 23. In addition, since the second transistor 22 of each of the pixel circuits Dj_ to Dj_ n in the ith row is turned off, the second transistor 22 confines the electric charges in the capacitor 24. In this manner, the second transistor 22 holds the level of the converted voltage between the gate 23g and source 23s of the driving transistor 23, thereby storing the current value of the electric current which flows through the source-to-drain path of the driving transistor 23. In this state, the high-level driving current reference voltage VHIGH by which the source-to-drain voltage Vrjg of the driving transistor 23 maintains the saturated region is applied to the voltage supply line Zj_, and the driving transistor
23 of each of the pixel circuits Dj_ 1 to Dj_ n is ON. Accordingly, each driving transistor 23 supplies the driving current from the voltage supply line Zj_ to a corresponding one of the organic EL elements Ej_ l to Ej_ n to allow it to emit light at luminance corresponding to the current value of the driving current. In this state, the level of the converted voltage between the gate 23g and source 23s of the driving transistor 23 of each of the pixel circuits Dj_ l to Dj_ n is held by the capacitor 24 so as to be equal to the level of the voltage when the tone designating current IQATA flows through a corresponding one of the current lines Y to Yn in the second half of the selection period TgE- As shown in FIG. 5, a divided voltage VE of each of the organic EL elements E-j_ l to Ej_ n in the non-selection period T^gE is obtained by subtracting, from the driving current reference voltage VJ^JQH, the voltage Vpg on the EL load border line indicated by the alternate long and short dashed line, which is obtained when a driving current (equivalent to Irjg shown in FIG. 5) having a current value equal to that of the tone designating current IoATA flows. That is, the voltage difference on the right side of the EL load border line is the divided voltage of one organic EL element. As described above, the divided voltage V of the organic EL elements Ej_ to Ej_ n rises as the luminance tone rises. In the non-selection period 1* NSE' the driving current reference voltage V^ Q^ is set higher than a voltage obtained by adding the divided voltage VEL when the luminance tone of the organic EL elements Ej_ ]_ to E_ n is a minimum to the ON resistance Vpg between the drain 23d and source 23s of the driving transistor at that time, and higher than a voltage obtained by adding the divided voltage VEL when the luminance tone of the organic EL elements Ej_ ]_ to Ej_ n is a maximum to the ON resistance V^ between the drain 23d and source 23s of the driving transistor at that time. Also, in the non-selection period T^gE, the voltage of the source 23s of the driving transistor 23 rises as the voltage VGg between the gate 23g and source 23s, which is held in the selection period T E rises. Although the capacitor 24 changes the electric charge in the electrode 24B connected to the source 23s accordingly, the voltage VGg between the gate 23g and source 23s is held constant by equally changing the electric charge in the electrode 24A. As shown in FIG. 5, therefore, between the drain 23d and source 23s of the driving transistor 23 in the non-selection period T^gE is always applied a saturated region voltage, and the current value of the driving current which flows through each of the organic EL elements Ej_ l to Ej_ n in the non-selection period TNSE is made equal to the current value of the tone designating current IDATA by the electric charges held between the gate 23g and source 23s in the selection period Tg - Also, as shown in FIG. 4, the voltage of the pixel electrodes 51 of the organic EL elements Ej_ to Ej_ n in the non-selection period T^ E rises as the luminance tone rises. This increases the voltage difference between the pixel electrodes 51 and the common electrode as a cathode, and increases the luminance of the organic EL elements Ej_ ]_ to E_ n. As described above, the luminance (the unit is nit.) of the organic EL elements Ej_ l to Ej_ n is uniquely determined by the current value of the tone designating current Io TA which flows through the pixel circuits Dj_ l to Dj_ n in the selection period TgE- A method of driving the organic EL display panel 2 by the current source driver 3, selection scan driver 5, voltage supply driver 6, and switches S^ to Sn, and the display operation of the organic EL display 1 will be described below. As shown in FIG. 4, the selection scan driver 5 applies the ON voltage VQN in order from the selection scan line X]_ in the first row to the selection scan line Xm in the mth row (the selection scan line Xm in the mth row is followed by the selection scan line X^ in the first row) , thereby selecting these selection scan lines. In synchronism with this selection by the selection scan driver 5, the voltage supply driver 6 applies the tone designating current reference voltage VLOW in order from the voltage supply line in the first row to the voltage supply line Zm in the mth row (the voltage supply line Zm in the mth row is followed by the voltage supply line Z in the first row) , thereby selecting these voltage supply lines. In the selection period T E of each row, the current source driver 3 controls the current terminals CT^ to CTn to generate the tone designating current IQATA having a current value corresponding to the image signal. Also, at the start of the selection period TgE of each row (at the end of the selection period TgE of the preceding row) , the switching signal Φ changes from low level to high level, the switching signal inv. Φ changes from high level to low level, and the reset voltage VR which removes the electric charges stored in the current lines Y_ to Yn and the electric charges stored in the pixel electrodes 51 via the first transistors 21 is applied. In the selection period T E of each row (at the end of the reset period TR of each row) , the switching signal Φ changes from high level to low level, and the switching signal inv.Φ changes from low level to high level. In the reset period TR in the initial part of the selection period TgE therefore, the switches S]_ to Sn allow the tone designating current IQATA to flow between the current terminals CT]_ to CTn and current lines Y_ to Yn, and shut down the application of the reset voltage VR to the current lines Y^ to Yn. After the reset period TR in the selection period TgE? the switches S^ to Sn shut off the flow of the electric current between the current terminals CT]_ to CTn and current lines Y]_ to Yn, and allow the application of the reset voltage VR to the current lines Y]_ to Yn. The current value of the tone designating current IDATA decreases as the luminance tone lowers. In this state, the voltages of the current lines Y]_ to Yn and pixel electrodes 51 approximate to the tone designating current reference voltage VLOW' i.e., to the reset voltage VR. Also, if the tone designating current "[DATA having a large current value flows in the selection period TgE of the preceding row or of the preceding frame period Tgς, the voltage of the pixel electrodes 51 become much lower than the reset voltage VR via the current lines Yi to Yn and first transistors 21. If, therefore, no reset voltage is applied to the current lines Y]_ to Yn without forming the switches Si to Sn, and the tone designating current IoATA having a low luminance tone and low current value is to be kept supplied to the ith row, the amount of electric charges to be modulated is large because the electric charges of the current lines Y^ to Yn, which are stored in accordance with the tone designating current IQATA having a large current value in the selection period T E of the (i - l)th row are held in the parasitic capacitances of the current lines Y^ to Yn. Accordingly, it takes a long time to obtain a desired current value of the tone designating current IQATA- Likewise, if no reset voltage is applied to the pixel electrodes 51 in the selection period without forming the switches S]_ to Sn, and the tone designating current IQATA having a low luminance tone and low current value is to be kept supplied in the next frame period Tgrj, the amount of electric charges to be modulated are large because the electric charges of the pixel electrodes 51 in the ith row, which are stored in accordance with the tone designating current IQAT having a large current value in the selection period T E of the frame period TgG before the next frame period T G are held in the parasitic capacitances of the pixel electrodes 51 in the ith row. Accordingly, it takes a long time to obtain a desired current value of the tone designating current IDATA* In the selection period Tg£, therefore, no sufficient electric charges can be held so that the required voltage is obtained between the gate 23g and source 23s of the driving transistor 23. As a consequence, the driving current in the non-selection period Tjg becomes different from the tone designating current IQATA' and this makes accurate tone display impossible . Since, however, the switches S]_ to Sn which apply the reset voltage VR in the reset period TR are provided, the electric charges stored in the current lines Y]_ to Yn and the electric charges stored in the pixel electrodes 51 via the first transistors 21 can be rapidly removed. Accordingly, the voltage between the gate 23g and source 23s of the driving transistor 23 can be rapidly set to a voltage by which the tone designating current IQATA having a low luminance tone and low current value flows. Since this makes high-speed display possible, images particularly excellent in motion image characteristics can be displayed. FIG. 9 is a timing chart showing, from above, the voltage of the selection scan line X_, the voltage of the voltage supply line Z]_, the switching signal inv. Φ, the switching signal Φ, the current value of the current terminal CTj, the current value of an electric current which flows through the driving transistor 23 of the pixel circuit Dj.,j/ the voltage of the pixel electrode 51 of the organic EL element Ej_ j , and the current value of an electric current which flows through the organic EL element Ej_ j . Referring to FIG. 9, the abscissa represents the common time. As shown in FIGS. 6 and 9, when the selection scan driver 5 applies the ON voltage VQN to the selection scan line Xj_ in the ith row (i.e., in the selection period TgE of the ith row) , the OFF voltage VQ F is applied to the other selection scan lines X]_ to Xm (except for X-j_) . In the selection period TgE of the ith row, therefore, the first and second transistors 21 and 22 of the pixel circuits Dj_ l to D-j_ n in the ith row are ON, and the first and second transistors 21 and 22 of the pixel circuits ^> \ to Dm n (except for Dj_ ]_ to Dj_ n) in the other rows are OFF. As described above, in the selection period TgE of the ith row, the tone designating current reference voltage V O is applied to the voltage supply line Zj_, and the second transistors 22 of the pixel circuits Dj_ l to Dj_ n in the ith row are ON. Accordingly, the voltage is also applied to the gates 23g of the driving transistors 23 of the pixel circuits D_ ι to Dj_ n.in the ith row, so the driving transistors 23 are turned on. In the reset period TR in the initial part of the selection period Tgg of the ith row, the transistors 32 of the switches S\ to Sn are turned on. Therefore, the voltage supply line Zj_ is electrically connected to the reset input terminal 41 via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ to Dj_ n and the current lines Y to Yn. In this state, the voltage applied from the voltage supply line Zj_ to the reset input terminal 41 via the driving transistors
23 and first transistors 21 of the pixel circuits Dj_ to Dj_ n and the current lines Y to Yn is equal to the reset voltage VR (= tone designating current reference voltage VLOW) which is equal to or lower than the reference voltage Vgg. Accordingly, the voltage of the pixel electrodes 51 of the organic EL elements Ej_ ]_ to Ej_ n is also equal to the reset voltage VR. In addition, since the reset voltage VR is applied to the current lines Y]_ to Yn, the electric charges stored in the parasitic capacitances of the current lines Y]_ to Yn and the electric charges stored in the parasitic capacitances of the pixel circuits Dj_ to Dj_ n including the pixel electrodes 51 are removed, so the voltage of these components becomes equal to the reset voltage VR. As a consequence, the organic EL elements Ej_ l to E_ n stop emitting light immediately after the start of the reset period TR of the ith row. As shown in FIGS. 7 and 9, in the second half of the selection period T E after the reset period TR, the ON voltage VQN is applied to the selection scan line Xj_ in the ith row, and the tone designating current reference voltage VLOW is applied to the voltage supply line Zj_ in the ith row. Therefore, the first transistors 21, second transistors 22, and driving transistors 23 of the pixel circuits Dj_ ]_ to D- n in the ith row are ON. After the reset period TR in the selection period Tg , the transistors 31 of the switches S to Sn are turned on, so the switches S^ to Sn allow an electric current to flow between the current terminals CT]_ to CTn and current lines Y-\_ to Yn. As a consequence, the current terminals CT_ to CTn are electrically connected to the voltage supply line Zj_ in the ith row. In this state, the current source driver 3 supplies the tone designating current ]"DATA from the voltage supply line Zj_ to the current terminals CT^ to CTn via the driving transistors 23 and first transistors 21 of the pixel circuits D^ to Di n' the current lines Y to Yn, and the switches S^ to Sn. Until the end of the selection period T E of the ith row, the current source driver 3 controls the current value of the tone designating current IQATA supplied to the current lines Y to Yn such that the current value is held constant in accordance with the image signal. In the second half of the selection period TgE of the ith row, the tone designating current IDAT flows along the voltage supply line Zj_ — > the path between the drain 23d and source 23s of the driving transistor 23 of each of the pixel circuits Dj_ ]_ to Dj_ n - the path between the drain 21d and source 21s of the first transistor 21 of each of the pixel circuits D-j_ ]_ to Di n ~* the current lines Y_ to Yn —» the transistors 31 of the switches S]_ to Sn —*► the current terminals CT]_ to CTn of the current source driver 3. In the selection period TgE of the ith row, therefore, the voltage applied from the voltage supply line Zj_ to the current terminals CT^ to CTn via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ l to Dj_ n and the current lines Y^ to Yn becomes steady. That is, since the voltage applied from the voltage supply line Z_ in the ith row to the current terminals CT]_ to CTn becomes steady, the voltage having a level corresponding to the current value of the tone designating current IQATA which flows through the driving transistor 23 is applied between the gate
23g and source 23s of the driving transistor 23, so electric charges corresponding to the level of this voltage between the gate 23g and source 23s of the driving transistor 23 is held in the capacitor 24. Consequently, the current value of the tone designating current IQATA which flows through the driving transistor 23 of each of the pixel circuits Dj_ 1 to Dj_ n in the ith row is converted into the level of the voltage between the gate 23g and source 23s of the driving transistor 23. In the reset period TR of the ith row as described above, the reset voltage VR is applied to the current lines Y]_ to Yn. Therefore, the voltage applied from the voltage supply line Zj_ to the reset input terminal 41 via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ l to Dj_ n and the current lines Y]_ to Yn can be made steady. Accordingly, even if a weak tone designating current IDATA flows through the current lines Y^ to Yn after the reset period TR of the ith row, electric charges corresponding to the tone designating current IQATA can ^e rapidly held in the capacitors 24 of the pixel circuits Dj_ ι to Dj_ n. As described above, the current value of the electric current which flows between the drain 23d and source 23s of the driving transistor 23 of each of the pixel circuits Dj_ to Dj_ n in the ith row and the level of the voltage between the source 23s and gate 23g are overwritten from those of the preceding frame period TgG. In the selection period T E of the ith row, therefore, the magnitude of the electric charges which are held in the capacitor 24 of each of the pixel circuits Dj_ l to Dj_ n in the ith row is overwritten from that of the preceding frame period Tgrj. The potential at arbitrary points in the paths from the driving transistors 23 of the pixel circuits Dj_ l to Dj_ n to the current lines Y]_ to Yn via the first transistors 21 changes in accordance with, e.g., the internal resistances of the transistors 21, 22, and 23, which change with time. In this embodiment, however, in the selection period T E, the current source driver 3 forcedly supplies the tone designating current IoATA rom the driving transistors 23 of the pixel circuits Dj_ to Dj_ n to the current lines Y to Yn via the first transistors 21. Therefore, even if the internal resistances of the transistors 21, 22, and 23 change with time, the tone designating current IQATA takes a desired current value. Also, in the selection period T E of the ith row, the common electrode of the organic EL elements Ej_ to Ej_ n in the ith row is at the reference voltage Vgg, and the voltage supply line Zj_ is at the tone designating current reference voltage VLOW which is equal to or lower than the reference voltage Vgg. As a consequence, a reverse bias voltage is applied to the organic EL elements Ej_ to Ej_ n in the ith row. Accordingly, no electric current flows through the organic EL elements Ej_ to Ej_ n in the ith row, so the organic EL elements Ej_ to Ej_ n do not emit light Subsequently, as shown in FIGS. 8 and 9, at the end time of the selection period TgE of the ith row (at the start time of the non-selection period Tjqgs of the ith row) , a signal output from the selection scan driver 5 to the selection scan line X_ changes from the high-level ON voltage VQN to the low-level OFF voltage VQFF- That is, the selection scan driver 5 applies the OFF voltage VQFF to the gate 21g of the first transistor 21 and the gate 22g of the second transistor 22 of each of the pixel circuits Dj_ to Dj_ n in the ith row. In the non-selection period T^gE °f the ith row, therefore, the first transistors 21 of the pixel circuits Dj_ l to Dj_ n in the ith row are turned off to prevent the electric current from flowing from the voltage supply line Z _ to the current lines Y]_ to Yn. In addition, in the non-selection period T^SE °f the ith row, when the second transistors 22 of the pixel circuits D_ l to Dj_ n in the ith row are turned off, the electric charges held in the capacitors 24 in the immediately preceding selection period Tg of the ith row are confined by the second transistors 22. Accordingly, the driving transistor 23 of each of the pixel circuits D_ l to Dj_ n in the ith row is kept ON in the non-selection period T^gE- That is, in each of the pixel circuits D_ l to D_ n in the ith row, the voltage Vgg between the gate 23g and source 23s of the driving transistor 23 in the non-selection period T^ E becomes equal to the voltage Vg between the gate 23g and source 23s of the driving transistor 23 in the immediately preceding selection period Tgg, i.e., the capacitor 24 in which the electric charges on the side of the electrode 24A are held by the second transistor 22 holds the voltage Vg between the gate 23g and source 23s of the driving transistor 23. Also, in the non-selection period T^ E of the ith row, the voltage supply driver 6 applies the driving current reference voltage VJUGH to the voltage supply line Zj_ in the ith row. In the non-selection period TNSE' the common electrode of the organic EL elements Ej_ l to Ej_ n in the ith row is at the reference voltage Vgg, and the voltage supply line Zj_ in the ith row is at the driving current reference voltage VJ-IJGH which is higher than the reference voltage Vgg, so the driving transistors 23 of the pixel circuits Dj_ l to Dj_ n in the ith row are ON. As a consequence, a forward bias voltage is applied to the organic EL elements Ej_ to Ej_ n. In the pixel circuits D^ to Dj_ n, therefore, a driving current flows from the voltage supply line Zj_ to the organic EL elements Ej_ l to Ej_ n via the driving transistors 23, and thus the organic EL elements Ej_ to Ej_ n emit light. More specifically, in the pixel circuit Dj_ j in the non-selection period Tj^gE of the ith row, the first transistor 21 electrically shuts off the path between the current line Yj and driving transistor 23, and the second transistor 22 confines the electric charges in the capacitor 24. In this manner, the level of the voltage, which is converted in the selection period T E, between the gate 23g and source 23s of the driving transistor 23 is held, and a driving current having a current value corresponding to the level of this voltage held between the gate 23g and source 23s is supplied to the organic EL element Ej → by the driving transistor 23. In this state, the current value of the driving current which flows through the organic EL elements Ej_ 1 to Ej_ n in the selection period TgE of the ith row is equal to the current value of the electric current which flows through the driving transistors 23 of the pixel circuits Dj_ ]_ to Dj_ n, and therefore equal to the current value of the tone designating current IQ^TA which flows through the driving transistors 23 of the pixel circuits D_ to D_ n in the selection period T E- As described above, in the selection period TgE, the current value of the tone designating current IDATA which flows through the driving transistors 23 of the pixel circuits D_ to Dj_ n is a desired current value. Therefore, a driving current having a desired current value can be supplied to the organic EL elements Ej_ ]_ to Ej_ n, so the organic EL elements Ej_ l to Ej_ n can emit light at a desired tone luminance. In the reset period TR of the (i + l)th row after the selection period T E of the ith row, as in the reset period TR of the ith row, the transistors 31 of the switches S^ to Sn are turned off, and the transistors 32 of the switches S]_ to Sn are turned on. Accordingly, in the reset period TR of the (i + l)th row, the tone designating current I TA does not flow through any of the current lines Y]_ to Yn, but the reset voltage VR is applied to all the current lines Y-]_ to Yn, the pixel electrodes 51 in the (i + l)th row, the electrodes 24B of the capacitors 24 in the (I + l)th row, and the sources 23s of the driving transistors 23 in the (i + l)th row. After the reset period TR in the selection period TgE of the (i + l)th row, as in the case of the ith row, the selection scan driver 5 selects the selection scan line X +χ in the (i + l)th row, so the tone designating current IQATA flows from the voltage supply line Z to the current terminals CT]_ to CTn via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ _ to Dj_ n, the current lines Y]_ to Yn, and the switches Dj_ -γ to Di/n. As described above, in the reset period TR, the reset voltage VR is forcedly applied to, e.g., the current lines Y to Yn and the pixel electrodes 51. Therefore, the charge amount of the parasitic capaci- tances of the current lines Y to Yn and the like approximates to the charge amount in a steady state in which a small electric current flows. Accordingly, even when the electric current which flows through the current lines Y to Yn after the reset period TR of the (i + l)th row is weak, a steady state can be immediately obtained. In this embodiment as described above, the current value of the driving current which flows through the organic EL elements E to Em n in the non-selection period T^gE is represented by the current value of the tone designating current IQATA after the reset period TR of the selection period TgE- Therefore, even when variations are produced in characteristics of the driving transistors 23 of the pixel circuits D^ to Dm n, no variations are produced in luminance of the organic EL elements E^ to Em n if the current value of the tone designating current IQATA r g ins the same for all the pixel circuits O to Dm n. That is, this embodiment can suppress planar variations by which pixels have different luminance values even though luminance tone signals having the same level are output to these pixels. Accordingly, the organic EL display 1 of this embodiment can display high-quality images. The tone designating current IQATA i ery weak because it is equal to the current value of the electric current which flows through the organic EL elements E_ to Em n in accordance with the luminance of the organic EL elements E]_ to Em n which emit light. The wiring capacitances of the current lines Y]_ to Yn delay the tone designating current IQATA which flows through the current lines Y]_ to Yn. If the selection period TgE is short, therefore, electric charges corresponding to the tone designating current ."DATA cannot be held in the gate-to-source path of the driving transistor 23. In this embodiment, however, the reset voltage VR is forcedly applied to the current lines Y-\_ to Yn in the reset period TR of each row.
Therefore, even if the tone designating current IQATA is weak or the selection period T E is short, electric charges corresponding to the tone designating current ]*DATA can be held in the gate-to-source path of the driving transistor 23 within the selection period T £. Also, in this embodiment, the data driving circuit 7 applies the reset voltage VR to the current lines Y]_ to Yn in the selection period Tg - Therefore, the first transistor 21 has both the function of a switching element which loads the reset voltage VR into each of the pixel circuits D]_ to Dm n, and the function of a switching element which loads the tone designating current IQATA into each of the pixel circuits D]_ to Dm n. This makes it unnecessary to form any switching TFT, which loads a blanking signal into a pixel circuit as in the conventional device (Jpn. Pat. Appln. KOKAI Publication No. 2000-221942), in the pixel circuits Ω to Dm n in addition to the first transistors 21. Accordingly, the number of transistors necessary for the pixel circuits D]_ ]_ to Dm n does not increase. When the organic EL elements E]_ i to Em n are formed on the same surface as the pixel circuits D]_ to Dm n, therefore, the aperture ratio of the pixels P]_ 1 to Pm n does not decrease. [Second Embodiment] FIG. 10 is a block diagram showing an organic EL display 101 according to the second embodiment to which the organic EL display of the present invention is applied. In FIG. 10, the same reference numerals and symbols as in the organic EL display 1 of the first embodiment denote the same parts in the organic EL display 101, and an explanation thereof will be omitted. Similar to the organic EL display 1 shown in FIG. 1, the organic EL display 101 includes an organic EL display panel 2, scan driving circuit 9, and data driving circuit 107. The organic EL display panel 2 and scan driving circuit 9 are the same as the organic EL display panel 2 and scan driving circuit 9 of the first embodiment. The data driving circuit 107 is different from the data driving circuit 7 of the first embodiment . The data driving circuit 107 includes n current terminals DT]_ to DTn, a current control driver 103 which supplies a pull current ILI to the current terminals DT]_ to DTn, first current mirror circuits M]_]_ to Mn]_ and second current mirror circuits M^2 to Mn2 which convert the pull current ILI flowing through the current terminals DT]_ to DTn into a tone designating current IQATA' and switches T]_ to Tn interposed between current lines Y_ to Yn, the first current mirror circuits ]_χ to Mn]_, and the second current mirror circuits M]_2 to Mn2. An 8-bit digital tone image signal is input to the current control driver 103. This digital tone image signal loaded into the current control driver 103 is converted into an analog signal by an internal D/A converter of the current control driver 103. The driver 103 generates the pull current ILI having a current value corresponding to the analog image signal at the current terminals DT_ to DTn . The driver 103 supplies the pull current ILI fr m the first current mirror circuits ]__ to Mn_ formed for individual rows to the current terminals DT]_ to DTn. In accordance with the pull current I I, the current control driver 103 supplies the tone designating current IQATA from driving transistors 23 in the individual rows to the second current mirror circuits M]_2 to n2 via the current lines Y]_ to Yn. The operation timings of the current control driver 103 are the same as those of the current source driver 3 of the first embodiment. That is, the current control driver 103 controls the current value of the pull current ILI at the current terminals DT]_ to DTn in each selection period T E of each row in accordance with the image signal, and makes the current value of the pull current ILI steady in a period from the end of each reset period TR to the end of the corresponding selection period T E- The pull current ILI supplied by the current control driver 103 is larger than and proportional to the tone designating current IDATA supplied by the current source driver 3 of the first embodiment. The first current mirror circuits M]_]_ to Mn]_ and second current mirror circuits M]_2 to n2 convert the pull current ILI which flows through the current terminals DT]_ to DTn into the tone designating current iDATA at a predetermined conversion ratio. Each of the first current mirror circuits M ι to Mnι is made up of two P-channel MOS transistors 61 and 62. The transistors 61 and 62 can be fabricated by the same steps as the transistors 21 to 23 of each of pixel circuits D]_ ]_ to Dm n. Each of the second current mirror circuits M^2 to Mn2 is made up of two N-channel MOS transistors 63 and 64. The transistors 63 and 64 can be partially fabricated by the same steps as the transistors 21 to 23 of each of the pixel circuits D^ _ to Dm,n. In the first current mirror circuits Mn to Mn]_, the gates and drains of the transistors 61 and the gates of the transistors 62 are connected to the current terminals DT]_ to DTn . The sources of the transistors 61 and 62 are connected to a reset input terminal 41 which outputs a reset voltage VR as a ground voltage. In the second current mirror circuits M^2 to Mn2, the gates and drains of the transistors 63 and the gates of the transistors 64 are connected together to the drains of the transistors 62. The sources of the transistors 63 and 64 are connected to a constant-voltage input terminal 45 to which a negative voltage
Figure imgf000064_0001
is applied, and the drains of the transistors 64 are connected to the sources of transistors 34 of the switches T]_ to Tn (to be described later) . In each of the first current mirror circuits M]_]_ to Mn]_, the channel resistance of the transistor 61 is lower than that of the transistor 62. In each of the second current mirror circuits M]_2 to n2, the channel resistance of the transistor 63 is lower than that of the transistor 64. Each of the switches T]_ to Tn has an N-channel MOS transistor 33 and the N-channel MOS transistor 34. The transistors 33 and 34 can be fabricated by the same steps as the transistors 21 to 23 of each of the pixel circuits D_ to Dm^n. An example of the switch Tj will be explained below. The gate of the transistor 34 of the switch Tj is connected to a switching signal input terminal 43, and thus a switching signal inv.Φ is input to the gate of the transistor 34. Also, the gate of the transistor 33 is connected to a switching signal input terminal 42, and thus a switching signal Φ is input to the gate of the transistor 33. The drains of the transistors 33 and 34 are connected to the current line Yj , the source of the transistor 33 is connected to the source of the transistor 61 of the first current mirror circuit M- and the reset input terminal 41, and the source of the transistor 34 is connected to the drain of the transistor 64 of the second current mirror circuit j_2 • In this arrangement, when the switching signal Φ is at high level and the switching signal inv.Φ is at low level, the transistor 33 is turned on, and the transistor 34 is turned off. The switching signals Φ and inv.Φ have the same waveforms as in FIG. 4 of the first embodiment. Accordingly, the switches T]_ to Tn switch the state in which the tone designating current IDATA obtained by modulating the current value of the pull current ILI by the first current mirror circuits Mii to Mnι and second current mirror circuits M12 to Mn2 is supplied to the driving transistors 23 and current lines Yi to Yn, and the state in which the reset voltage VR is applied to the current lines Yi to Yn. When the current control driver 103 supplies the pull current ILI to the current terminal DTj , an electric current which flows through the drain-to-source path of the transistor 62 in the first current mirror circuit Mj 1 has a value obtained by multiplying the ratio of the channel resistance of the transistor 62 to that of the transistor 61 by the current value of the pull current ILI R the drain-to-source path of the transistor 61. In the second current mirror circuit j2, an electric current which flows through the drain-to-source path of the transistor 64 has a value obtained by multiplying the ratio of the channel resistance of the transistor 64 to that of the transistor 63 by the current value of an electric current in the drain-to-source path of the transistor 63. The current value of the electric current in the drain-to-source path of the transistor 63 matches the electric current which flows through the drain-to-source path of the transistor 62. Therefore, the current value of the tone designating current iDATA i obtained by multiplying the ratio of the channel resistance of the transistor 64 to that of the transistor 63 by the value which is obtained by multiplying the ratio of the channel resistance of the transistor 62 to that of the transistor 61 by the current value of the pull current ILI in the drain-to-source path of the transistor 61. As described above, the first current mirror circuits Mn to Mnι and second current mirror circuits M12 to n2 convert the pull current ILI which flows through the current terminals DTi to DTn into the tone designating current IDATA* Since the tone designating current IoATA flows through the output sides of the second current mirror circuits M 2 to Mn2, i.e., the drains of the transistors 64, these drains of the transistors 64 of the second current mirror circuits M12 to Mn2 are equivalent to the current terminal CTj of the current source driver 3 of the first embodiment. That is, an arrangement obtained by combining the first current mirror circuits Mn to Mn]_, second current mirror circuits M12 to Mn2, and current control driver 103 is equivalent to the current source driver 3 of the first embodiment. In the first embodiment, the reset voltage VR is at the same level as the tone designating current reference voltage VLOW- ln the second embodiment, however, the reset voltage VR is set at 0 [V] . Therefore, when a voltage Vgg is set at the ground voltage, no voltage difference is produced between pixel electrodes 51 as the anodes of the organic EL elements Ei l to Em n and the common electrode as the cathode. As a consequence, electric charges stored in the pixel electrodes 51 can be easily removed. In order for the switches T to Tn to perform the switching operation, as in the first embodiment, the switching signal Φ is input to the switching signal input terminal 42, and the switching signal inv.Φ is input to the switching signal input terminal 43. The relationship between the timings of the switching signals Φ and inv. Φ and the selection timings of a selection scan driver 5 and voltage supply driver 6 is the same as in the first embodiment. Also, the operation timings of the selection scan driver 5 and voltage supply driver 6 in the second embodiment are the same as in the first embodiment. In the second embodiment, as in the first embodiment, in the reset period TR of the former period in the selection period TgE of the ith row, the transistors 33 of the switches Ti to Tn are turned on, so a voltage supply line Zj_ is electrically connected to the reset input terminal 41 via the driving transistors 23 and first transistors 21 of the pixel circuits Dj_ i to Di n and the current lines Yi to Yn. Also, in the reset period TR of the ith row, the reset voltage VR is applied to the current lines Yi to Yn and pixel electrodes 51, so the electric charges stored in the parasitic capacitances of the current lines Yi to Yn and the electric charges stored in the parasitic capacitances of the pixel electrodes 51 can be rapidly removed. Accordingly, even when the weak tone designating current IQATA flows through the current lines Yi to Yn after the reset period TR of the ith row, electric charges corresponding to the tone designating current ID TA can be rapidly held in capacitors 24 of the pixel circuits Di i to Di n. In addition, in a non-selection period T^gE, the current value of a driving current which flows through the organic EL elements Ei to Em n is represented by the current value of the tone designating current IQATA after the reset period TR of each selection period T E- Therefore, even if variations are produced in characteristics of the driving transistors 23 of the pixel circuits Di i to Dm n, no variations are produced in driving current because the tone designating current IDATA is forcedly supplied to the driving transistors 23. As a consequence, no variations are produced in luminance of the organic EL elements E]_ ]_ to Em n. Furthermore, since the first current mirror circuits Mn to nι and second current mirror circuits M12 to Mn2 are formed, the current value of the tone designating current IβATA or" the current lines Y]_ to Yn is proportional to and smaller than the pull current
ILI at the current terminals DTi to DTn. Accordingly, even if the pull current ILI at the current terminals DTi to DTn is unexpectedly reduced by a leakage current produced in the current control driver 103 or the like, the tone designating current I TA °f the current lines Yl to Yn does not largely reduce. That is, even a decrease in output from the current control drive 103 caused by a current leak has no large influence on the tone designating current IoATA °f the current lines Yi to Yn, so the luminance of the organic EL elements Ei i to Em n does not largely decrease. In the second embodiment, the data driving circuit 107 can well generate the tone designating current IQATA even when the current control driver 103 cannot generate a weak electric current close to the tone designating current IDATA matching the light emission characteristics of the organic EL elements. The data driving circuit 107 applies the reset voltage VR to the current lines Yi to Yn in the selection period Tgg in the second embodiment as well. Therefore, the first transistor 21 has both the function of a switching element which loads the reset voltage VR into each of the pixel circuits Di i to Dm n, and the function of a switching element which loads the tone designating current IDATA into each of the pixel circuits Di i to Dm n. Accordingly, the number of transistors necessary for the pixel circuits Di l to Dm n does not increase. When the organic EL elements Ei l to Em n are formed on the same surface as the pixel circuits Di i to Dm n, therefore, the aperture ratio of the pixels Pi i to Pm n does not decrease.
[Third Embodiment] FIG. 11 is a block diagram showing an organic EL display 201 according to the third embodiment to which the organic EL display of the present invention is applied. In FIG. 11, the same reference numerals and symbols as in the organic EL display 1 of the first embodiment denote the same parts in the organic EL display 201, and an explanation thereof will be omitted. Similar to the organic EL display 1, the organic
EL display 201 includes an organic EL display panel 2, scan driving circuit 9, and data driving circuit 207. The organic EL display panel 2 and scan driving circuit 9 are the same as the organic EL display panel 2 and scan driving circuit 9 of the first embodiment. The data driving circuit 207 is different from the data driving circuit 7 of the first embodiment. The data driving circuit 207 includes a current control driver 203 which has n current terminals FT]_ to FTn and supplies a push current I 2 to the current terminals FTi to FTn, current mirror circuits i to Mn for converting the push current IL2 flowing through the current terminals FTi to FTn, and switches Si to Sn interposed between current lines Yi to Yn and the current mirror circuits Mi to Mn. In the second embodiment, the current control driver 103 supplies the pull current ILI from the current mirror circuits i to Mn to the current terminals DTi to DTn. In the third embodiment, the current control driver 203 supplies the push current IL2 from the current terminals FTi to FTn to the current mirror circuits i to Mn. Each of the current mirror circuits Mi to Mn is made up of two N-channel MOS transistors 161 and 162. The transistors 161 and 162 can be fabricated by the same steps as transistors 21 to 23 of pixel circuits Ol f l to Dm,n. In each of the current mirror circuits Mi to Mn, the gate and drain of the transistor 161 and the gate of the transistor 162 are connected together, and the sources of the transistors 161 and 162 are connected to a constant-voltage input terminal 45. A constant voltage VQQ is applied to the constant-voltage input terminal 45. The level of the constant voltage VQQ is lower than a tone designating current reference voltage VLO and reference voltage Vgg. When the reference voltage Vgg or tone designating current reference voltage VLO is 0 IN] as in the first embodiment, the constant voltage VQQ is a negative voltage. An example of the switch Sj will be explained below. The switch Sj is made up of Ν-channel field-effect transistors 31 and 32. The gate of the transistor 31 is connected to a switching signal input terminal 43, and thus a switching signal inv.Φ is input to the gate of the transistor 31. Also, the gate of the transistor 32 is connected to a switching signal input terminal 42, and thus a switching signal Φ is input to the gate of the transistor 32. The drain of the transistor 31 is connected to the current line Yj , and the source of the transistor 31 is connected to the drain of the transistor 162. The drain of the transistor 32 is connected to the current line Yj . The source of the transistor 32 is connected to a reset input terminal 41, and thus a reset voltage VR as a constant voltage is applied to the source of the transistor 32. In this arrangement, when the switching signal Φ is at high level and the switching signal inv.Φ is at low level, the transistor 32 is turned on, and the transistor 31 is turned off. When the switching signal Φ is at low level and the switching signal inv.Φ is at high level, the transistor 31 is turned on, and the transistor 32 is turned off. The transistors 31 and 32 can be fabricated by the same steps as the transistors 21 to 23 of the pixel circuits D]_ i to Dm n. The reset voltage VR is preferably 0 [V] in order to completely discharge, e.g., the electric charges stored in the parasitic capacitances of the current lines Y]_ to Yn and the electric charges stored in the parasitic capacitances of pixel electrodes 51. The current control driver 203 controls the current value of the push current IL2 at the current terminals FTj. to FTn in accordance with the image signal in each selection period TgE of each row, and holds the magnitude of the push current IL2 constant in a period from the end of each reset period TR to the end of the corresponding selection period gE-
The push current IL2 supplied by the current control driver 203 is larger than and proportional to the tone designating current IoATA supplied by the current source driver 3 of the first embodiment. The channel resistance of the transistor 161 is lower than that of the transistor 162. Therefore, the current mirror circuits Mi to Mn convert the push current IL2 which flows through the current terminals FTi to FTn into a tone designating current IoATA- Tne current value of the tone designating current IDATA is substantially a value obtained by multiplying the ratio of the cannel resistance of the transistor 161 to that of the transistor 162 by the current value of the push current IL2 in the drain-to-source path of the transistor 161. Since the tone designating current IDATA flows through the output sides of the current mirror circuits Mi to Mn, i.e., the drains of the transistors 162, these drains of the transistors 162 of the current mirror circuits Mi to Mn are equivalent to the current terminals CTi to CTn of the current source driver 3 of the first embodiment. That is, an arrangement obtained by combining the current mirror circuits Mi to Mn and current control driver 203 is equivalent to the current source driver 3 of the first embodiment . The relationship between the timings of the switching signals Φ and inv.Φ and the selection timings of the selection scan driver 5 and voltage supply driver 6 in this embodiment is the same as in the first embodiment. Also, the operation timings of the selection scan driver 5 and voltage supply driver 6 in the third embodiment are the same as in the first embodiment. Therefore, in the reset period TR of the ith row, the first transistors 21 of the pixel circuits Dl,l to Dm^n are ON in the third embodiment as well. Accordingly, the voltages of the pixel electrodes 51 of organic EL elements Ei i to Ei n, drains 21d of the first transistors 21 in the ith row, electrodes 24B of capacitors 24 in the ith row, sources 23s of the driving transistors 23 in the ith row, and the current lines Y]_ to Yn are set in a steady state, thereby removing the electric charges stored in these parasitic capacitances in the preceding selection period TgE- Consequently, the tone designating current IQATA can be rapidly and accurately written in the next selection period TgE- The data driving circuit 207 applies the reset voltage VR to the current lines Yi to Yn in the selection period TgE in the third embodiment as well. Therefore, the first transistor 21 has both the function of a switching element which loads the reset voltage VR into each of the pixel circuits D]_ to Dm n, and the function of a switching element which loads the tone designating current IQATA into each of the pixel circuits Di i to Dm n. Accordingly, the number of transistors necessary for the pixel circuits Di l to Dm n does not increase. When the organic EL elements Ei to Em n are formed on the same surface as the pixel circuits Di i to Dm n, therefore, the aperture ratio of the pixels Pi l to Pm n does not decrease. [Fourth Embodiment] FIG. 12 is a block diagram showing an organic EL display 301 according to the fourth embodiment to which the organic EL display of the present invention is applied. In FIG. 12, the same reference numerals and symbols as in the organic EL display 1 of the first embodiment denote the same parts in the organic EL display 301, and an explanation thereof will be omitted. Similar to the organic EL display 1, the organic
EL display 301 includes an organic EL display panel 2, scan driving circuit 9, and data driving circuit 307. The organic EL display panel 2 and scan driving circuit 9 are the same as the organic EL display panel 2 and scan driving circuit 9 of the third embodiment. The data driving circuit 307 is different from the data driving circuit 7 of the first embodiment. The data driving circuit 307 includes a current control driver 303, current mirror circuits Mi to Mn, switching elements Ki to Kn, and switching elements Wi to Wn as switches. The current control driver 303 has n current terminals GTi to GTn . An 8-bit digital tone image signal is input to the current control driver 303. This digital tone image signal loaded into the current control driver 303 is converted into an analog signal by an internal D/A converter of the current control driver 303. The current control driver 303 generates a push current IL3 having a current value corresponding to the analog image signal at the current terminals GTi to GTn. The current control driver 303 controls the current value of the push current IL3 at the current terminals GTi to GTn in each selection period T E of each row in accordance with the image signal, and holds the current value of the push current IL3 constant in a period from the end of each reset period TR to the end of the corresponding selection period Tg - The push current IL3 supplied by the current control driver 303 is larger than the tone designating current IoATA supplied by the current source driver 3 of the first embodiment, and proportional to a tone designating current IQATA which flows through a transistor 362 (to be described later) . The current mirror circuits Mi to Mi convert the push current IL3 which flows through the current terminals GTi to GTn into the tone designating current IDATA- Each of the current mirror circuits Mi to Mn has two transistors 361 and 362. In the current mirror circuit Mj , the gate of the transistor 361 is connected to the gate of the transistor 362, and the drain of the transistor 361 is connected to the current terminal and to the gates of the transistors 361 and 362. The drain of the transistor 362 is connected to a current line Yj . The sources of the transistors 361 and 362 are connected to a common voltage terminal 344. A constant voltage VQQ is applied to the voltage terminal 344. The level of the constant voltage VQQ is lower than a tone designating current reference voltage VLOW and reference voltage Vgg. When the reference voltage Vgg or tone designating current reference voltage VLO is 0 [V] as in the first embodiment, the constant voltage VQO is a negative voltage. The current value of the tone designating current IDATA is substantially a value obtained by multiplying the ratio of the cannel resistance of the transistor 362 to that of the transistor 361 by the current value of the push current IL3 in the drain-to-source path of the transistor 361. That is, an arrangement obtained by combining the current mirror circuits Mi to Mn and current control driver 303 is equivalent to the current source driver. The drains of the transistors or switching elements W]_ to Wn are connected to the current terminals GT_ to GTn and to the drains and gates of the transistors 361 of the current mirror circuits Mi to Mn. The sources of the switching elements W]_ to Wn are connected to the voltage terminal 344. The gates of the switching elements W]_ to Wn are connected to a switching signal input terminal 42. The switching elements Wi to Wn switch the application of the constant voltage VQQ to the drains of the transistors 361 of the current mirror circuits Mi to Mn. Note that the switching elements Wi to Wn may also be incorporated into the current control driver 303. The relationship between the timings of switching signals and the selection timings of a selection scan 71
driver 5 and voltage supply driver 6 in this embodiment is the same as in the first embodiment. In the reset period TR in the initial part of the selection period Tgg of the ith row, therefore, the transistors i to Wn are turned on, so the voltages of the sources and drains of the transistors 361 become equal to each other. Accordingly, after the reset period TR of the selection period TgE, the influence of the parasitic capacitances of the current mirror circuits Mi to Mn on the current lines Yi to Yn can be removed. In each of switching elements Ki to Kn, one of the drain and source is connected to a reset input terminal 41, the other of the drain and source is connected to a corresponding one of the current lines Yi to Yn, and the gate is connected to the switching signal input terminal 42. The switching elements Ki to Kn switch the application of the reset voltage VR to the current lines Yi to Yn. The reset voltage VR is set at 0 [V] . Note that on the opposite side of the connecting portion between each of the current lines Yi to Yn and the transistor 362, the other of the drain and source of a corresponding one of the switching elements Ki to Kn may also be connected to a corresponding one of the current lines Yi to Yn, and the switching elements Ki to Kn may also be formed on the organic EL display panel 2. In the reset period TR in the initial part of the selection period T E of the ith row, the switching elements Ki to Kn are turned on, so pixel electrodes 51 and the current lines Yi to Yn electrically conduct to the reset input terminal 41 to apply the grounded reset voltage VR. Therefore, immediately after the start of the reset period TR of the ith row, it is possible to remove the electric charges stored in the parasitic capacitances of the current lines Yi to Yn, the electric charges stored in the parasitic capacitances of the pixel electrodes 51, the electric charges stored in the parasitic capacitances of electrodes 24B of capacitors 24, and the electric charges stored in the parasitic capacitances of the sources of driving transistors 23. Accordingly, the tone designating current IQATA having a very small current value can be accurately and rapidly supplied. After the reset period TR, the switching elements Ki to Kn and Wi to Wn are turned off, and an electric current having a current value corresponding to the tone flows through the current terminals GTi to GTn of the current control driver 303. Consequently, the tone designating current ID TA modulated by the current mirror circuits Mi to Mn flow through the current lines Yi to Yn and driving transistor 23. The data driving circuit 307 applies the reset voltage VR to the current lines Yi to Yn in the selection period TgE in the fourth embodiment as well. Therefore, a first transistor 21 has both the function of a switching element which loads the reset voltage VR into each of the pixel circuits Di i to Dm n, and the function of a switching element which loads the tone designating current IpATA into each of the pixel circuits Di i to Dm n. Accordingly, the number of transistors necessary for the pixel circuits Di i to Dm n does not increase. When organic EL elements Ei i to Em n are formed on the same surface as the pixel circuits Di i to Dm n, therefore, the aperture ratio of the pixels Pi l to Pm n does not decrease. The present invention is not limited to the above embodiments, and various improvements and design changes can be made without departing from the spirit and scope of the present invention. For example, an organic EL element is used as a light-emitting element in each of the above embodiments. However, another light-emitting element having rectification characteristics may also be used. That is, it is also possible to use a light-emitting element in which no electric current flows if a reverse bias voltage is applied and an electric current flows if a forward bias voltage is applied, and which emits light at luminance corresponding to the current value of the flowing electric current. An example of the light-emitting element having rectification characteristics is an LED (Light-Emitting Diode) . In addition, the tone designating current reference voltage VLOW of the voltage supply driver 6 may also be positioned on the right side of the EL load border line corresponding to the maximum luminance tone shown in FIG. 4, provided that a portion or the whole of the tone designating current IoATA does not flow through the organic EL elements in the selection period Tgg.

Claims

C L A I M S 1. A display device comprising: a plurality of selection scan lines; a plurality of current lines; a selection scan driver which sequentially selects said plurality of selection scan lines in each selection period; a data driving circuit which applies a reset voltage to said plurality of current lines in a first part of the selection period, and supplies a designating current having a current value corresponding to an image signal to said plurality of current lines in a second part of the selection period after applying the reset voltage in the selection period; and a plurality of pixel circuits which are connected to said plurality of selection scan lines and said plurality of current lines, and supply a driving current having a current value corresponding to the current value of the designating current which flows through said plurality of current lines.
2. A device according to claim 1, wherein said data driving circuit comprises: a switch which switches to a state in which the reset voltage is applied to said plurality of current lines in the first part of the selection period; and ■ a current source driver which supplies the designating current having the current value corresponding to the image signal after the reset voltage is applied by the switch within the selection period.
3. A device according to claim 1, wherein In the selection period, each of said plurality of pixel circuits loads the designating current which flows through said plurality of current lines, and stores a level of a voltage converted in accordance with the current value of the designating current, and after the selection period, each of said plurality of pixel circuits shuts off the designating current which flows through said plurality of current lines, and supplies a driving current corresponding to the level of the voltage converted in accordance with the designating current.
4. A device according to any one of claims 1 to 3, further comprising a plurality of light-emitting elements which are arranged at intersections of said plurality of selection scan lines and said plurality of current lines, emit light at luminance corresponding to a current value of a driving current, and each have two electrodes one of which is connected to a corresponding one of said plurality of pixel circuits.
5. A device according to claim 4, wherein the reset voltage applied by the data driving circuit is set equal to or lower than a voltage of the other electrode of the light-emitting element.
6. A device according to claim 1, further comprising: a plurality of voltage supply lines; and a voltage supply driver which sequentially selects said plurality of voltage supply lines in synchronism with the sequential selection of said plurality of selection scan lines by the selection scan driver.
7. A device according to claim 6, wherein each of said pixel circuits comprises: a first transistor having a gate connected to the selection scan line, and a drain and source one of which is connected to the current line; a second transistor having a gate connected to the selection scan line, and a drain and source one of which is connected to the voltage supply line; a driving transistor having a gate connected to the other of the drain and source of the second transistor, and a drain and source one of which is connected to the voltage supply line, and the other of which is connected to the other of the drain and source of the first transistor; and a capacitor which stores a gate-to-one of source and drain voltage of the driving transistor by holding the voltage.
8. A device according to claim 7, which further comprises a plurality of light-emitting elements which are arranged at intersections of said plurality of selection scan lines and said plurality of current lines, emit light at luminance corresponding to a current value of a driving current, and each have two electrodes one of which is connected to a corresponding one of said plurality pixel circuits, and in which the other electrode of the light-emitting element is connected to the other of the drain and source of the driving transistor.
9. A device according to claim 8, wherein in the selection period, the first transistor supplies the designating current from the voltage supply line to the current line via the drain-to-source path of the driving transistor, the driving transistor converts the current value of the designating current into a level of a gate-to-one of source and drain voltage, and the capacitor stores the level of the converted voltage, and after the selection period, the driving transistor supplies, to the light-emitting element, a driving current having a current value corresponding to the level of the gate-to- one of source and drain voltage stored by the capacitor.
10. A device according to claim 8, wherein the voltage applied to the voltage supply line by the voltage supply driver in the selection period is set not higher than a voltage of the other electrode of the light-emitting element, and the voltage applied to the voltage supply line by the voltage supply driver after the selection period is set higher than the voltage of the other electrode of the light-emitting element.
11. A display device comprising: a plurality of selection scan lines; a plurality of current lines; a plurality of light-emitting elements which are arranged at intersections of said plurality of selection scan lines and said plurality of current lines, and emit light at luminance corresponding to a current value of a driving current; a selection scan driver which sequentially select said plurality of selection scan lines in each selection period; a data driving circuit which applies a reset voltage to said plurality of current lines in a first part of the selection period, and supplies a designating current having a current value corre- sponding to an image signal to said plurality of current lines in a second part of the selection period after applying the reset voltage in the selection period; and a plurality of pixel circuits which are connected to said plurality of selection scan lines and said plurality of current lines, and electrically connect said plurality of current lines and said plurality of light-emitting elements to each other in the selection period.
12. A data driving circuit of an active matrix driving display device comprising a plurality of light-emitting elements connected to a plurality of selection scan lines and a plurality of current lines, a selection scan driver which sequentially selects said plurality of selection scan lines in each selection period, and a plurality of pixel circuits connected to said plurality of light-emitting elements, wherein a reset voltage is applied to said plurality of current lines in a first part of the selection period, and a designating current having a current value corresponding to an image signal is supplied to said plurality of current lines in a second part of the selection period after the first part of the selection period.
13. A circuit according to claim 12, further comprising: a switch which switches to a state in which the reset voltage is applied to said plurality of current lines in the first part of the selection period; and a current source driver which, after the reset voltage is applied by the switch in the selection period, supplies the designating current having the current value corresponding to the image signal to said plurality of current lines.
14. A display panel driving method comprising: a selection step of sequentially selecting a plurality of selection scan lines of a display panel comprising a plurality of pixel circuits connected to the plurality of selection scan lines and a plurality of current lines, and a plurality of light-emitting elements which are arranged at intersections of the plurality of selection scan lines and the plurality of current lines, each of the light-emitting elements emits light at luminance corresponding to a current value of a current flowing the current line; and a reset step of applying a reset voltage to the plurality of current lines in an initial part of a period in which each of the plurality of selection scan lines is selected.
15. A method according to claim 14, further comprising: a designating current supply step of, after the reset step, supplying designating currents having current value corresponding to an image signal to the plurality of current lines, and storing, in the plurality of pixel circuits, the current value of the designating currents flowing through the plurality of current lines; and a light emission step of, after the designating current supply step, allowing the plurality of pixel circuits to supply, to the plurality of light-emitting elements, driving currents having current value corresponding to the stored current value of the designating currents.
PCT/JP2005/000731 2004-01-16 2005-01-14 Display device, data driving circuit, and display panel driving method WO2005069260A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05703959A EP1714266A2 (en) 2004-01-16 2005-01-14 Display device, data driving circuit, and display panel driving method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004-009146 2004-01-16
JP2004009146A JP4203656B2 (en) 2004-01-16 2004-01-16 Display device and display panel driving method

Publications (2)

Publication Number Publication Date
WO2005069260A2 true WO2005069260A2 (en) 2005-07-28
WO2005069260A3 WO2005069260A3 (en) 2007-02-08

Family

ID=34747204

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/000731 WO2005069260A2 (en) 2004-01-16 2005-01-14 Display device, data driving circuit, and display panel driving method

Country Status (7)

Country Link
US (1) US7499042B2 (en)
EP (1) EP1714266A2 (en)
JP (1) JP4203656B2 (en)
KR (1) KR100675551B1 (en)
CN (1) CN100520891C (en)
TW (1) TWI286303B (en)
WO (1) WO2005069260A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412291B2 (en) 2011-05-13 2016-08-09 Semiconductor Energy Laboratory Co., Ltd. Display device
EP3413295A4 (en) * 2016-01-26 2019-08-14 Boe Technology Group Co. Ltd. Pixel circuit, driving method therefor, display panel, and display device

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003195810A (en) * 2001-12-28 2003-07-09 Casio Comput Co Ltd Driving circuit, driving device and driving method for optical method
JP3918642B2 (en) * 2002-06-07 2007-05-23 カシオ計算機株式会社 Display device and driving method thereof
JP4610843B2 (en) * 2002-06-20 2011-01-12 カシオ計算機株式会社 Display device and driving method of display device
JP4103500B2 (en) * 2002-08-26 2008-06-18 カシオ計算機株式会社 Display device and display panel driving method
AU2003276706A1 (en) * 2002-10-31 2004-05-25 Casio Computer Co., Ltd. Display device and method for driving display device
JP4566528B2 (en) * 2002-12-05 2010-10-20 シャープ株式会社 Display device
JP3952965B2 (en) * 2003-02-25 2007-08-01 カシオ計算機株式会社 Display device and driving method of display device
KR100742063B1 (en) * 2003-05-26 2007-07-23 가시오게산키 가부시키가이샤 Electric current generation supply circuit and display device
JP4304585B2 (en) * 2003-06-30 2009-07-29 カシオ計算機株式会社 CURRENT GENERATION SUPPLY CIRCUIT, CONTROL METHOD THEREOF, AND DISPLAY DEVICE PROVIDED WITH THE CURRENT GENERATION SUPPLY CIRCUIT
JP4103079B2 (en) 2003-07-16 2008-06-18 カシオ計算機株式会社 CURRENT GENERATION SUPPLY CIRCUIT, ITS CONTROL METHOD, AND DISPLAY DEVICE PROVIDED WITH CURRENT GENERATION SUPPLY CIRCUIT
JP4665419B2 (en) * 2004-03-30 2011-04-06 カシオ計算機株式会社 Pixel circuit board inspection method and inspection apparatus
TWI264694B (en) * 2005-05-24 2006-10-21 Au Optronics Corp Electroluminescent display and driving method thereof
TWI298599B (en) * 2006-03-03 2008-07-01 Au Optronics Corp Organic light emitting display, panel and driving device thereof
US7616179B2 (en) * 2006-03-31 2009-11-10 Canon Kabushiki Kaisha Organic EL display apparatus and driving method therefor
TW200746022A (en) 2006-04-19 2007-12-16 Ignis Innovation Inc Stable driving scheme for active matrix displays
JP4240059B2 (en) 2006-05-22 2009-03-18 ソニー株式会社 Display device and driving method thereof
JP5275551B2 (en) * 2006-06-02 2013-08-28 富士フイルム株式会社 CURRENT CONTROL TYPE DRIVE CIRCUIT AND DISPLAY DEVICE
US8330492B2 (en) 2006-06-02 2012-12-11 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
JP5114889B2 (en) * 2006-07-27 2013-01-09 ソニー株式会社 Display element, display element drive method, display device, and display device drive method
EP1895545B1 (en) 2006-08-31 2014-04-23 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
JP5467484B2 (en) * 2007-06-29 2014-04-09 カシオ計算機株式会社 Display drive device, drive control method thereof, and display device including the same
TWI386904B (en) * 2008-05-12 2013-02-21 Chimei Innolux Corp Flat display
JP4544355B2 (en) * 2008-08-04 2010-09-15 ソニー株式会社 Pixel circuit, driving method thereof, display device, and driving method thereof
JP5346520B2 (en) * 2008-08-13 2013-11-20 株式会社ジャパンディスプレイ Image display device
KR20100060611A (en) * 2008-11-28 2010-06-07 삼성전자주식회사 Output driving circuit for use in output buffer for source driver integrated circuit
JP2010145709A (en) * 2008-12-18 2010-07-01 Hitachi Displays Ltd Image display device
WO2011036987A1 (en) 2009-09-24 2011-03-31 Semiconductor Energy Laboratory Co., Ltd. Display device
US8944632B2 (en) * 2010-10-15 2015-02-03 Douglas Tveit LED lighting system and method for external surfaces
JP2014029438A (en) * 2012-07-31 2014-02-13 Sony Corp Display device, drive circuit, and electronic apparatus
KR101975489B1 (en) * 2012-09-10 2019-05-08 삼성디스플레이 주식회사 Display device and driving method thereof
JP6433716B2 (en) * 2014-08-19 2018-12-05 ラピスセミコンダクタ株式会社 Display device and image data signal transmission processing method
CN105810143B (en) * 2014-12-29 2018-09-28 昆山工研院新型平板显示技术中心有限公司 A kind of data drive circuit and its driving method and organic light emitting display
CN108877669A (en) * 2017-05-16 2018-11-23 京东方科技集团股份有限公司 A kind of pixel circuit, driving method and display device
US10624190B1 (en) * 2019-01-21 2020-04-14 Mikro Mesa Technology Co., Ltd. Micro light-emitting diode driving circuit and method for driving the same
CN114038396B (en) * 2021-08-17 2022-10-21 重庆康佳光电技术研究院有限公司 Drive compensation circuit, display device and drive method of display unit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1372136A1 (en) * 2002-06-12 2003-12-17 Seiko Epson Corporation Scan driver and a column driver for active matrix display device and corresponding method
WO2004001714A1 (en) * 2002-06-20 2003-12-31 Casio Computer Co., Ltd. Light emitting element display apparatus and driving method thereof

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2506840B2 (en) 1987-11-09 1996-06-12 松下電器産業株式会社 Inspection method for active matrix array
JP3442449B2 (en) * 1993-12-25 2003-09-02 株式会社半導体エネルギー研究所 Display device and its driving circuit
CN1176732A (en) * 1995-12-30 1998-03-18 卡西欧计算机株式会社 Display device for performing display operation in accordance with signal light and driving method therefor
TW375696B (en) * 1996-06-06 1999-12-01 Toshiba Corp Display device
JP4147594B2 (en) * 1997-01-29 2008-09-10 セイコーエプソン株式会社 Active matrix substrate, liquid crystal display device, and electronic device
CN100533528C (en) * 1997-02-17 2009-08-26 精工爱普生株式会社 Display device
US6229506B1 (en) * 1997-04-23 2001-05-08 Sarnoff Corporation Active matrix light emitting diode pixel structure and concomitant method
US6023259A (en) * 1997-07-11 2000-02-08 Fed Corporation OLED active matrix using a single transistor current mode pixel design
JP3765918B2 (en) 1997-11-10 2006-04-12 パイオニア株式会社 Light emitting display and driving method thereof
WO1999028896A1 (en) * 1997-11-28 1999-06-10 Seiko Epson Corporation Drive circuit for electro-optic apparatus, method of driving the electro-optic apparatus, electro-optic apparatus, and electronic apparatus
GB9812742D0 (en) * 1998-06-12 1998-08-12 Philips Electronics Nv Active matrix electroluminescent display devices
JP2000163014A (en) * 1998-11-27 2000-06-16 Sanyo Electric Co Ltd Electroluminescence display device
JP3686769B2 (en) 1999-01-29 2005-08-24 日本電気株式会社 Organic EL element driving apparatus and driving method
TW526455B (en) * 1999-07-14 2003-04-01 Sony Corp Current drive circuit and display comprising the same, pixel circuit, and drive method
EP1129446A1 (en) 1999-09-11 2001-09-05 Koninklijke Philips Electronics N.V. Active matrix electroluminescent display device
CN1199144C (en) 1999-10-18 2005-04-27 精工爱普生株式会社 Display
US6750835B2 (en) * 1999-12-27 2004-06-15 Semiconductor Energy Laboratory Co., Ltd. Image display device and driving method thereof
TW582011B (en) * 2000-01-06 2004-04-01 Toshiba Corp Array substrate and method of inspecting the same
KR100566813B1 (en) * 2000-02-03 2006-04-03 엘지.필립스 엘시디 주식회사 Circuit for Electro Luminescence Cell
GB0008019D0 (en) 2000-03-31 2000-05-17 Koninkl Philips Electronics Nv Display device having current-addressed pixels
US6611108B2 (en) * 2000-04-26 2003-08-26 Semiconductor Energy Laboratory Co., Ltd. Electronic device and driving method thereof
TW493153B (en) * 2000-05-22 2002-07-01 Koninkl Philips Electronics Nv Display device
KR100568016B1 (en) * 2000-07-07 2006-04-07 세이코 엡슨 가부시키가이샤 Current sampling circuit for organic electroluminescent display
KR100710279B1 (en) * 2000-07-15 2007-04-23 엘지.필립스 엘시디 주식회사 Electro Luminescence Panel
WO2002011115A1 (en) * 2000-07-28 2002-02-07 Nichia Corporation Drive circuit of display and display
JP3736399B2 (en) * 2000-09-20 2006-01-18 セイコーエプソン株式会社 Drive circuit for active matrix display device, electronic apparatus, drive method for electro-optical device, and electro-optical device
JP2003195815A (en) 2000-11-07 2003-07-09 Sony Corp Active matrix type display device and active matrix type organic electroluminescence display device
JP4929431B2 (en) 2000-11-10 2012-05-09 Ｎｌｔテクノロジー株式会社 Data line drive circuit for panel display device
JP3950988B2 (en) * 2000-12-15 2007-08-01 エルジー フィリップス エルシーディー カンパニー リミテッド Driving circuit for active matrix electroluminescent device
JP2002215095A (en) * 2001-01-22 2002-07-31 Pioneer Electronic Corp Pixel driving circuit of light emitting display
SG111928A1 (en) * 2001-01-29 2005-06-29 Semiconductor Energy Lab Light emitting device
US6661180B2 (en) * 2001-03-22 2003-12-09 Semiconductor Energy Laboratory Co., Ltd. Light emitting device, driving method for the same and electronic apparatus
JP4027614B2 (en) * 2001-03-28 2007-12-26 株式会社日立製作所 Display device
KR100593276B1 (en) * 2001-06-22 2006-06-26 탑폴리 옵토일렉트로닉스 코포레이션 Oled current drive pixel circuit
US6667580B2 (en) * 2001-07-06 2003-12-23 Lg Electronics Inc. Circuit and method for driving display of current driven type
JP2003043998A (en) * 2001-07-30 2003-02-14 Pioneer Electronic Corp Display device
JP5636147B2 (en) 2001-08-28 2014-12-03 パナソニック株式会社 Active matrix display device
JP4650601B2 (en) * 2001-09-05 2011-03-16 日本電気株式会社 Current drive element drive circuit, drive method, and image display apparatus
JP2003195810A (en) 2001-12-28 2003-07-09 Casio Comput Co Ltd Driving circuit, driving device and driving method for optical method
GB2386462A (en) * 2002-03-14 2003-09-17 Cambridge Display Tech Ltd Display driver circuits
JP3918642B2 (en) * 2002-06-07 2007-05-23 カシオ計算機株式会社 Display device and driving method thereof
JP3972359B2 (en) * 2002-06-07 2007-09-05 カシオ計算機株式会社 Display device
JP4103500B2 (en) * 2002-08-26 2008-06-18 カシオ計算機株式会社 Display device and display panel driving method
US6960680B2 (en) * 2003-01-08 2005-11-01 Rhodia Chirex, Inc. Manufacture of water-soluble β-hydroxynitriles
JP4103957B2 (en) 2003-01-31 2008-06-18 東北パイオニア株式会社 Active drive pixel structure and inspection method thereof
JP3952965B2 (en) * 2003-02-25 2007-08-01 カシオ計算機株式会社 Display device and driving method of display device
JP4665419B2 (en) * 2004-03-30 2011-04-06 カシオ計算機株式会社 Pixel circuit board inspection method and inspection apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1372136A1 (en) * 2002-06-12 2003-12-17 Seiko Epson Corporation Scan driver and a column driver for active matrix display device and corresponding method
WO2004001714A1 (en) * 2002-06-20 2003-12-31 Casio Computer Co., Ltd. Light emitting element display apparatus and driving method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412291B2 (en) 2011-05-13 2016-08-09 Semiconductor Energy Laboratory Co., Ltd. Display device
US9886905B2 (en) 2011-05-13 2018-02-06 Semiconductor Energy Laboratory Co., Ltd. Display device
US10395593B2 (en) 2011-05-13 2019-08-27 Semiconductor Energy Laboratory Co., Ltd. Display device
US11081048B2 (en) 2011-05-13 2021-08-03 Semiconductor Energy Laboratory Co., Ltd. Display device
EP3413295A4 (en) * 2016-01-26 2019-08-14 Boe Technology Group Co. Ltd. Pixel circuit, driving method therefor, display panel, and display device
US10446082B2 (en) 2016-01-26 2019-10-15 Boe Technology Group Co., Ltd. OLED pixel circuit and driving method for improving light emitting efficiency

Also Published As

Publication number Publication date
WO2005069260A3 (en) 2007-02-08
CN101076846A (en) 2007-11-21
KR100675551B1 (en) 2007-01-30
KR20050107455A (en) 2005-11-11
JP4203656B2 (en) 2009-01-07
CN100520891C (en) 2009-07-29
TWI286303B (en) 2007-09-01
EP1714266A2 (en) 2006-10-25
TW200535766A (en) 2005-11-01
US20050157581A1 (en) 2005-07-21
JP2005202209A (en) 2005-07-28
US7499042B2 (en) 2009-03-03

Similar Documents

Publication Publication Date Title
US7499042B2 (en) Display device, data driving circuit, and display panel driving method
CA2463486C (en) Display device and display device driving method
JP4610843B2 (en) Display device and driving method of display device
KR101142994B1 (en) Display device and driving method thereof
TWI413066B (en) Display device, method of laying out light emitting elements, and electronic device
JP3918642B2 (en) Display device and driving method thereof
KR20060054603A (en) Display device and driving method thereof
KR20050121379A (en) Display device and driving method thereof
US20060244687A1 (en) Active matrix display device
JP3952965B2 (en) Display device and driving method of display device
EP2195805A1 (en) Pixel circuit
TW201207814A (en) Display device and electronic apparatus
TW201037662A (en) Display device, display device drive method, and electronic apparatus
US20130127819A1 (en) Display device, method of laying out wiring in display device, and electronic device
US20030020335A1 (en) Electroluminescence display apparatus for displaying gray scales
WO2004088626A1 (en) Active matrix display devices with modelling circuit located outside the display area for compensating threshold variations of the pixel drive transistor
WO2006054189A1 (en) Active matrix display devices
JP4486335B2 (en) Display device and display panel driving method
KR101240658B1 (en) Display device and driving method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 2005703959

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020057015719

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 20058000778

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 1020057015719

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

WWP Wipo information: published in national office

Ref document number: 2005703959

Country of ref document: EP

WWG Wipo information: grant in national office

Ref document number: 1020057015719

Country of ref document: KR