WO2005076794A2 - Die encapsulation using a porous carrier - Google Patents
Die encapsulation using a porous carrier Download PDFInfo
- Publication number
- WO2005076794A2 WO2005076794A2 PCT/US2005/001529 US2005001529W WO2005076794A2 WO 2005076794 A2 WO2005076794 A2 WO 2005076794A2 US 2005001529 W US2005001529 W US 2005001529W WO 2005076794 A2 WO2005076794 A2 WO 2005076794A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- porous carrier
- adhesive
- integrated circuit
- carrier
- circuit die
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates in general to integrated circuit (IC) die encapsulation.
- Carriers are utilized for supporting IC die during encapsulation processes in the manufacture of packaged integrated circuits.
- IC die are attached to a carrier with tape or other types of attaching structures.
- a mold is placed around the IC die where encapsulate is then applied to the die with the tape defining the bottom surface of the mold outside of the die.
- the carrier is removed from the encapsulated structure by heating the tape to soften the adhesives of the tape. The tape is then removed from the encapsulated structure.
- the adhesive of the tape may be degraded by applying Ultra Violet (UN) radiation to the tape.
- UN Ultra Violet
- the UN degradable adhesive on the tape may not function adequately after being subjected to the curing temperatures of the encapsulation processes.
- Figure 1 is a cross sectional view of one embodiment of a carrier according to the present invention.
- Figure 2 is a cross sectional view of one embodiment of a carrier with adhesive tape applied on top thereof during a stage in the manufacture of a packaged integrated circuit according to the present invention.
- Figure 3 is a cross sectional view of one embodiment of a carrier, adhesive tape, and an encapsulant mold during another stage in the manufacture of a packaged integrated circuit according to the present invention.
- Figure 4 is a cross sectional view of one embodiment of a carrier, adhesive tape, an encapsulant mold, and IC die during another stage in the manufacture of a packaged integrated circuit according to the present invention.
- Figure 5 is a cross sectional view of one embodiment of a carrier, adhesive tape, an encapsulant mold, and an encapsulated structure during another stage in the manufacture of a packaged integrated circuit according to the present invention.
- Figure .6 is a cross sectional view of one embodiment of a carrier, adhesive tape, an encapsulant mold, and an encapsulated structure during another stage in the manufacture of a packaged integrated circuit according to the present invention.
- Figure 7 is a cross sectional view of one embodiment of adhesive tape, an encapsulant mold, and an encapsulated structure after the removal of the carrier during another stage in the manufacture of a packaged integrated circuit according to the present invention.
- Figure 8 is a cross sectional view of one embodiment of an encapsulant mold and an encapsulated structure after the removal of tape during another stage in the manufacture of a packaged integrated circuit according to the present invention.
- Figure 9 is a cross sectional view of one embodiment of an encapsulated structure after the removal of the encapsulant mold during another stage in the manufacture of a packaged integrated circuit according to the present invention.
- the use of the same reference symbols in different drawings indicates identical items unless otherwise noted.
- Figures 1-9 show one embodiment of various stages of a process for encapsulating an IC die with the use of a porous carrier to allow for solvent to pass through the carrier to reduce the adhesive strength of an adhesive structure for the removal of a carrier from an encapsulated structure.
- FIG 1 is a cross sectional view of carrier 101 prior to the application of a tape for an encapsulating process.
- Carrier 101 is porous in that has pores that allow a solvent to pass through from one side of the carrier to another side.
- carrier 101 is made of a composite material of aluminum oxide embedded in a glass matrix.
- carrier 101 may be made with other material such as e.g. metal, ceramics, glass, plastics, polymer or a combination thereof, where such materials are made to have a continuous open porosity.
- the carrier is made of a material that can withstand temperatures of the encapsulation process (e.g. 150 C).
- carrier 101 has pores with a .2 micron diameter pore size and a coefficient of thermal expansion (CTE) of 8 parts per million (ppm).
- the pore size of carrier 101 may range from .02 microns up to 30 microns. In other embodiments, the pore size may be bigger. However, in some embodiments, a larger pore size may affect the smoothness of the surface of the carrier beyond a smoothness level that is desired. In one embodiment, the desired smoothness of the surface of the carrier is dependent upon the type of adhesive structure utilized for attachment of IC die. With some embodiments, the adhesive structure may be applied as a planar layer thereby allowing for a carrier to have larger pore sizes.
- a carrier with pores of a smaller pore size may be used. However, with a smaller pore size, a reduced amount of solvent passes thought the carrier. With some embodiments, the time needed for reducing the strength of the adhesive structure is dependent upon the amount of solvent passing through the carrier. Accordingly, with some embodiments, carriers with an open continuous porosity of a .02 micron diameter pour size or greater are utilized depending upon the amount of solvent desired to be passed through. Also, utilizing a carrier with pores of a smaller size may affect the reusability of the carrier in that the small pores may become clogged.
- carrier 101 may have CTE of other values.
- the CTE of carrier 101 is less than the CTE of an encapsulant used for encapsulating the IC die.
- the encapsulant has a CTE ranging from .5- 20 ppm.
- tape 203 is applied to the top surface of carrier 101.
- carrier 101 Prior to applying tape 203, carrier 101 is cleaned e.g. by baking and scrubbing.
- tape 203 is a two sided adhesive tape.
- the die side (the top side in the view of Figure 2) of tape 203 has a silicone adhesive material with a thickness of 50 microns, but may be of other thicknesses (e.g. 12-100 microns) and/or of other adhesive materials (e.g. acrylic or organic) in other embodiments..
- the carrier side (the bottom side in the view of Figure 2) of tape 203 has a silicone adhesive material with a thickness of 75 microns.
- the carrier side adhesive material may be of other types of adhesive material (e.g. acrylic or organic) and/or may be of other thicknesses.
- the thickness of the carrier side adhesive material should be thick enough to fill in pores or other voids in the top side of carrier 101 so as to "planarize" the top surface of carrier 101.
- the maximum thickness of the carrier side adhesive material is limited by the ability to release the carrier from tape 203 with solvent.
- the thickness of the carrier side adhesive material may range from 12-100 microns, but may be of other thicknesses in other embodiments.
- the tape has an adhesive material on the die side that is greater than 30 microns and an adhesive material on the carrier side that is greater than 50 microns.
- the silicone adhesive may have additives to increase or decrease the silicone strength.
- the die side and carrier side adhesive materials are separated by a tape carrier (e.g. polyester or polyamide).
- Figure 3 shows a cross sectional view of carrier 101 after an encapsulant mold is placed on top of tape 203.
- Mold 305 has an opening 307 for exposing the middle portion of tape 203.
- integrated circuit die 403 and 405 are placed on tape 203 in opening 307 in predefined locations.
- multiple die are placed in an array configuration (e.g. 4 x 6, 6 x 6, or 8 x 8) on tape 203.
- the die are placed on tape 203 by a standard pick and place method, but may be placed on tape 203 by other methods.
- die 403 and 405 include integrated circuits built on a semiconductor wafer which was subsequently singulated into separate die.
- die 403 and 405 have a flip chip configuration and are placed active side down on tape 203, wherein the bond pads (not show) are located on the bottom sides of die 403 and 405 relative to the view shown in Figure 4.
- an encapsulant material is dispensed (e.g. with syringe and robotic needle) into opening 307 to form an encapsulant 503 that encapsulates die 403 and 405 in an encapsulated structure 505.
- encapsulant 503 may be formed by other encapsulating processes such as e.g. screen print, extrusion coating, transfer mold, ejection mold, glob top, or other encapsulating processes.
- the bottom portion of carrier 101 is placed in a solvent bath 603. Solvent from solvent bath 603 is absorbed up through the carrier via a capillary action where it contacts the carrier side adhesive material of tape 203. The solvent breaks down the adhesive strength of the carrier side adhesive material of tape 203. In one embodiment where the solvent is acetone and the adhesive material is a silicone adhesive, the solvent softens the adhesive property of the silicone adhesive. In one embodiment, the bottom portion of carrier 101 is placed in bath 603 for about 5 minutes before carrier 101 separates from tape 203. In other embodiments, a greater portion of the carrier may be submerged in bath 603. In some embodiments, the entire carrier/mold/encapsulated structure may be submerged in bath 603.
- the carrier removal process may be performed at room temperature, or in some embodiments, at least at temperatures below the transition temperature (T g ) of the encapsulant.
- T g transition temperature
- the carrier may be removed from the encapsulated structure 505 without causing die 403 and 405 to drift within encapsulated structure 505.
- the transition temperature of encapsulant 503 is about 140 C.
- other types of encapsulant material may have a T g ranging from 90 C to 200 C.
- Figure 7 shows a cross sectional view of mold 305, encapsulated structure 505, and tape 203 after carrier 101 has been removed.
- tape 203 is pulled from encapsulated structure 505 and mold 305.
- mold 305 is removed from encapsulated structure 505.
- structure 505 is subject to further buildup processes (e.g. dielectric and metal interconnect processing) on the active side of the die to form interconnect structures (not shown).
- Encapsulated structure 505 is then singulated into a plurality of packaged ICs.
- each packaged IC includes one IC die (e.g. 403).
- each packaged IC may include multiple die (e.g. in stacked or side by side configurations).
- package ICs of other embodiments may include stand alone devices (e.g. transistors, filters, capacitors, amplifiers) that are encapsulated in the encapsulant (e.g. 503). These additional items by be placed on tape 203 prior to encapsulation.
- entire embedded systems e.g. multichip modules, RF systems, or other wireless or information processing systems may be included in a packaged IC.
- a package substrate may be located between tape 203 and the IC die (e.g. 405) with, in some embodiments, the package substrate defining the bottom portion of the encapsulant.
- the IC die are mounted to the packaged substrate, and then the package substrate is placed in opening 307.
- the package substrate is first placed on tape 203 in opening 307 and then the IC die are placed on the substrate.
- the die may be placed on the packaged substrate active side up wherein wire bonds are attached to bond pads on the active side and bond pads on the package substrate prior to encapsulation.
- tape 203 may be used in place of tape 203.
- two layers of tape may be used for attaching an integrated circuit die.
- One layer of tape would have adhesive material on two sides and the other layer would have adhesive on only one side.
- photo resist or other types of adhesives may be used as an adhesive structure for attaching the die to the carrier.
- a first layer of photo resist (not shown) would be applied to the top surface of carrier 101.
- a second layer of photo resist is applied on the cured layer of photo resist.
- the IC die are then placed on the second layer of photo resist. Afterwards, the second layer of photo resist is cured.
- a dry film photo resist or other adhesive may be used where only one layer is used for attaching the die to the carrier.
- An example of one such adhesive is RISTON as sold byDUPONT.
- acetone or N- Methyl 2-Pyn-olidone may be used as a solvent that dissolves the photo resist or adhesive layer(s) (e.g. as when the bottom portion of carrier 101 is placed in a solvent bath).
- NMP N- Methyl 2-Pyn-olidone
- other types of adhesive structures may be used including, e.g., other types of adhesive materials or other types of photo resist materials.
- the adhesive structure is able to withstand curing temperatures for curing the encapsulant.
- a method in one aspect of the invention, includes providing a porous carrier, providing an adhesive structure overlying the porous carrier, and placing a first integrated circuit die over the adhesive structure. The method also includes encapsulating the first integrated circuit die to form an encapsulated structure and separating the porous carrier from the encapsulated structure.
- a method in another aspect of the invention, includes providing a porous carrier, adhering an adhesive structure to the porous carrier, and placing at least one integrated circuit die over the adhesive structure. The method also includes encapsulating the at least one integrated circuit die to form an encapsulated structure and removing the porous carrier from the encapsulated structure. The removing includes using a solvent that is passed through the porous carrier to reduce adhesive strength between the adhesive structure and the porous carrier.
- a method in another aspect of the invention, includes providing a reusable porous carrier including pores with a pore size diameter of at least 0.02 microns, adhering an adhesive structure to the reusable porous carrier, and placing a plurality of integrated circuit die in an array configuration over the adhesive structure.
- the method also includes encapsulating the plurality of integrated circuit die to form an encapsulated structure and separating the reusable porous carrier from the encapsulated structure. The separating comprises using a solvent that is passed through the porous carrier to reduce adhesive strength between the adhesive structure and the reusable porous carrier.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006553132A JP4555835B2 (en) | 2004-02-09 | 2005-01-12 | Die encapsulation using porous carrier |
EP05705847A EP1721332A2 (en) | 2004-02-09 | 2005-01-12 | Die encapsulation using a porous carrier |
CN2005800043966A CN1918702B (en) | 2004-02-09 | 2005-01-12 | Die encapsulation using a porous carrier |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/774,977 | 2004-02-09 | ||
US10/774,977 US7015075B2 (en) | 2004-02-09 | 2004-02-09 | Die encapsulation using a porous carrier |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/837,153 Continuation-In-Part US20050244365A1 (en) | 2004-05-03 | 2004-05-03 | Methods, compositions, formulations, and uses of cellulose and acrylic-based polymers |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/592,479 Continuation-In-Part US20070148124A1 (en) | 2004-05-03 | 2006-11-03 | Cellulose and acrylic based polymers and the use thereof for the treatment of infectious diseases |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005076794A2 true WO2005076794A2 (en) | 2005-08-25 |
WO2005076794A3 WO2005076794A3 (en) | 2006-01-19 |
Family
ID=34827103
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/001529 WO2005076794A2 (en) | 2004-02-09 | 2005-01-12 | Die encapsulation using a porous carrier |
Country Status (6)
Country | Link |
---|---|
US (1) | US7015075B2 (en) |
EP (1) | EP1721332A2 (en) |
JP (1) | JP4555835B2 (en) |
CN (1) | CN1918702B (en) |
TW (1) | TWI389221B (en) |
WO (1) | WO2005076794A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8963314B2 (en) | 2008-06-26 | 2015-02-24 | Nxp B.V. | Packaged semiconductor product and method for manufacture thereof |
Families Citing this family (86)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930256B1 (en) | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
US9691635B1 (en) | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US7633765B1 (en) | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US7548430B1 (en) | 2002-05-01 | 2009-06-16 | Amkor Technology, Inc. | Buildup dielectric and metallization process and semiconductor package |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US11081370B2 (en) | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
US10811277B2 (en) | 2004-03-23 | 2020-10-20 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US20070212813A1 (en) * | 2006-03-10 | 2007-09-13 | Fay Owen R | Perforated embedded plane package and method |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US8137417B2 (en) | 2006-09-29 | 2012-03-20 | Semiconductor Energy Laboratory Co., Ltd. | Peeling apparatus and manufacturing apparatus of semiconductor device |
TWI570900B (en) | 2006-09-29 | 2017-02-11 | 半導體能源研究所股份有限公司 | Method for manufacturing semiconductor device |
US7550857B1 (en) | 2006-11-16 | 2009-06-23 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US7588951B2 (en) * | 2006-11-17 | 2009-09-15 | Freescale Semiconductor, Inc. | Method of packaging a semiconductor device and a prefabricated connector |
US7476563B2 (en) | 2006-11-17 | 2009-01-13 | Freescale Semiconductor, Inc. | Method of packaging a device using a dielectric layer |
US7807511B2 (en) | 2006-11-17 | 2010-10-05 | Freescale Semiconductor, Inc. | Method of packaging a device having a multi-contact elastomer connector contact area and device thereof |
US7696016B2 (en) * | 2006-11-17 | 2010-04-13 | Freescale Semiconductor, Inc. | Method of packaging a device having a tangible element and device thereof |
US20080182363A1 (en) * | 2007-01-31 | 2008-07-31 | Freescale Semiconductor, Inc. | Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer |
TWI360207B (en) * | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
US7802359B2 (en) * | 2007-12-27 | 2010-09-28 | Freescale Semiconductor, Inc. | Electronic assembly manufacturing method |
US8609471B2 (en) * | 2008-02-29 | 2013-12-17 | Freescale Semiconductor, Inc. | Packaging an integrated circuit die using compression molding |
US7741151B2 (en) * | 2008-11-06 | 2010-06-22 | Freescale Semiconductor, Inc. | Integrated circuit package formation |
JP5586920B2 (en) * | 2008-11-20 | 2014-09-10 | 株式会社半導体エネルギー研究所 | Method for manufacturing flexible semiconductor device |
US7960827B1 (en) | 2009-04-09 | 2011-06-14 | Amkor Technology, Inc. | Thermal via heat spreader package and method |
US8623753B1 (en) | 2009-05-28 | 2014-01-07 | Amkor Technology, Inc. | Stackable protruding via package and method |
US8222538B1 (en) | 2009-06-12 | 2012-07-17 | Amkor Technology, Inc. | Stackable via package and method |
TWI456715B (en) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | Chip package structure and manufacturing method thereof |
TWI466259B (en) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | Semiconductor package, manufacturing method thereof and manufacturing method for chip-redistribution encapsulant |
TWI405306B (en) * | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | Semiconductor package, manufacturing method thereof and chip-redistribution encapsulant |
US8471154B1 (en) | 2009-08-06 | 2013-06-25 | Amkor Technology, Inc. | Stackable variable height via package and method |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US20110084372A1 (en) * | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US8378466B2 (en) * | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US8327532B2 (en) * | 2009-11-23 | 2012-12-11 | Freescale Semiconductor, Inc. | Method for releasing a microelectronic assembly from a carrier substrate |
TWI497679B (en) * | 2009-11-27 | 2015-08-21 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8372689B2 (en) * | 2010-01-21 | 2013-02-12 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof |
US8536462B1 (en) | 2010-01-22 | 2013-09-17 | Amkor Technology, Inc. | Flex circuit package and method |
US8320134B2 (en) * | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
TWI411075B (en) * | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8300423B1 (en) | 2010-05-25 | 2012-10-30 | Amkor Technology, Inc. | Stackable treated via package and method |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8338229B1 (en) | 2010-07-30 | 2012-12-25 | Amkor Technology, Inc. | Stackable plasma cleaned via package and method |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8717775B1 (en) | 2010-08-02 | 2014-05-06 | Amkor Technology, Inc. | Fingerprint sensor package and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8337657B1 (en) | 2010-10-27 | 2012-12-25 | Amkor Technology, Inc. | Mechanical tape separation package and method |
US8482134B1 (en) | 2010-11-01 | 2013-07-09 | Amkor Technology, Inc. | Stackable package and method |
US9748154B1 (en) | 2010-11-04 | 2017-08-29 | Amkor Technology, Inc. | Wafer level fan out semiconductor device and manufacturing method thereof |
US8525318B1 (en) | 2010-11-10 | 2013-09-03 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8557629B1 (en) | 2010-12-03 | 2013-10-15 | Amkor Technology, Inc. | Semiconductor device having overlapped via apertures |
US8535961B1 (en) | 2010-12-09 | 2013-09-17 | Amkor Technology, Inc. | Light emitting diode (LED) package and method |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US9013011B1 (en) | 2011-03-11 | 2015-04-21 | Amkor Technology, Inc. | Stacked and staggered die MEMS package and method |
KR101140113B1 (en) | 2011-04-26 | 2012-04-30 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device |
US8653674B1 (en) | 2011-09-15 | 2014-02-18 | Amkor Technology, Inc. | Electronic component package fabrication method and structure |
US8633598B1 (en) | 2011-09-20 | 2014-01-21 | Amkor Technology, Inc. | Underfill contacting stacking balls package fabrication method and structure |
US9029962B1 (en) | 2011-10-12 | 2015-05-12 | Amkor Technology, Inc. | Molded cavity substrate MEMS package fabrication method and structure |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
TWI449152B (en) | 2011-12-21 | 2014-08-11 | Ind Tech Res Inst | Semiconductor device stacked structure |
JP5903920B2 (en) * | 2012-02-16 | 2016-04-13 | 富士通株式会社 | Semiconductor device manufacturing method and electronic device manufacturing method |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
KR101429344B1 (en) | 2012-08-08 | 2014-08-12 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package and Manufacturing Methode thereof |
KR20140038116A (en) | 2012-09-20 | 2014-03-28 | 제이앤제이 패밀리 주식회사 | Led lamp |
US9799592B2 (en) | 2013-11-19 | 2017-10-24 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
KR101366461B1 (en) | 2012-11-20 | 2014-02-26 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
KR101488590B1 (en) | 2013-03-29 | 2015-01-30 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and manufacturing method thereof |
TWI642094B (en) | 2013-08-06 | 2018-11-21 | 半導體能源研究所股份有限公司 | Peeling method |
TWI663722B (en) | 2013-09-06 | 2019-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device and method for manufacturing light-emitting device |
KR101607981B1 (en) | 2013-11-04 | 2016-03-31 | 앰코 테크놀로지 코리아 주식회사 | Interposer and method for manufacturing the same, and semiconductor package using the same |
JP6513929B2 (en) | 2013-11-06 | 2019-05-15 | 株式会社半導体エネルギー研究所 | Peeling method |
US10147630B2 (en) * | 2014-06-11 | 2018-12-04 | John Cleaon Moore | Sectional porous carrier forming a temporary impervious support |
US9799829B2 (en) | 2014-07-25 | 2017-10-24 | Semiconductor Energy Laboratory Co., Ltd. | Separation method, light-emitting device, module, and electronic device |
JP6822858B2 (en) | 2016-01-26 | 2021-01-27 | 株式会社半導体エネルギー研究所 | Method of forming the starting point of peeling and peeling method |
US9960328B2 (en) | 2016-09-06 | 2018-05-01 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5620928A (en) * | 1995-05-11 | 1997-04-15 | National Semiconductor Corporation | Ultra thin ball grid array using a flex tape or printed wiring board substrate and method |
JP2002362677A (en) * | 2001-06-06 | 2002-12-18 | Nitto Denko Corp | Carrier tape of chip-like electronic component, and using method thereof |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4918811A (en) | 1986-09-26 | 1990-04-24 | General Electric Company | Multichip integrated circuit packaging method |
US5032543A (en) | 1988-06-17 | 1991-07-16 | Massachusetts Institute Of Technology | Coplanar packaging techniques for multichip circuits |
US5144747A (en) | 1991-03-27 | 1992-09-08 | Integrated System Assemblies Corporation | Apparatus and method for positioning an integrated circuit chip within a multichip module |
US5250843A (en) | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
US5474958A (en) * | 1993-05-04 | 1995-12-12 | Motorola, Inc. | Method for making semiconductor device having no die supporting surface |
US5866952A (en) | 1995-11-30 | 1999-02-02 | Lockheed Martin Corporation | High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate |
US5841193A (en) | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US5830800A (en) * | 1997-04-11 | 1998-11-03 | Compeq Manufacturing Company Ltd. | Packaging method for a ball grid array integrated circuit without utilizing a base plate |
DE19752195A1 (en) * | 1997-11-25 | 1999-06-17 | Siemens Ag | Semiconductor component has a two-sided adhesive coated lead-on-chip tape with an aluminum oxide support |
KR100266138B1 (en) * | 1998-06-24 | 2000-09-15 | 윤종용 | Method for manufacturing chip scale package |
US6613413B1 (en) * | 1999-04-26 | 2003-09-02 | International Business Machines Corporation | Porous power and ground planes for reduced PCB delamination and better reliability |
US6370293B1 (en) * | 1999-09-16 | 2002-04-09 | Lucent Technologies, Inc. | Flexible optical circuits having optical fibers encapsulated between porous substrates and methods for fabricating same |
JP2001313350A (en) * | 2000-04-28 | 2001-11-09 | Sony Corp | Chip-shaped electronic component and its manufacturing method, and pseudo-wafer used for manufacture of chip- shaped electronic component and its manufacturing method |
US6528145B1 (en) * | 2000-06-29 | 2003-03-04 | International Business Machines Corporation | Polymer and ceramic composite electronic substrates |
KR100414479B1 (en) * | 2000-08-09 | 2004-01-07 | 주식회사 코스타트반도체 | Implantable circuit tapes for implanted semiconductor package and method for manufacturing thereof |
US6734534B1 (en) | 2000-08-16 | 2004-05-11 | Intel Corporation | Microelectronic substrate with integrated devices |
JP4100936B2 (en) * | 2002-03-01 | 2008-06-11 | Necエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP2003303919A (en) * | 2002-04-10 | 2003-10-24 | Hitachi Ltd | Semiconductor device and its manufacturing method |
-
2004
- 2004-02-09 US US10/774,977 patent/US7015075B2/en not_active Expired - Fee Related
-
2005
- 2005-01-12 CN CN2005800043966A patent/CN1918702B/en not_active Expired - Fee Related
- 2005-01-12 JP JP2006553132A patent/JP4555835B2/en not_active Expired - Fee Related
- 2005-01-12 WO PCT/US2005/001529 patent/WO2005076794A2/en active Application Filing
- 2005-01-12 EP EP05705847A patent/EP1721332A2/en not_active Withdrawn
- 2005-01-25 TW TW094102210A patent/TWI389221B/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5620928A (en) * | 1995-05-11 | 1997-04-15 | National Semiconductor Corporation | Ultra thin ball grid array using a flex tape or printed wiring board substrate and method |
JP2002362677A (en) * | 2001-06-06 | 2002-12-18 | Nitto Denko Corp | Carrier tape of chip-like electronic component, and using method thereof |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8963314B2 (en) | 2008-06-26 | 2015-02-24 | Nxp B.V. | Packaged semiconductor product and method for manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
TWI389221B (en) | 2013-03-11 |
US7015075B2 (en) | 2006-03-21 |
US20050176180A1 (en) | 2005-08-11 |
JP4555835B2 (en) | 2010-10-06 |
EP1721332A2 (en) | 2006-11-15 |
JP2007522675A (en) | 2007-08-09 |
CN1918702B (en) | 2010-05-26 |
CN1918702A (en) | 2007-02-21 |
WO2005076794A3 (en) | 2006-01-19 |
TW200531189A (en) | 2005-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7015075B2 (en) | Die encapsulation using a porous carrier | |
US20080182363A1 (en) | Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer | |
US8101527B2 (en) | Dicing film having shrinkage release film and method for manufacturing semiconductor package using the same | |
US9142434B2 (en) | Method for singulating electronic components from a substrate | |
US7202107B2 (en) | Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method | |
US8609471B2 (en) | Packaging an integrated circuit die using compression molding | |
US20090079064A1 (en) | Methods of forming a thin tim coreless high density bump-less package and structures formed thereby | |
US7476568B2 (en) | Wafer-level assembly of heat spreaders for dual IHS packages | |
US6946328B2 (en) | Method for manufacturing semiconductor devices | |
US8327532B2 (en) | Method for releasing a microelectronic assembly from a carrier substrate | |
JP2019515509A (en) | Floating die package | |
US20090091022A1 (en) | Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device | |
WO2015003068A1 (en) | Method and structure of panelized packaging of semiconductor devices | |
US9929072B2 (en) | Packaged semiconductor devices | |
WO2011093955A2 (en) | Dual carrier for joining ic die or wafers to tsv wafers | |
US20160343616A1 (en) | Semiconductor device including at least one element | |
US10163804B2 (en) | Molding structure for wafer level package | |
US8232140B2 (en) | Method for ultra thin wafer handling and processing | |
US20180063963A1 (en) | Polymer film stencil process for fan-out wafer-level packaging of semiconductor devices | |
US20080200037A1 (en) | Method of thinning a wafer | |
KR20080095797A (en) | Stack package with releasing layer and method for forming the same | |
TWI425580B (en) | Process for manufacturing semiconductor chip packaging module | |
TWI240386B (en) | Package for semiconductor components and method for producing the same | |
TW565898B (en) | Method for producing a package for semiconductor chips | |
RU2705229C1 (en) | Method for three-dimensional multi-chip packaging of integrated memory microcircuits |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
WWE | Wipo information: entry into national phase |
Ref document number: 3952/DELNP/2006 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2005705847 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2006553132 Country of ref document: JP Ref document number: 200580004396.6 Country of ref document: CN |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: DE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 11592479 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 2005705847 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 11592479 Country of ref document: US |