WO2005083768A1 - A method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor - Google Patents
A method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor Download PDFInfo
- Publication number
- WO2005083768A1 WO2005083768A1 PCT/SE2005/000251 SE2005000251W WO2005083768A1 WO 2005083768 A1 WO2005083768 A1 WO 2005083768A1 SE 2005000251 W SE2005000251 W SE 2005000251W WO 2005083768 A1 WO2005083768 A1 WO 2005083768A1
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- Prior art keywords
- layer region
- region
- silicon
- layer
- insulating material
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000003990 capacitor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 150000004767 nitrides Chemical group 0.000 claims abstract description 8
- 239000011810 insulating material Substances 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 9
- 206010010144 Completed suicide Diseases 0.000 claims 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 28
- 239000012212 insulator Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000013590 bulk material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0658—Vertical bipolar transistor in combination with resistors or capacitors
Definitions
- the present invention generally relates to the field of integrated circuit technology, and more specifically the invention relates to a method for fabrication of an SOI (Silicon-On-Insulator) substrate capacitor, and to a monolithically integrated circuit comprising such an SOI substrate capacitor.
- SOI Silicon-On-Insulator
- SOI technology especially using thin silicon top layers, which can be partially depleted (PD) or fully depleted (FD) already at very low bias voltages, are believed to become a key contributor to the continuous increase of circuit performance as predicted by Moore's law.
- PD partially depleted
- FD fully depleted
- SOI technology today is mainly applied in the field of high-speed processor technology.
- CMOS complementary metal-oxide-semiconductor
- BiCMOS complementary metal-oxide-semiconductor
- capacitors, resistors, varactors, inductors, etc. these devices have also to be redesigned for the new substrate material.
- a capacitor having high capacitance per area and high breakdown voltage is formed using a thin layer of silicon nitride deposited on top of highly doped silicon.
- a highly doped polycrystalline silicon layer region on top of the nitride serves as the top electrode.
- the bottom electrode consists of a subcollector layer and a collector plug arrangement to the upper side of the substrate.
- the thickness of the nitride layer is chosen so that the capacitor will obtain high capacitance values per area unit such as e.g. 2-4 fF/ ⁇ m 2 .
- a similar method to realize a capacitor is disclosed by H. Klose et al, B6HF: A 0.8 micron 25GHz/25ps bipolar technology for "Mobile radio” and “Ultra fast data link” IC-products, p. 125 in Proceedings of the 1993 Bipolar/BiCMOS Circuits and Technology Meeting.
- the capacitor is however described as ONO-type (ONO, oxide-nitride-oxide) with a capacitance value of 2 fF/ ⁇ m 2 , which means that the fabrication method is different.
- substrate capacitors may consist of a MOS-similar structure, where the gate oxide serves as dielectric.
- the isolation regions extend all the way down to the buried oxide layer, and thus the capacitor structures disclosed above cannot be fabricated.
- a method for fabrication of a monolithically integrated SOI substrate capacitor comprising the steps of: forming an insulating trench in a monocrystalline silicon top layer of a SOI structure, which trench reaches down to the buried insulator and surrounds a region of the monocrystalline silicon top layer of the SOI structure; doping the monocrystalline silicon top layer region; forming an insulating, preferably nitride, layer region on a portion of the monocrystalline silicon top layer region; forming a doped silicon layer region on the insulating layer region; and forming an insulating outside sidewall spacer on the monocrystalline silicon region, where the outside spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon top layer region.
- the monocrystalline silicon top layer region, the insulating layer region, and the doped silicon layer region constitute a lower
- the monocrystalline silicon top layer region is formed to a thickness of less than about 200 nm to allow for the fabrication of partly or fully depleted MOS devices therein.
- a monolithically integrated circuit comprising an SOI- substrate-based plate capacitor.
- the lower electrode of the capacitor is comprised of a doped monocrystalline SOI layer region surrounded by an insulating trench, which reaches down to a buried oxide layer of the SOI structure.
- the dielectric of the capacitor is comprised of a layer region of an insulating material, preferably nitride, on top of a portion of the monocrystalline SOI layer region.
- the upper electrode is comprised of a doped polycrystalline silicon layer region on top of the layer region of insulating material.
- An outside sidewall spacer structure of an insulating material, which surrounds the doped polycrystalline silicon layer region, provides isolation between the doped polycrystalline silicon layer region and exposed portions of the monocrystalline SOI layer region.
- the doped polycrystalline silicon layer region and the exposed portions of the monocrystalline SOI layer region are suicided, and metallic contacts to them are provided.
- the present invention provides a monolithically integrated SOI substrate capacitor, which has high capacitance per area unit, and can thus be made very compact.
- the use of doped monocrystalline silicon as lower electrode provides for a capacitor having low series resistance.
- the use of silicon nitride as the sole material for the capacitor dielectric has several advantages such as higher breakdown voltage and higher capacitance per unit area.
- Figs. 1-8 are highly enlarged cross-sectional views of a portion of a semiconductor structure during processing according to preferred embodiments of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
- a first preferred embodiment of a method in the fabrication of a monolithically integrated circuit including an SOI substrate capacitor is described below with reference to Figs. 1-6.
- the method is implemented in a CMOS, bipolar or BiCMOS process.
- a semiconductor structure is shown in Fig. 1 in cross section.
- a buried silicon oxide layer 11 is arranged between a silicon bulk substrate 12 and a monocrystalline silicon layer 13 to form a common SOI structure.
- the monocrystalline silicon layer 13 is a thin layer having advantageously a thickness of less than about 200 nm in order to be capable of fabricating fully depleted or partially depleted MOS devices provided that the fabrication process is a CMOS or BiCMOS process.
- a trench 14 is formed to surround a region 13' of the monocrystalline layer 13 of silicon.
- the trench 14, which is preferably formed by masking and etching, is filled with insulating material , to form a shallow trench isolation (STI) region. Due to the small thickness of the monocrystalline silicon layer 13, the trench 14 reaches down to the buried silicon oxide layer 11. The resulting structure is illustrated in Fig. 2.
- a thin oxide layer 15 is formed on the monocrystalline layer region 13' and an implantation mask 16 is applied on the structure.
- the thin oxide layer 15 may be a deposited low- quality oxide for the sole purpose of the ion implantation, or may be a grown high-quality oxide for use as e.g. gate oxides for MOS transistors in a CMOS or BiCMOS process.
- the monocrystalline silicon layer region 13', surrounded by the trench 14, is next doped to n ++ or p ++ to form a lower electrode of the monolithically integrated SOI substrate capacitor. If the substrate capacitor is fabricated in a bipolar or BiCMOS process, the silicon monocrystalline layer region 13' is preferably doped simultaneously with n + low-resistance collector contacts or plugs for bipolar transistors. The resulting structure is illustrated in Fig. 3.
- a thin layer 17 of an insulating material preferably silicon nitride, is formed on top of the structure.
- an insulating material preferably silicon nitride
- the thin insulating layer 17 can be used for isolation between extrinsic base connections and collector regions of bipolar transistors to lower the parasitic capacitance of the base- collector junctions, and if the fabrication process is a CMOS or BiCMOS process, the thin insulating layer 17 can be used for encapsulation of the gates of MOS transistors during subsequent processing e.g. in order to protect them from unwanted oxidation.
- a layer of polycrystalline silicon is formed on top of the thin layer 17.
- This silicon layer is either doped to n ++ or p ++ simultaneously with its deposition, or is doped to n ++ or p ++ subsequent to deposition by means of ion implantation.
- the polycrystalline silicon layer and the thin insulating layer 17 are next patterned and etched to form layer regions 18, 17' of doped silicon and insulating material, respectively, on top of a portion of the monocrystalline silicon layer region 13' as being illustrated in Fig. 5.
- the etching may be performed in a two-step etch process.
- the doped silicon layer region 18 constitutes an upper electrode of the monolithically integrated SOI substrate capacitor, whereas the insulating layer region 17' constitutes a dielectric thereof . It is particularly preferred if the insulating layer region 17' is of a material having a high dielectric number, such as silicon nitride, since a high capacitance per area unit is obtained.
- bipolar or BiCMOS process base layer regions i.e. extrinsic bases, for bipolar transistors are preferably formed in the polycrystalline silicon layer at least partly simultaneously with the formation of the silicon layer region 18.
- an outside spacer 61 of an insulating material is formed on top of the monocrystalline silicon layer region 13', and, depending on the layout, on top of the trench 14, where the outside spacer 61 surrounds the polycrystalline silicon layer region 18 to provide electric isolation between the polycrystalline silicon layer region 18 and exposed portions of the monocrystalline silicon layer region 13'.
- the spacer 61 is advantageously formed by means of conformal deposition of oxide or nitride followed by anisotropic etching.
- exposed silicon surfaces are suicided, preferably using a so-called self-aligned silicide (SALICIDE) method.
- SALICIDE self-aligned silicide
- a thin metal layer is deposited on the structure, and is made to react with exposed silicon at an elevated temperature to form a silicide.
- metal that has not reacted with silicon i.e. the metal at those portions, which had no exposed silicon surface prior to the metal deposition, is removed by wet chemical methods.
- metal silicide layer regions 62, 63 are formed on top of the upper surface of the polycrystalline silicon layer region 18, and on top of the exposed portions of the monocrystalline silicon layer region 13 ' to provide low- resistance connections.
- the resulting structure is illustrated in fig. 6.
- the processing continues with metallization in a customary manner, i.e. by forming a passivation layer, in which contact holes are etched and subsequently filled with metallic material, to achieve low-resistance connection paths from the capacitor electrodes 18, 13' to the metallization layers formed on top of the passivation layer.
- the monolithically integrated SOI substrate capacitor thus formed can be made compact as it has high capacitance per area unit.
- the use of doped monocrystalline silicon as lower electrode provides for low series resistance.
- a further doped polycrystalline silicon layer region 71 is formed prior to silicidation by means of depositing a polycrystalline silicon layer followed by patterning and etching the same. Doping may be performed simultaneously with the deposition of the layer or afterward by means of ion implantation.
- the further doped polycrystalline silicon layer region 71 is located laterally separated from the polycrystalline silicon layer region 18, which constitutes the upper electrode of the capacitor, and at least partly on top of the monocrystalline silicon layer region 13' to obtain an electric connection there between.
- the polycrystalline silicon layer region 71 constitutes an integral part of the lower electrode of the capacitor.
- An outside sidewall spacer 72 of an insulating material is formed to laterally surround and thus electrically isolate the further doped silicon layer region 71.
- This outside sidewall spacer 72 may be formed simultaneously with, or subsequent to, the formation of the outside spacer 61, which surrounds the polycrystalline silicon layer region 18 that constitutes the upper electrode of the capacitor.
- the upper surfaces of the polycrystalline layer regions 18, 71 are suicided in a self-aligned silicidation method whereupon metal silicide layer regions 62, 73 are formed. Simultaneously herewith, a metal silicide layer region 74 is formed on top of the upper surface of the monocrystalline silicon layer region 13' between the polycrystalline layer regions 18, 71.
- the further polycrystalline silicon layer region 71 which is part of the lower electrode of the capacitor, is advantageously formed simultaneously with the formation of emitter layer regions for bipolar transistors and gate layer regions for MOS transistors.
- this embodiment may be identical with the embodiment described with reference to Figs . 1-6.
- FIG. 8 A yet further preferred embodiment of the fabrication method of the invention is illustrated in Fig. 8.
- This embodiment is identical with the embodiment described with reference to Fig. 7 except for that the lateral distance between the polycrystalline silicon layer regions 18, 71 is similar to, or shorter than, a distance corresponding to the sum of the widths of the outside sidewall spacers 61, 72.
- the outside sidewall spacers 61, 72 are filling up the region on the upper surface of the monocrystalline silicon layer region 13' between the polycrystalline layer regions 18, 71, and no metal silicide layer region 74 is formed there.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112005000487T DE112005000487B4 (en) | 2004-03-02 | 2005-02-23 | A method of manufacturing a capacitor and a monolithic integrated circuit comprising such a capacitor |
US11/469,651 US7534685B2 (en) | 2004-03-02 | 2006-09-01 | Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0400504A SE527487C2 (en) | 2004-03-02 | 2004-03-02 | A method of producing a capacitor and a monolithic integrated circuit including such a capacitor |
SE0400504-7 | 2004-03-02 |
Related Child Applications (1)
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US11/469,651 Continuation US7534685B2 (en) | 2004-03-02 | 2006-09-01 | Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor |
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WO2005083768A1 true WO2005083768A1 (en) | 2005-09-09 |
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PCT/SE2005/000251 WO2005083768A1 (en) | 2004-03-02 | 2005-02-23 | A method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor |
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US (2) | US7534685B2 (en) |
CN (1) | CN100499042C (en) |
DE (1) | DE112005000487B4 (en) |
SE (1) | SE527487C2 (en) |
WO (1) | WO2005083768A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US7534685B2 (en) | 2004-03-02 | 2009-05-19 | Infineon Technologies Ag | Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor |
Families Citing this family (1)
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US9847293B1 (en) | 2016-08-18 | 2017-12-19 | Qualcomm Incorporated | Utilization of backside silicidation to form dual side contacted capacitor |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5807776A (en) * | 1995-12-06 | 1998-09-15 | Micron Technology, Inc. | Method of forming dynamic random access memory circuitry and dynamic random access memory |
US20030104658A1 (en) * | 2000-10-17 | 2003-06-05 | Toshiharu Furukawa | SOI hybrid structure with selective epitaxial growth of silicon |
US20040094792A1 (en) * | 2001-12-12 | 2004-05-20 | Matsushita Electric Industrial Co., Ltd. | Variable capacitance device and process for manufacturing the same |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6047458A (en) | 1983-08-26 | 1985-03-14 | Hitachi Ltd | Soi type mos dynamic memory |
US5087580A (en) * | 1990-09-17 | 1992-02-11 | Texas Instruments Incorporated | Self-aligned bipolar transistor structure and fabrication process |
US5273921A (en) * | 1991-12-27 | 1993-12-28 | Purdue Research Foundation | Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor |
US6008110A (en) * | 1994-07-21 | 1999-12-28 | Kabushiki Kaisha Toshiba | Semiconductor substrate and method of manufacturing same |
US5561302A (en) * | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US5952695A (en) * | 1997-03-05 | 1999-09-14 | International Business Machines Corporation | Silicon-on-insulator and CMOS-on-SOI double film structures |
CA2295990A1 (en) * | 1997-07-11 | 1999-01-21 | Telefonaktiebolaget Lm Ericsson | A process for manufacturing ic-components to be used at radio frequencies |
DE19853268C2 (en) * | 1998-11-18 | 2002-04-11 | Infineon Technologies Ag | Field effect controlled transistor and method for its production |
SE0103036D0 (en) * | 2001-05-04 | 2001-09-13 | Ericsson Telefon Ab L M | Semiconductor process and integrated circuit |
DE10124032B4 (en) * | 2001-05-16 | 2011-02-17 | Telefunken Semiconductors Gmbh & Co. Kg | Method of manufacturing components on an SOI wafer |
US6596570B2 (en) * | 2001-06-06 | 2003-07-22 | International Business Machines Corporation | SOI device with reduced junction capacitance |
US6498358B1 (en) * | 2001-07-20 | 2002-12-24 | Motorola, Inc. | Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating |
JP4136452B2 (en) * | 2002-05-23 | 2008-08-20 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US7012298B1 (en) * | 2002-06-21 | 2006-03-14 | Advanced Micro Devices, Inc. | Non-volatile memory device |
DE10229003B4 (en) * | 2002-06-28 | 2014-02-13 | Advanced Micro Devices, Inc. | A method of fabricating an SOI field effect transistor element having a recombination region |
US6965128B2 (en) * | 2003-02-03 | 2005-11-15 | Freescale Semiconductor, Inc. | Structure and method for fabricating semiconductor microresonator devices |
US6900502B2 (en) * | 2003-04-03 | 2005-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel on insulator device |
US6864149B2 (en) * | 2003-05-09 | 2005-03-08 | Taiwan Semiconductor Manufacturing Company | SOI chip with mesa isolation and recess resistant regions |
US6958513B2 (en) * | 2003-06-06 | 2005-10-25 | Chih-Hsin Wang | Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells |
US20050136580A1 (en) * | 2003-12-22 | 2005-06-23 | Luigi Colombo | Hydrogen free formation of gate electrodes |
SE527487C2 (en) | 2004-03-02 | 2006-03-21 | Infineon Technologies Ag | A method of producing a capacitor and a monolithic integrated circuit including such a capacitor |
EP1630863B1 (en) * | 2004-08-31 | 2014-05-14 | Infineon Technologies AG | Method of fabricating a monolithically integrated vertical semiconducting device in an soi substrate |
-
2004
- 2004-03-02 SE SE0400504A patent/SE527487C2/en not_active IP Right Cessation
-
2005
- 2005-02-23 DE DE112005000487T patent/DE112005000487B4/en not_active Expired - Fee Related
- 2005-02-23 WO PCT/SE2005/000251 patent/WO2005083768A1/en active Application Filing
- 2005-02-23 CN CNB2005800133727A patent/CN100499042C/en not_active Expired - Fee Related
-
2006
- 2006-09-01 US US11/469,651 patent/US7534685B2/en active Active
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2009
- 2009-03-30 US US12/413,646 patent/US7871881B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5807776A (en) * | 1995-12-06 | 1998-09-15 | Micron Technology, Inc. | Method of forming dynamic random access memory circuitry and dynamic random access memory |
US20030104658A1 (en) * | 2000-10-17 | 2003-06-05 | Toshiharu Furukawa | SOI hybrid structure with selective epitaxial growth of silicon |
US20040094792A1 (en) * | 2001-12-12 | 2004-05-20 | Matsushita Electric Industrial Co., Ltd. | Variable capacitance device and process for manufacturing the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7534685B2 (en) | 2004-03-02 | 2009-05-19 | Infineon Technologies Ag | Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor |
Also Published As
Publication number | Publication date |
---|---|
CN100499042C (en) | 2009-06-10 |
SE527487C2 (en) | 2006-03-21 |
US20070117285A1 (en) | 2007-05-24 |
US20090181512A1 (en) | 2009-07-16 |
US7534685B2 (en) | 2009-05-19 |
US7871881B2 (en) | 2011-01-18 |
DE112005000487B4 (en) | 2012-01-05 |
DE112005000487T5 (en) | 2007-01-04 |
SE0400504L (en) | 2005-09-03 |
CN1947233A (en) | 2007-04-11 |
SE0400504D0 (en) | 2004-03-02 |
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