WO2005088441A2 - Inserting bits within a data word - Google Patents

Inserting bits within a data word Download PDF

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Publication number
WO2005088441A2
WO2005088441A2 PCT/GB2004/003343 GB2004003343W WO2005088441A2 WO 2005088441 A2 WO2005088441 A2 WO 2005088441A2 GB 2004003343 W GB2004003343 W GB 2004003343W WO 2005088441 A2 WO2005088441 A2 WO 2005088441A2
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WO
WIPO (PCT)
Prior art keywords
register
shift
value
data
bits
Prior art date
Application number
PCT/GB2004/003343
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French (fr)
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WO2005088441A3 (en
Inventor
Simon Andrew Ford
Paul Matthew Carpenter
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Arm Limited
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Publication date
Application filed by Arm Limited filed Critical Arm Limited
Priority to EP04743646A priority Critical patent/EP1723512A2/en
Priority to JP2007502375A priority patent/JP2007528545A/en
Publication of WO2005088441A2 publication Critical patent/WO2005088441A2/en
Publication of WO2005088441A3 publication Critical patent/WO2005088441A3/en
Priority to IL177507A priority patent/IL177507A/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Definitions

  • This invention relates to data processing systems. More particularly, this invention relates to the insertion of bits within a data word under program control.
  • one possible solution is to provide program instructions which specify both a length of a bit field within a source register which is to be inserted into a destination register and the position within the destination register at which that bit field is to be inserted.
  • Such an instruction will typically have to specify the source register, the destination register, the bit field length and the bit field insertion position. Having to specify four separate parameters within a single instruction in this way places a disadvantageously high demand upon the instruction bit space available within the instruction and makes such instructions disadvantageous in terms of the instruction bit space they consume.
  • the present invention provides apparatus for processing data, said apparatus comprising: a plurality of registers operable to store data values to be manipulated; processing logic operable to perform a data processing operation upon one or more data values stored within said plurality of registers; and an instruction decoder responsive to a program instruction to control said processing logic to perform a data processing operation specified by said program instruction; wherein said instruction decoder is responsive to a shift-and-insert instruction to control said processing logic to perform a shift-and-insert data processing operation yielding a result having a result value given by: shifting a first data value stored within a first register by a shift amount of N bit positions to form a shifted value including N shifted-in bits, where N has one of a plurality of different non-zero values; and inserting respective bits of said shifted value, other than said N shifted-in bits, into corresponding bit positions in a second data value stored within a second register with bits within said second data value corresponding to said N shifted-in
  • the present invention recognises that a large proportion of the cases in which it is desired to use such instructions the full flexibility of being able to separately specify the bit field length and the bit field position is not required. Instead, a single parameter specifying the amount of shift to be applied to the source value controls the starting position at which bits of the source value are written into the destination value. The bits written into the destination value extend from the starting position to the appropriate end of the destination value depending upon the shift direction of the instruction concerned. It may be that a greater number of bits are inserted than are ultimately required.
  • the present technique recognises that in a large proportion of cases multiple such instructions are executed and the excess bits written in one instruction will be over-written with the desired data in a following instruction such that the final packed data value will contain the correct bits as desired.
  • the packing type of operations, or other bit assembly operations can be achieved with instructions having an advantageously small instruction bit space requirement.
  • the expression of the invention as set out above is made in terms of a shift-and-insert instruction yielding a result having a result value given by a specified shift operation and a specified insert operation.
  • the actual mechanisms employed to achieve a result value the same as if such a shift and insert had been performed can vary.
  • Such variant mechanisms and steps are encompassed by the present technique.
  • the shifting and inserting steps are one way of expressing how the desired end result is related to the inputs but the same relationship between inputs and outputs may be achieved and expressed in a variety of different ways. These alternatives are encompassed within the present technique.
  • the shift amount could be specified as a value stored within a register specified within the instruction or alternatively and preferably as an immediate value encoded within the shift-and-insert instruction itself.
  • the first and second registers are advantageously specified by a source register specifying fields, both relative to the registers of a register bank.
  • a destination register specifying field (optionally shared with one of the first register or second register) may also be used.
  • the shifting of the present technique may be either right shifting or left shifting depending upon the circumstances and the desired form of packing or bit insertion. It is possible that the first data value and the second data value could have different bit lengths and be stored in registers of different lengths although in preferred embodiments the first data value and the second data value have the same number of bits.
  • the relationship between the inputs and the outputs as set out above may be implemented in a variety of different ways although a preferred way is to use a shift of the first value and to form a mask value for selecting which bits within the second data value are replaced by corresponding bits within the shifted data value and which bits within the second data value are unaltered.
  • This mask value can advantageously be formed by a shift upon a starting mask or by alternative techniques such as a decode of the instruction directly forming the mask.
  • the present technique may be used with advantage both within scalar processing systems and single instruction multiple data packets (SIMD) processing systems.
  • SIMD single instruction multiple data packets
  • a method of processing data comprising the steps of: storing data values to be manipulated within a plurality of registers; performing a data processing operation using processing logic upon one or more data values stored within said plurality of registers; and in response to a program instruction, using an instruction decoder to control said processing logic to perform a data processing operation specified by said program instruction; wherein said instruction decoder is responsive to a shift-and-insert instruction to control said processing logic to perform a shift-and-insert data processing operation yielding a result having a result value given by: shifting a first data value stored within a first register by a shift amount of N bit positions to form a shifted value including N shifted-in bits, where N has one of a plurality of different non-zero values; and inserting respective bits of said shifted value, other than said N shifted-in bits, into corresponding bit positions in a second data value stored within a second register with bits within said second data value corresponding to said N
  • Figure 1 schematically illustrates a data processing system of the type which may utilise the present techniques
  • Figure 2 schematically illustrates the syntax of three different shift-and-insert instructions in accordance with one example of the present technique
  • Figure 3 schematically illustrates the action of a shift-and-insert instruction
  • Figure 4 schematically illustrates a hardware arrangement for performing a shift- and-insert operation
  • Figure 5 illustrates an example of a pixel value packing operation within a scalar processing system
  • Figure 6 schematically illustrates a pixel packing operation within a single instruction multiple data system.
  • Figure 1 schematically illustrates a data processing system 2 which may be in the form of an integrated circuit including a register bank 4, a multiplier 6, a shifter 8 and an adder 10.
  • the register bank 4, the multiplier 6, the shifter 8 and the adder 10 can be considered to form processing logic for executing desired data processing operations under control of control signals generated by an instruction decoder 12.
  • the instruction decoder 12 is itself responsive to program instructions loaded into an instruction pipeline 14. It will be appreciated that the data processing system of Figure 2 will typically contain many more elements, but these have been omitted for the sake of clarity.
  • program instructions are fetched into the instruction pipeline 14 and when they reach an execute stage within the instruction pipeline 14 are used by the instruction decoder 12 to generate control signals which configure the various elements of the processing logic 4, 6, 8, 10 to execute the desired data processing operation.
  • the processing logic will typically include many further elements for providing processing operations other than the simple multiply, shift and add operations illustrated in Figure 1.
  • FIG. 2 schematically illustrates the syntax of some example shift-and-insert instructions which may be supported by the data processing system 2 of Figure 1.
  • a shift left and insert instruction SLI includes a register field specifying a destination register dest, a register field specifying a source register src and a field specifying an immediate value #imm.
  • the source register contains the data value which is to be shifted and then inserted into the destination register with some of the bits within the destination register being unaltered.
  • the immediate value #imm specifies the amount of shift applied to the source register value before the insertion takes place and also effectively the position at which the insertion takes place as will be described further below.
  • Figure 2 illustrates a right shifting variant of the above instruction, namely an SRI instruction. There is also illustrated a variant of the left shifted instruction in which the shift value is specified by a second source register src2. It will be appreciated that the syntax and exact form of the instructions as illustrated in Figure 1 is only one example and different embodiments of the present technique may use instruction representations and syntaxes which vary considerably.
  • Figure 3 illustrates one example of a shift and insert operation.
  • a register 16 contains a source value. This source value contains a data portion 18, such as a pixel value. The portion of the register 16 outside of the data portion 18 may represent nothing meaningful or may be a fractional part of the data value which it is desired to discard.
  • the value within the register 16 is in this example subject to a right shift by an amount specified by the immediate field #imm within the SRI instruction concerned.
  • shifted-in bits are introduced into the shifted value which is generated. This is normal shift operation behavior.
  • the destination value is held within a register 20 and a portion of the shifted value other than the shifted-in bits is written into this destination value replacing the corresponding bits initially stored within the destination value.
  • the bits within the destination value 20 correspond to the shifted-in bits within the shifted value are not replaced and are left unaltered.
  • the final result value contains the original destination value with the inserted bits from the shifted value replacing its original bits at those corresponding positions.
  • bits from the shifted value other than only the data portion 18 have been inserted within the result value, namely bits G and H. If significant, then these unwanted bits can be overwritten by further bit values in a subsequence shift-and-insert operation, as desired.
  • Figure 4 schematically illustrates a hardware representation as to how the shift-and- insert instruction can be implemented.
  • the source register 22 supplies its value to, in this example, a left shifter 24. It will be appreciated that for the right shifting variants of the instruction right shifting circuits will be used instead.
  • the shift amount is specified in this example by an immediate value of #4.
  • the left shifter 24 produces a shifted value 26 with four shifted-in zero values in its four right most bit positions.
  • a mask value is produced by taking a starting mask value 28 containing all ones and subjecting this to the same shift as is being applied to the source value 22 with its own left shifter 30.
  • the shifted-in values into the mask value are again zeros and this results in a shifted mask 32.
  • the shifted mask 32 can then be used as a multi-bit control signal supplied to a multi-bit multiplexer 34 which selects either bits from the shifted value 26 or bits from the destination value 36 to feed to a result value 38.
  • Figure 5 illustrates a scalar packing operation of red, green and blue pixel value components into a 16 bit result value. The first operation executes upon the red and green component values using a right shift-and-insert instruction with a shift amount of five bit positions. This leaves the 5-bit red component R 5 unaltered within the result but writes in the green component G 6 as well as its remainder into that result.
  • the second instruction takes the combined red and green component and inserts into it the blue component B 5 by performing a right shift-and-insert instruction with a shift amount of 11 bit positions such that the blue component B 5 abuts the end of the already inserted green component G 6 and fills the remaining positions within the 16 bit result value.
  • Figure 6 illustrates the same type of packing operation as illustrated in Figure 5 but in this case performed within a single instruction multiple data (SMID) system.
  • SMID single instruction multiple data
  • the same shift-and-insert operation is separately performed upon each data lane within the SIMD system to enable four sets of pixel values to be packed together in parallel using two SIMD right shift-and-insert instructions.

Abstract

A data processing system (2) is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination value with the remaining bits within that destination value being unaltered.

Description

INSERTING BITS WITHIN A DATA WORD
This invention relates to data processing systems. More particularly, this invention relates to the insertion of bits within a data word under program control.
It is known within data processing systems to pack together a plurality of fields of bits within a single data word. As an example, within a 16 bit data word it may be desired to pack three colour component values respectively representing red, green and blue values, two of which are of 5 bits in length and one of which is 6 bits in length. It is often the case that these different component values will be separately processed and their magnitudes separately calculated. After such calculations the separate components require assembling together within a single data word such that they may be stored in a more compact form and more readily manipulated on a pixel-by-pixel basis. In order to achieve such data packing, one possible solution is to provide program instructions which specify both a length of a bit field within a source register which is to be inserted into a destination register and the position within the destination register at which that bit field is to be inserted. Such an instruction will typically have to specify the source register, the destination register, the bit field length and the bit field insertion position. Having to specify four separate parameters within a single instruction in this way places a disadvantageously high demand upon the instruction bit space available within the instruction and makes such instructions disadvantageous in terms of the instruction bit space they consume. Viewed from one aspect the present invention provides apparatus for processing data, said apparatus comprising: a plurality of registers operable to store data values to be manipulated; processing logic operable to perform a data processing operation upon one or more data values stored within said plurality of registers; and an instruction decoder responsive to a program instruction to control said processing logic to perform a data processing operation specified by said program instruction; wherein said instruction decoder is responsive to a shift-and-insert instruction to control said processing logic to perform a shift-and-insert data processing operation yielding a result having a result value given by: shifting a first data value stored within a first register by a shift amount of N bit positions to form a shifted value including N shifted-in bits, where N has one of a plurality of different non-zero values; and inserting respective bits of said shifted value, other than said N shifted-in bits, into corresponding bit positions in a second data value stored within a second register with bits within said second data value corresponding to said N shifted-in bits being unaltered thereby forming said result.
The present invention recognises that a large proportion of the cases in which it is desired to use such instructions the full flexibility of being able to separately specify the bit field length and the bit field position is not required. Instead, a single parameter specifying the amount of shift to be applied to the source value controls the starting position at which bits of the source value are written into the destination value. The bits written into the destination value extend from the starting position to the appropriate end of the destination value depending upon the shift direction of the instruction concerned. It may be that a greater number of bits are inserted than are ultimately required. However, the present technique recognises that in a large proportion of cases multiple such instructions are executed and the excess bits written in one instruction will be over-written with the desired data in a following instruction such that the final packed data value will contain the correct bits as desired. Thus, the packing type of operations, or other bit assembly operations, can be achieved with instructions having an advantageously small instruction bit space requirement. It will be appreciated that the expression of the invention as set out above is made in terms of a shift-and-insert instruction yielding a result having a result value given by a specified shift operation and a specified insert operation. It will be appreciated that the actual mechanisms employed to achieve a result value the same as if such a shift and insert had been performed can vary. Such variant mechanisms and steps are encompassed by the present technique. The shifting and inserting steps are one way of expressing how the desired end result is related to the inputs but the same relationship between inputs and outputs may be achieved and expressed in a variety of different ways. These alternatives are encompassed within the present technique. The shift amount could be specified as a value stored within a register specified within the instruction or alternatively and preferably as an immediate value encoded within the shift-and-insert instruction itself.
The first and second registers are advantageously specified by a source register specifying fields, both relative to the registers of a register bank. A destination register specifying field (optionally shared with one of the first register or second register) may also be used.
It will be appreciated that the shifting of the present technique may be either right shifting or left shifting depending upon the circumstances and the desired form of packing or bit insertion. It is possible that the first data value and the second data value could have different bit lengths and be stored in registers of different lengths although in preferred embodiments the first data value and the second data value have the same number of bits.
As previously mentioned it will be appreciated that the relationship between the inputs and the outputs as set out above may be implemented in a variety of different ways although a preferred way is to use a shift of the first value and to form a mask value for selecting which bits within the second data value are replaced by corresponding bits within the shifted data value and which bits within the second data value are unaltered. This mask value can advantageously be formed by a shift upon a starting mask or by alternative techniques such as a decode of the instruction directly forming the mask.
The present technique may be used with advantage both within scalar processing systems and single instruction multiple data packets (SIMD) processing systems.
Viewed from another aspect the present invention a method of processing data, said method comprising the steps of: storing data values to be manipulated within a plurality of registers; performing a data processing operation using processing logic upon one or more data values stored within said plurality of registers; and in response to a program instruction, using an instruction decoder to control said processing logic to perform a data processing operation specified by said program instruction; wherein said instruction decoder is responsive to a shift-and-insert instruction to control said processing logic to perform a shift-and-insert data processing operation yielding a result having a result value given by: shifting a first data value stored within a first register by a shift amount of N bit positions to form a shifted value including N shifted-in bits, where N has one of a plurality of different non-zero values; and inserting respective bits of said shifted value, other than said N shifted-in bits, into corresponding bit positions in a second data value stored within a second register with bits within said second data value corresponding to said N shifted-in bits being unaltered thereby forming said result.
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 schematically illustrates a data processing system of the type which may utilise the present techniques;
Figure 2 schematically illustrates the syntax of three different shift-and-insert instructions in accordance with one example of the present technique;
Figure 3 schematically illustrates the action of a shift-and-insert instruction;
Figure 4 schematically illustrates a hardware arrangement for performing a shift- and-insert operation;
Figure 5 illustrates an example of a pixel value packing operation within a scalar processing system; and Figure 6 schematically illustrates a pixel packing operation within a single instruction multiple data system.
Figure 1 schematically illustrates a data processing system 2 which may be in the form of an integrated circuit including a register bank 4, a multiplier 6, a shifter 8 and an adder 10. The register bank 4, the multiplier 6, the shifter 8 and the adder 10 can be considered to form processing logic for executing desired data processing operations under control of control signals generated by an instruction decoder 12. The instruction decoder 12 is itself responsive to program instructions loaded into an instruction pipeline 14. It will be appreciated that the data processing system of Figure 2 will typically contain many more elements, but these have been omitted for the sake of clarity. In operation, program instructions are fetched into the instruction pipeline 14 and when they reach an execute stage within the instruction pipeline 14 are used by the instruction decoder 12 to generate control signals which configure the various elements of the processing logic 4, 6, 8, 10 to execute the desired data processing operation. The processing logic will typically include many further elements for providing processing operations other than the simple multiply, shift and add operations illustrated in Figure 1.
Figure 2 schematically illustrates the syntax of some example shift-and-insert instructions which may be supported by the data processing system 2 of Figure 1. A shift left and insert instruction SLI includes a register field specifying a destination register dest, a register field specifying a source register src and a field specifying an immediate value #imm. The source register contains the data value which is to be shifted and then inserted into the destination register with some of the bits within the destination register being unaltered. The immediate value #imm specifies the amount of shift applied to the source register value before the insertion takes place and also effectively the position at which the insertion takes place as will be described further below.
Figure 2 illustrates a right shifting variant of the above instruction, namely an SRI instruction. There is also illustrated a variant of the left shifted instruction in which the shift value is specified by a second source register src2. It will be appreciated that the syntax and exact form of the instructions as illustrated in Figure 1 is only one example and different embodiments of the present technique may use instruction representations and syntaxes which vary considerably. Figure 3 illustrates one example of a shift and insert operation. A register 16 contains a source value. This source value contains a data portion 18, such as a pixel value. The portion of the register 16 outside of the data portion 18 may represent nothing meaningful or may be a fractional part of the data value which it is desired to discard. The value within the register 16 is in this example subject to a right shift by an amount specified by the immediate field #imm within the SRI instruction concerned. At the left hand end of the register, shifted-in bits are introduced into the shifted value which is generated. This is normal shift operation behavior. The destination value is held within a register 20 and a portion of the shifted value other than the shifted-in bits is written into this destination value replacing the corresponding bits initially stored within the destination value. The bits within the destination value 20 correspond to the shifted-in bits within the shifted value are not replaced and are left unaltered. The final result value contains the original destination value with the inserted bits from the shifted value replacing its original bits at those corresponding positions. It will be seen in the current example that bits from the shifted value other than only the data portion 18 have been inserted within the result value, namely bits G and H. If significant, then these unwanted bits can be overwritten by further bit values in a subsequence shift-and-insert operation, as desired.
Figure 4 schematically illustrates a hardware representation as to how the shift-and- insert instruction can be implemented. The source register 22 supplies its value to, in this example, a left shifter 24. It will be appreciated that for the right shifting variants of the instruction right shifting circuits will be used instead. The shift amount is specified in this example by an immediate value of #4. The left shifter 24 produces a shifted value 26 with four shifted-in zero values in its four right most bit positions. In parallel with the generation of the shifted value 26, a mask value is produced by taking a starting mask value 28 containing all ones and subjecting this to the same shift as is being applied to the source value 22 with its own left shifter 30. The shifted-in values into the mask value are again zeros and this results in a shifted mask 32. The shifted mask 32 can then be used as a multi-bit control signal supplied to a multi-bit multiplexer 34 which selects either bits from the shifted value 26 or bits from the destination value 36 to feed to a result value 38. Figure 5 illustrates a scalar packing operation of red, green and blue pixel value components into a 16 bit result value. The first operation executes upon the red and green component values using a right shift-and-insert instruction with a shift amount of five bit positions. This leaves the 5-bit red component R5 unaltered within the result but writes in the green component G6 as well as its remainder into that result. The second instruction takes the combined red and green component and inserts into it the blue component B5 by performing a right shift-and-insert instruction with a shift amount of 11 bit positions such that the blue component B5 abuts the end of the already inserted green component G6 and fills the remaining positions within the 16 bit result value. Figure 6 illustrates the same type of packing operation as illustrated in Figure 5 but in this case performed within a single instruction multiple data (SMID) system. As will be appreciated the same shift-and-insert operation is separately performed upon each data lane within the SIMD system to enable four sets of pixel values to be packed together in parallel using two SIMD right shift-and-insert instructions.

Claims

1. Apparatus for processing data, said apparatus comprising: a plurality of registers operable to store data values to be manipulated; processing logic operable to perform a data processing operation upon one or more data values stored within said plurality of registers; and an instruction decoder responsive to a program instruction to control said processing logic to perform a data processing operation specified by said program instruction; wherein said instruction decoder is responsive to a shift-and-insert instruction to control said processing logic to perform a shift-and-insert data processing operation yielding a result having a result value given by: shifting a first data value stored within a first register by a shift amount of N bit positions to form a shifted value including N shifted-in bits, where N has one of a plurality of different non-zero values; and inserting respective bits of said shifted value, other than said N shifted-in bits, into corresponding bit positions in a second data value stored within a second register with bits within said second data value corresponding to said N shifted-in bits being unaltered thereby forming said result.
2. Apparatus as claimed in claim 1, wherein said shift-and-insert instruction includes an immediate value specifying said shift amount of N bit positions.
3. Apparatus as claimed in any one of claims 1 and 2, wherein said shift-and-insert instruction includes a register specifying field specifying a register within a register bank to be used as said first register.
4. Apparatus as claimed in any one of claims 1, 2 and 3, wherein said shift-and-insert instruction includes a register specifying field specifying a register within a register bank to be used as said second register.
5. Apparatus as claimed in any one of the preceding claims, wherein a shift-and-insert instruction includes a register specifying field specifying a register within a register bank to be used as a destination register.
6. Apparatus as claimed in claim 5, wherein said register specifying field for said destination register is shared with one of said first register and second register.
7. Apparatus as claimed in any one of the preceding claims, wherein said first data value is right shifted.
8. Apparatus as claimed in any one of claims 1 to 6, wherein said first data value is left shifted.
9. Apparatus as claimed in any one of the preceding claims, wherein said first data value and said second data value have the same number of bits.
10. Apparatus as claimed in any one of the preceding claims, wherein, in response to said shift-and-insert instruction, said processing logic is operable to shift said first value.
11. Apparatus as claimed in any one of the preceding claims, wherein, in response to said shift-and-insert instruction, said processing logic is operable to form a mask value for selecting which bits within said second data value are replaced by corresponding bits within said shifted data value and which bits within said second data value are unaltered.
12. Apparatus as claimed in any one of the preceding claims, wherein said processing logic is single instruction multiple data processing logic and said first register and said second register are respective portions of a first single instruction multiple data register and a second single instruction multiple data register, said shift-and-insert instruction being operable to control execution in parallel of a plurality of shift-and-insert operations in respective processing lanes.
13. Apparatus as claimed in any one of claims 1 to 11, wherein said processing logic is scalar processing logic.
14. A method of processing data, said method comprising the steps of: storing data values to be manipulated within a plurality of registers; performing a data processing operation using processing logic upon one or more data values stored within said plurality of registers; and in response to a program instruction, using an instruction decoder to control said processing logic to perform a data processing operation specified by said program instruction; wherein said instruction decoder is responsive to a shift-and-insert instruction to control said processing logic to perform a shift-and-insert data processing operation yielding a result having a result value given by: shifting a first data value stored within a first register by a shift amount of N bit positions to form a shifted value including N shifted-in bits, where N has one of a plurality of different non-zero values; and inserting respective bits of said shifted value, other than said N shifted-in bits, into corresponding bit positions in a second data value stored within a second register with bits within said second data value corresponding to said N shifted-in bits being unaltered thereby forming said result.
15. A method as claimed in claim 14, wherein said shift-and-insert instruction includes an immediate value specifying said shift amount of N bit positions.
16. A method as claimed in any one of claims 14 and 15, wherein said shift-and-insert instruction includes a register specifying field specifying a register within a register bank to be used as said first register.
17. A method as claimed in any one of claims 14, 15 and 16, wherein shift-and-insert instruction includes a register specifying field specifying a register within a register bank to be used as said second register.
18. A method as claimed in any one of claims 14 to 17, wherein shift-and-insert instruction includes a register specifying field specifying a register within a register bank to be used as a destination register.
19. A method as claimed in claim 18, wherein said register specifying field for said destination register is shared with one of said first register and second register.
20. A method as claimed in any one of claims 13 to 17, wherein said first data value is right shifted.
21. A method as claimed in any one of claims 14 to 17, wherein said first data value is left shifted.
22. A method as claimed in any one of claims 14 to 19, wherein said first data value and said second data value have the same number of bits.
23. A method as claimed in any one of claims 14 to 20, wherein, in response to said shift-and-insert instruction, said processing logic is operable to shift said first value.
24. A method as claimed in any one of claims 14 to 21, wherein, in response to said shift-and-insert instruction, said processing logic is operable to form a mask value for selecting which bits within said second data value are replaced by corresponding bits within said shifted data value and which bits within said second data value are unaltered.
25. A method as claimed in any one of claims 14 to 22, wherein said processing logic is single instruction multiple data processing logic and said first register and said second register are respective portions of a first single instruction multiple data register and a second single instruction multiple data register, said shift-and-insert instruction being operable to control execution in parallel of a plurality of shift-and-insert operations in respective processing lanes.
26. A method as claimed in any one of claims 14 to 22, wherein said processing logic is scalar processing logic.
PCT/GB2004/003343 2004-03-10 2004-08-03 Inserting bits within a data word WO2005088441A2 (en)

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US20050204117A1 (en) 2005-09-15
GB2411978A (en) 2005-09-14
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TW200530838A (en) 2005-09-16
MY137200A (en) 2009-01-30
KR20070028322A (en) 2007-03-12
GB0405407D0 (en) 2004-04-21
CN100538624C (en) 2009-09-09
TWI322947B (en) 2010-04-01
KR100981998B1 (en) 2010-09-13
IL177507A (en) 2010-12-30
WO2005088441A3 (en) 2006-06-22
GB2411978B (en) 2007-04-04
IL177507A0 (en) 2006-12-10
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JP2007528545A (en) 2007-10-11
RU2006135629A (en) 2008-04-20

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