WO2005089165A3 - Nano-enabled memory devices and anisotropic charge carrying arrays - Google Patents

Nano-enabled memory devices and anisotropic charge carrying arrays Download PDF

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Publication number
WO2005089165A3
WO2005089165A3 PCT/US2005/007709 US2005007709W WO2005089165A3 WO 2005089165 A3 WO2005089165 A3 WO 2005089165A3 US 2005007709 W US2005007709 W US 2005007709W WO 2005089165 A3 WO2005089165 A3 WO 2005089165A3
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WO
WIPO (PCT)
Prior art keywords
substrate
memory device
nanoelements
discrete energy
memory devices
Prior art date
Application number
PCT/US2005/007709
Other languages
French (fr)
Other versions
WO2005089165A2 (en
Inventor
Xiangfeng Duan
Calvin Y H Chow
David L Heald
Chunming Niu
J Wallace Parce
David P Stumbo
Original Assignee
Nanosys Inc
Xiangfeng Duan
Calvin Y H Chow
David L Heald
Chunming Niu
J Wallace Parce
David P Stumbo
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/796,413 external-priority patent/US20050202615A1/en
Priority claimed from US11/018,572 external-priority patent/US7595528B2/en
Application filed by Nanosys Inc, Xiangfeng Duan, Calvin Y H Chow, David L Heald, Chunming Niu, J Wallace Parce, David P Stumbo filed Critical Nanosys Inc
Priority to EP05758741A priority Critical patent/EP1723676A4/en
Priority to JP2007502948A priority patent/JP4871255B2/en
Publication of WO2005089165A2 publication Critical patent/WO2005089165A2/en
Publication of WO2005089165A3 publication Critical patent/WO2005089165A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G5/00—Recording members for original recording by exposure, e.g. to light, to heat, to electrons; Manufacture thereof; Selection of materials therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G5/00—Recording members for original recording by exposure, e.g. to light, to heat, to electrons; Manufacture thereof; Selection of materials therefor
    • G03G5/02—Charge-receiving layers
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    • G03G5/00—Recording members for original recording by exposure, e.g. to light, to heat, to electrons; Manufacture thereof; Selection of materials therefor
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    • G03G5/04—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor
    • G—PHYSICS
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    • G03G5/00—Recording members for original recording by exposure, e.g. to light, to heat, to electrons; Manufacture thereof; Selection of materials therefor
    • G03G5/02—Charge-receiving layers
    • G03G5/04—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor
    • G03G5/043—Photoconductive layers characterised by having two or more layers or characterised by their composite structure
    • G—PHYSICS
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    • G03G5/08—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor characterised by the photoconductive material being inorganic
    • G—PHYSICS
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    • G03G5/08—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor characterised by the photoconductive material being inorganic
    • G03G5/082—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor characterised by the photoconductive material being inorganic and not being incorporated in a bonding material, e.g. vacuum deposited
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G5/00—Recording members for original recording by exposure, e.g. to light, to heat, to electrons; Manufacture thereof; Selection of materials therefor
    • G03G5/02—Charge-receiving layers
    • G03G5/04—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor
    • G03G5/08—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor characterised by the photoconductive material being inorganic
    • G03G5/082—Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor characterised by the photoconductive material being inorganic and not being incorporated in a bonding material, e.g. vacuum deposited
    • G03G5/08214—Silicon-based
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
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    • G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/17—Memory cell being a nanowire transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/18—Memory cell being a nanowire having RADIAL composition
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/08—Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S977/70—Nanostructure
    • Y10S977/773—Nanoparticle, i.e. structure having three dimensions of 100 nm or less
    • Y10S977/774—Exhibiting three-dimensional carrier confinement, e.g. quantum dots
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10S977/778—Nanostructure within specified host or matrix material, e.g. nanocomposite films
    • Y10S977/785—Electrically insulating host material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device

Abstract

Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
PCT/US2005/007709 2004-03-10 2005-03-09 Nano-enabled memory devices and anisotropic charge carrying arrays WO2005089165A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05758741A EP1723676A4 (en) 2004-03-10 2005-03-09 Nano-enabled memory devices and anisotropic charge carrying arrays
JP2007502948A JP4871255B2 (en) 2004-03-10 2005-03-09 Nano-capable memory devices and anisotropic charge transport arrays

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US10/796,413 US20050202615A1 (en) 2004-03-10 2004-03-10 Nano-enabled memory devices and anisotropic charge carrying arrays
US10/796,413 2004-03-10
US96297204A 2004-10-12 2004-10-12
US10/962,972 2004-10-12
US11/018,572 2004-12-21
US11/018,572 US7595528B2 (en) 2004-03-10 2004-12-21 Nano-enabled memory devices and anisotropic charge carrying arrays

Publications (2)

Publication Number Publication Date
WO2005089165A2 WO2005089165A2 (en) 2005-09-29
WO2005089165A3 true WO2005089165A3 (en) 2006-05-04

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US (3) US7382017B2 (en)
EP (1) EP1723676A4 (en)
WO (1) WO2005089165A2 (en)

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