WO2005091714A3 - Apparatus and methods for multi-level sensing in a memory array - Google Patents

Apparatus and methods for multi-level sensing in a memory array Download PDF

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Publication number
WO2005091714A3
WO2005091714A3 PCT/IL2004/001107 IL2004001107W WO2005091714A3 WO 2005091714 A3 WO2005091714 A3 WO 2005091714A3 IL 2004001107 W IL2004001107 W IL 2004001107W WO 2005091714 A3 WO2005091714 A3 WO 2005091714A3
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WO
WIPO (PCT)
Prior art keywords
cell
memory array
sensing
methods
dbl
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Application number
PCT/IL2004/001107
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French (fr)
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WO2005091714A2 (en
Inventor
Oleg Dadashev
Original Assignee
Saifun Semiconductors Ltd
Oleg Dadashev
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Saifun Semiconductors Ltd, Oleg Dadashev filed Critical Saifun Semiconductors Ltd
Publication of WO2005091714A2 publication Critical patent/WO2005091714A2/en
Publication of WO2005091714A3 publication Critical patent/WO2005091714A3/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Abstract

A method for sensing a signal (DBL) received from an array cell within a memory array (10), the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array (10), and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal (cmp). A method is also provided for sensing a memory cell by transforming a signal (DBL) from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell (ref. DBL).
PCT/IL2004/001107 2004-03-29 2004-12-06 Apparatus and methods for multi-level sensing in a memory array WO2005091714A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/810,683 US7142464B2 (en) 2003-04-29 2004-03-29 Apparatus and methods for multi-level sensing in a memory array
US10/810,683 2004-03-29

Publications (2)

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WO2005091714A2 WO2005091714A2 (en) 2005-10-06
WO2005091714A3 true WO2005091714A3 (en) 2006-05-04

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Family Applications (1)

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PCT/IL2004/001107 WO2005091714A2 (en) 2004-03-29 2004-12-06 Apparatus and methods for multi-level sensing in a memory array

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US (2) US7142464B2 (en)
TW (1) TWI379306B (en)
WO (1) WO2005091714A2 (en)

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