WO2005098685A3 - Block-based processing in a packet-based reconfigurable architecture - Google Patents

Block-based processing in a packet-based reconfigurable architecture Download PDF

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Publication number
WO2005098685A3
WO2005098685A3 PCT/US2005/010387 US2005010387W WO2005098685A3 WO 2005098685 A3 WO2005098685 A3 WO 2005098685A3 US 2005010387 W US2005010387 W US 2005010387W WO 2005098685 A3 WO2005098685 A3 WO 2005098685A3
Authority
WO
WIPO (PCT)
Prior art keywords
packet
block
reconfigurable architecture
processing
based processing
Prior art date
Application number
PCT/US2005/010387
Other languages
French (fr)
Other versions
WO2005098685A2 (en
Inventor
Vicki Tsai
Inching Chen
Original Assignee
Intel Corp
Vicki Tsai
Inching Chen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Vicki Tsai, Inching Chen filed Critical Intel Corp
Priority to EP05736836A priority Critical patent/EP1730661A2/en
Publication of WO2005098685A2 publication Critical patent/WO2005098685A2/en
Publication of WO2005098685A3 publication Critical patent/WO2005098685A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

A reconfigurable circuit including a heterogeneous mix of processing elements is configured to use variable packet sizes.
PCT/US2005/010387 2004-03-30 2005-03-25 Block-based processing in a packet-based reconfigurable architecture WO2005098685A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05736836A EP1730661A2 (en) 2004-03-30 2005-03-25 Block-based processing in a packet-based reconfigurable architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/813,461 US20050229139A1 (en) 2004-03-30 2004-03-30 Block-based processing in a packet-based reconfigurable architecture
US10/813,461 2004-03-30

Publications (2)

Publication Number Publication Date
WO2005098685A2 WO2005098685A2 (en) 2005-10-20
WO2005098685A3 true WO2005098685A3 (en) 2006-02-02

Family

ID=34966373

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/010387 WO2005098685A2 (en) 2004-03-30 2005-03-25 Block-based processing in a packet-based reconfigurable architecture

Country Status (4)

Country Link
US (1) US20050229139A1 (en)
EP (1) EP1730661A2 (en)
TW (1) TW200604867A (en)
WO (1) WO2005098685A2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050149890A1 (en) * 2003-12-29 2005-07-07 Tsai Vicki W. Programming reconfigurable packetized networks
US7424698B2 (en) * 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
US20050223110A1 (en) * 2004-03-30 2005-10-06 Intel Corporation Heterogeneous building block scalability
US7073159B2 (en) * 2004-03-31 2006-07-04 Intel Corporation Constraints-directed compilation for heterogeneous reconfigurable architectures
US20060004902A1 (en) * 2004-06-30 2006-01-05 Siva Simanapalli Reconfigurable circuit with programmable split adder
US7568059B2 (en) * 2004-07-08 2009-07-28 Asocs Ltd. Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards
EP1645963B1 (en) * 2004-10-07 2014-05-14 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Determining sizes of memory frames for dynamic memory allocation limiting internal fragmentation
US20090327546A1 (en) * 2005-03-03 2009-12-31 Gaby Guri System for and method of hand-off between different communication standards
JP2008306419A (en) * 2007-06-07 2008-12-18 Sony Corp Transmission device and method, and program
JP5163332B2 (en) * 2008-07-15 2013-03-13 富士通セミコンダクター株式会社 Design program, design apparatus, and design method
US9841954B1 (en) * 2016-08-10 2017-12-12 Dspace Digital Signal Processing And Control Engineering Gmbh Method and system for automatic code generation

Citations (1)

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EP1315335A1 (en) * 2001-11-19 2003-05-28 AT&T Corp. Adaptive MAC packets fragmentation and rate selection for 802.11 wireless networks

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US20050149890A1 (en) * 2003-12-29 2005-07-07 Tsai Vicki W. Programming reconfigurable packetized networks
US7424698B2 (en) * 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
US20050223110A1 (en) * 2004-03-30 2005-10-06 Intel Corporation Heterogeneous building block scalability
US7073159B2 (en) * 2004-03-31 2006-07-04 Intel Corporation Constraints-directed compilation for heterogeneous reconfigurable architectures

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CHANDRANMENON G P ET AL: "RECONSIDERING FRAGMENTATION AND REASSEMBLY", PROCEEDINGS OF THE 17TH ANNUAL ACM SYMPOSIUM ON PRINCIPLES OF DISTRIBUTED COMPUTING.PODC 1998. PUERTO VALLARTA, MEXICO, JUNE 28 - JULY 2, 1998, ACM SIGACT - SIGMOD SYMPOSIUM ON PRINCIPLES OF DISTRIBUTED COMPUTING, NEW YORK, NY : ACM, US, 28 June 1998 (1998-06-28), pages 21 - 29, XP002921718, ISBN: 0-89791-877-7 *
COMPTON K HAUCK: "Reconfigurable computing: A survey of systems and software", ACM COMPUTING SURVEYS, ACM, NEW YORK, US, US, vol. 34, no. 2, June 2002 (2002-06-01), pages 171AND210, XP002957662, ISSN: 0360-0300 *
E. TSUI ET AL: "A New Distributed DSP Architecture Based on the Intel IXS for Wireless Client and Infrastructure (Hot Chips 14, Session 7: Digital Signal Processors,20 August 2002)", HOT CHIPS 14 : CONFERENCE RECORD ; AUGUST 18 - 20, 2002, MEMORIAL AUDITORIUM, STANFORD UNIVERSITY, PALO ALTO, CALIFORNIA / SPONSORED BY THE IEEE COMPUTER SOCIETY TECHNICAL COMMITTEE ON MICROPROCESSORS AND MICROCOMPUTERS, 2002, Palo Alto, Calif., pages 1 - 17, XP009053119 *
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Also Published As

Publication number Publication date
EP1730661A2 (en) 2006-12-13
TW200604867A (en) 2006-02-01
US20050229139A1 (en) 2005-10-13
WO2005098685A2 (en) 2005-10-20

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