WO2005098923A1 - Methods of forming trench isolation regions - Google Patents
Methods of forming trench isolation regions Download PDFInfo
- Publication number
- WO2005098923A1 WO2005098923A1 PCT/US2005/010197 US2005010197W WO2005098923A1 WO 2005098923 A1 WO2005098923 A1 WO 2005098923A1 US 2005010197 W US2005010197 W US 2005010197W WO 2005098923 A1 WO2005098923 A1 WO 2005098923A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- masking material
- trench
- amorphous carbon
- layer
- isolation
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Definitions
- This invention relates to methods of forming trench isolation region s.
- trench isolation regions are formed by depositing or otherwise forming a masking layer over a semiconductor substrate. Trenches are etched through the -masking layer into the semiconductor substrate, with the trenches being subsequently filled with insulative material.
- Exemplary masking materials for trench isolation include silicon nitride and polysilicon with or without an underlying pad oxide layer.
- trench isolation material which is formed in the isolation trenches typically includes deposition of insulative material over the masking material and to within the trenches, typically over-filling them.
- the isolation material is typically then polished back, for example by chemical-mechanical polishing, at least to the outer surface of the masking material.
- the masking material is then typically selectively etched away from the substrate leaving, at least at this point in the process, insulative isolation material filling and extending outwardly of the trench isolation regions.
- the masking material comprises silicon nitride and where silicon nitride is also utilized to line the trenches
- the nitride liner might get etched as well. This can cause nitride liner recessing within the trenches relative to the outer surface of the semiconductive material of the substrate. This can result in gate oxide wrap-around that can degrade the transistors which are ultimately fabricated. While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.
- a masking material is formed over a semiconductor substrate.
- the masking material comprises at least one of tungsten, titanium nitride and amorphous carbon.
- An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate.
- a trench isolation material is formed within the isolation trench and over the masking material outside of the trench effective to overfill the isolation trench.
- the trench isolation material is polished at least to an outermost surface of the at least one of tungsten, titanium nitride and amorphous carbon of the masking material.
- the at least one of tungsten, titanium nitride and amorphous carbon is/are etched from the substrate.
- a method of forming a trench isolation region comprises forming masking material over a semiconductor substrate, where at least some of the masking material is oxidizable. An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate. The opening and the isolation trench have respective sidewalls. The substrate is exposed to oxidizing conditions effective to oxidize the masking material sidewalls at a greater rate than which the sidewalls of the semiconductive material are oxidized. Trench isolation material is formed within the isolation trench.
- a method of forming a trench isolation region comprises forming a masking material over a semiconductor substrate.
- An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate.
- a silicon nitride comprising layer is deposited within the isolation trench and over the masking material effective to line the trench.
- Trench isolation material is deposited over the silicon nitride comprising layer within the isolation trench and over the masking material outside of the trench.
- the trench isolation material and the silicon nitride comprising layer are polished at least to the masking material.
- the masking material and the trench isolation material are removed relative to the silicon nitride comprising layer from outwardly of semiconductive material of the semiconductor substrate effective to leave a portion of the silicon nitride comprising layer projecting outwardly from semiconductive material of the semiconductor substrate.
- Fig. 1 is a diagrammatic section view of a semiconductor wafer fragment in process in accordance with an aspect of the invention.
- Fig. 2 is a view of the Fig. 1 wafer fragment at a processing subsequent to that depicted by Fig. 1.
- Fig. 3 is a view of the Fig. 2 wafer fragment at a processing subsequent to that depicted by Fig. 2.
- Fig. 4 is a view of the Fig. 3 wafer fragment at a processing subsequent to that depicted by Fig. 3.
- Fig. 5 is a view of the Fig. 4 wafer fragment at a processing subsequent to that depicted by Fig. 4.
- Fig. 6 is a diagrammatic section view of another semiconductor wafer fragment in process in accordance with an aspect of the invention.
- Fig. 7 is a diagrammatic section view of another semiconductor wafer fragment in process in accordance with an aspect of the invention.
- Fig. 8 is a view of the Fig. 7 wafer fragment at a processing subsequent to that depicted by Fig. 7.
- Fig. 9 is a view of the Fig. 8 wafer fragment at a processing subsequent to that depicted by Fig. 8.
- Fig. 10 is a diagrammatic section view of another semiconductor wafer fragment in process in accordance with an aspect of the invention.
- Fig. 11 is a view of the Fig. 10 wafer fragment at a processing subsequent to that depicted by Fig. 10.
- Fig. 10 is a diagrammatic section view of another semiconductor wafer fragment in process in accordance with an aspect of the invention.
- Fig. 11 is a view of the Fig. 10 wafer fragment at a processing subsequent to that depicted by
- FIG. 12 is a view of the Fig. 11 wafer fragment at a processing subsequent to that depicted by Fig. 11.
- Fig. 13 is a view of the Fig. 12 wafer fragment at a processing subsequent to that depicted by Fig. 12.
- Fig. 14 is a diagrammatic section view of another semiconductor wafer fragment in process in accordance with an aspect of the invention.
- Fig. 15 is a view of the Fig. 14 wafer fragment at a processing subsequent to that depicted by Fig. 14.
- Fig. 16 is a diagrammatic section view of another semiconductor wafer fragment in process in accordance with an aspect of the invention.
- Fig. 17 is a view of the Fig. 16 wafer fragment at a processing subsequent to that depicted by Fig. 16.
- Fig. 1 depicts a semiconductor substrate 10 comprising bulk semiconductive material 12, for example monocrystalline silicon.
- bulk semiconductive material 12 for example monocrystalline silicon.
- semiconductor substrate or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
- substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
- layer encompasses both the singular and the plural.
- a masking material 14 is formed over and comprises semiconductor substrate 10. In the depicted exemplary embodiment, such comprises a pad oxide layer 16 and a layer 18 formed thereover.
- An exemplary thickness for layer 16 is from 20 Angstroms to 75 Angstroms, with 60 Angstroms being a preferred specific example.
- Masking material layer 18 preferably has a thickness of from 200 Angstroms to 1 ,500 Angstroms, with 5O0 Angstroms being a specific preferred example.
- Masking material layer 18 comprises at least one of tungsten (in elemental and/or alloy form), titanium nitride and amorphous carbon. In one embodiment where amorphous carbon is utilized, it might comprise at least one of boron and nitrogen. Further in one exemplary embodiment with respect to amorphous carbon, such might comprise a layer that is transparent to visible light.
- an amorphous carbon comprising layer that is transparent to visible light means that the amorphous carbon comprising layer has a substantially low absorption coefficient (k) in which k has a range between about 0.15 and about 0.001 (or lower) at wavelength 633 nm.
- the amorphous carbon comprising layer transparent to visible light range radiation might be formed at a temperature from about 200°C to about 450°C, with an exemplary preferred pressure range being from about 3 Torr to about 7 Torr. A specific preferred example is 375°C and 5 Torr.
- Such deposition preferably occurs by plasma generation, with an exemplary power applied to the showerhead being from 500 watts to 1100 watts, with 800 watts being a specific preferred example.
- An exemplary flow rate for the C 3 H 6 is from 400 seem to 2400 seem, with 1450 seem being a specific preferred example.
- An exemplary preferred flow rate for the helium is from 250 seem to 650 seem, with 450 seem being a specific preferred example.
- An exemplary preferred spacing of the showerhead/substrate support-susceptor is 240 mils.
- Exemplary additional or other hydrocarbon gases utilizable in producing transparency as described include CH 4 , C 2 H 2 , C 2 H 4 , C 2 H 6 , and C 3 H 8 .
- a preferred gas provided during such deposition might be either one gas or a combination of various gases, including the absence of any helium. Further, lower temperature depositions can result in greater transparency than higher temperature depositions.
- an exemplary deposition thickness over the substrate for the amorphous carbon comprising layer is 4000 Angstroms.
- an exemplary boron source gas is B 2 H6 at an exemplary flow rate of 1500 seem, and an exemplary nitrogen source gas is N 2 at an exemplary flow rate of 1 000 seem.
- an exemplary concentration range in the layer for boron is from 0.5% atomic to 60% atomic.
- an exemplary concentration range in the layer for nitrogen is from 0.1 % atomic to 20% atomic.
- Hard masking and/or antireflective coating layers might be utilized over masking material layer 18.
- masking material 14 is void of silicon nitride.
- an opening 20 has been formed through masking material 14 into semiconductor substrate 10 effective to form an isolation trench 22 within semiconductive material 12 of semiconductor substrate 10.
- An exemplary preferred manner of doing so is by photolithographic patterning, development and etching, whether using existing or yet-to-be developed technologies.
- trench isolation material 24 has been formed within isolation trench 22 and over masking material 14 outside of trench 22 effective to overfill isolation trench 22.
- An exemplary preferred material is silicon dioxide, for example high density plasma deposited silicon dioxide, and further, for example, with or without thermal oxide and/or silicon nitride trench liner materials. Referring to Fig.
- trench isolation material 24 has been polished at least to an outermost surface of the at least one of tungsten, tungsten nitride and amorphous carbon material 18 of masking material 14.
- Exemplary preferred techniques include chemical-mechanical polishing, for example utilizing any existing or yet-to-be developed CMP tool and slurries.
- the at least one of tungsten, titanium nitride and amorphous carbon material 18 has been etched from the substrate.
- the etching is conducted selectively to at least some of trench isolation material 24, with the etching as shown being selective to all of trench isolation material 24.
- a selective etch or removal removes one material compared to another at a ratio of at least 2: 1.
- the exemplary pad oxide layer 16 might also be removed, as well as some or all of material 24 from outwardly of isolation trench 22.
- an alternate exemplary embodiment to that depicted by Fig. 4 is illustrated in Fig. 6 in connection with a semiconductor substrate 10a.
- Masking material 14a comprises at least two of tungsten, titanium nitride and amorphous carbon with, for example, an outer layer 19 of at least one of such materials being received outwardly of masking material layer 18a which comprises another of at least one of tungsten, titanium nitride and amorphous carbon.
- material 19 preferably comprises amorphous carbon and material 18a comprises at least one of tungsten and tungsten nitride.
- material 18a comprises at least one of tungsten and tungsten nitride.
- FIGs. 7-9 in connection with a semiconductor substrate 10b. Like numerals from the first- described embodiment are utilized where appropriate, with differences being indicated with different numerals or with the suffix "b".
- trench isolation material 24b has been formed within isolation trench 22 and over masking material 14 outside of trench 22 effective to overfill isolation trench 22.
- Trench isolation material 24b includes a silicon nitride comprising layer 30 and at least one material 32 other than silicon nitride formed thereover.
- An exemplary thickness for layer 30 is 70 Angstroms, and an exemplary preferred material for layer 32 is high density plasma deposited silicon dioxide. Of course, a thermal silicon dioxide layer might be formed on trench sidewalls 22 before or after deposition of layer 30.
- trench isolation material 24b has been polished to at least an outermost surface of the at least one of tungsten, titanium nitride and amorphous carbon material 18 of masking material 14.
- the at least one of tungsten, titanium nitride and amorphous carbon material 18 has been etched from the substrate substantially selectively to silicon nitride comprising layer 30.
- an exemplary etching chemistry for etching elemental tungsten, amorphous carbon, and/or TiN selectively relative to silicon nitride comprises H 2 SO 4 and H2O 2 at a 9:1 ratio by weight at 140°C.
- an exemplary etching chemistry for etching elemental tungsten and/or TiN selectively relative to silicon nitride comprises H 2 O, HCI, and H 2 O2 at a 20:4:1 ratio by weight at 70°C.
- Yet another exemplary method of forming a trench isolation region is described in connection with Figs. 10-13 in connection with a semiconductor substrate 10c.
- a masking material 14c has been formed over semiconductor substrate 12. Such is depicted as comprising a pad oxide layer 16 and an overlyi ng material 18c, at least some of which is oxidizable. Thicknesses are preferably as described above in connection with the first described embodiment. Exemplary materials include those as described above, specifically tungsten, amorphous carbon, and/or tungsten nitride. An additional alternate exemplary material is polysilicon, whether updoped or doped with another material or materials such as boron and/or phosphorus.
- masking material 14c is void of silicon nitride.
- an opening 20 is formed through masking material 14c and into semiconductor substrate 10c effective to form an isolation trench 22 within semiconductive material 12 of semiconductor substrate 1 Oc.
- Mask opening 20 has sidewalls 34, and isolation trench 22 has sidewalls 36.
- substrate 10c has been exposed to oxidizing conditions effective to oxidize masking material sidewalls 34 at a greater rate than that at which sidewalls 36 of semiconductor material 12 are oxidized.
- an oxide layer 39 is formed which is laterally thicker over the masking material sidewalls within opening 20 than over the sidewalls of semiconductive material 12.
- trench isolation material 24c has been formed within isolation trench 22. Such might comprise one or more materials, with material 39 also comprising trench isolation material. Processing might otherwise continue as described above in connection with the first-described embodiments, for example whereby materials 24c, 39 and 14c are removed outwardly from semiconductive material 12, for example as shown in Fig. 13.
- An alternate exemplary embodiment semiconductor substrate 10d is depicted in Figs. 14 and 15. Like numerals from the Figs. 10-13 embodiment are utilized where appropriate, with differences being indicated with different numerals or with the suffix "d". Referring to Fig.
- Semiconductor substrate 10d is shown. as being for ed to comprise trench isolation material 24d comprising a silicon nitride comprising layer 42 received over (and "on", as shown) the oxidized masking material sidewalls and oxidized semiconductive material sidewalls (i.e., on material 39).
- An exemplary additional material 44 is formed thereover, for example high density plasma deposited silicon dioxide. Referring to Fig . 15, and by way of example only, subsequent processing is depicted whereby al I material has been removed outwardly from material 12 of semiconductor substrate 10d. Yet another preferred method of forming a trench isolation region in accordance with aspects of the invention is described in connection with a semiconductor substrate 10e in Figs. 16 and 17.
- a masking material 14 is formed over a semiconductor substrate 12. Any material is contemplated, and including for example those described above, and preferably with such masking material being void of silicon nitride.
- An opening 20 has been formed through masking material 14 and into semiconductor material 12 effective to form an isolation trench 22 within material 12 of semiconductor substrate 10e.
- a silicon nitride comprising layer 50 has been deposited within isolation trench 22 and over masking material 14 effective to line trench 22.
- An exemplary thickness for layer 50 is from 10 Angstroms to 150 Angstroms.
- Trench isolation material 24 has been deposited over silicon nitride comprising layer 50 within isolation trench 22 and over masking material 14 outside of trench 22.
- Exemplary preferred materials are as described above, namely high density plasma deposited silicon dioxide.
- Fig. 16 depicts such trench isolation material 24 and silicon nitride comprising layer 50 as having been polished at least to masking material 14.
- masking material 14 and trench isolation material 24 have been removed relative to silicon nitride comprising layer 50 from outwardly of semiconductive material 12 of semiconductive substrate 10e effective to leave a portion of silicon nitride comprising layer 50 projecting outwardly of semiconductive material 12 of semiconductive substrate 10e.
- An exemplary technique for such processing, where for example material 24 is silicon dioxide and material 18 is polysilicon includes dipping or spraying with a 25:1 by volume solution of H 2 O:HF at room temperature and p ressure conditions.
- a 25:1 by volume solution of H 2 O:HF at room temperature and p ressure conditions.
- such a solution could be utilized initially to strip any native oxide overlying material 18 followed by etching polysilicon with tetramethyl ammonium hydroxide (TMAH).
- TMAH tetramethyl ammonium hydroxide
- An exemplary such solution is 2.25% TMAH by weight in deionized water at 30°C.
Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05731310A EP1738403A1 (en) | 2004-04-01 | 2005-03-25 | Methods of forming trench isolation regions |
CN2005800104955A CN1938831B (en) | 2004-04-01 | 2005-03-25 | Methods of forming trench isolation regions |
JP2007506404A JP2007531324A (en) | 2004-04-01 | 2005-03-25 | Method for forming trench isolation region |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/817,029 US7015113B2 (en) | 2004-04-01 | 2004-04-01 | Methods of forming trench isolation regions |
US10/817,029 | 2004-04-01 |
Publications (2)
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WO2005098923A1 true WO2005098923A1 (en) | 2005-10-20 |
WO2005098923A8 WO2005098923A8 (en) | 2006-12-07 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/US2005/010197 WO2005098923A1 (en) | 2004-04-01 | 2005-03-25 | Methods of forming trench isolation regions |
Country Status (7)
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US (3) | US7015113B2 (en) |
EP (1) | EP1738403A1 (en) |
JP (1) | JP2007531324A (en) |
KR (1) | KR100870616B1 (en) |
CN (1) | CN1938831B (en) |
SG (2) | SG148896A1 (en) |
WO (1) | WO2005098923A1 (en) |
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-
2004
- 2004-04-01 US US10/817,029 patent/US7015113B2/en not_active Expired - Lifetime
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2005
- 2005-03-25 KR KR1020067019876A patent/KR100870616B1/en active IP Right Grant
- 2005-03-25 CN CN2005800104955A patent/CN1938831B/en active Active
- 2005-03-25 SG SG200704899-4A patent/SG148896A1/en unknown
- 2005-03-25 SG SG200704900-0A patent/SG148897A1/en unknown
- 2005-03-25 WO PCT/US2005/010197 patent/WO2005098923A1/en not_active Application Discontinuation
- 2005-03-25 JP JP2007506404A patent/JP2007531324A/en active Pending
- 2005-03-25 EP EP05731310A patent/EP1738403A1/en not_active Withdrawn
- 2005-08-22 US US11/209,081 patent/US7279396B2/en active Active
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7279396B2 (en) | 2004-04-01 | 2007-10-09 | Micron Technology, Inc. | Methods of forming trench isolation regions with nitride liner |
US7402498B2 (en) | 2004-04-01 | 2008-07-22 | Micron Technology, Inc. | Methods of forming trench isolation regions |
WO2010025024A1 (en) * | 2008-08-27 | 2010-03-04 | Advanced Micro Devices, Inc. | Semiconductor device with isolation trench liner, and related fabrication methods |
US7998832B2 (en) | 2008-08-27 | 2011-08-16 | Advanced Micro Devices, Inc. | Semiconductor device with isolation trench liner, and related fabrication methods |
US8716828B2 (en) | 2008-08-27 | 2014-05-06 | Advanced Micro Devices, Inc. | Semiconductor device with isolation trench liner |
KR101810111B1 (en) | 2008-08-27 | 2017-12-18 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | Semiconductor device with isolation trench liner, and related fabrication methods |
Also Published As
Publication number | Publication date |
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SG148896A1 (en) | 2009-01-29 |
EP1738403A1 (en) | 2007-01-03 |
CN1938831A (en) | 2007-03-28 |
US20060003544A1 (en) | 2006-01-05 |
US20050227450A1 (en) | 2005-10-13 |
US20060003543A1 (en) | 2006-01-05 |
KR20060130680A (en) | 2006-12-19 |
SG148897A1 (en) | 2009-01-29 |
US7279396B2 (en) | 2007-10-09 |
KR100870616B1 (en) | 2008-11-25 |
CN1938831B (en) | 2011-01-12 |
WO2005098923A8 (en) | 2006-12-07 |
US7015113B2 (en) | 2006-03-21 |
JP2007531324A (en) | 2007-11-01 |
US7402498B2 (en) | 2008-07-22 |
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