WO2005104189A3 - System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques - Google Patents

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques Download PDF

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Publication number
WO2005104189A3
WO2005104189A3 PCT/US2005/007301 US2005007301W WO2005104189A3 WO 2005104189 A3 WO2005104189 A3 WO 2005104189A3 US 2005007301 W US2005007301 W US 2005007301W WO 2005104189 A3 WO2005104189 A3 WO 2005104189A3
Authority
WO
WIPO (PCT)
Prior art keywords
resolution enhancement
enhancement techniques
manufacture
integrated circuit
circuit device
Prior art date
Application number
PCT/US2005/007301
Other languages
French (fr)
Other versions
WO2005104189A2 (en
Inventor
Cyrus E Tabery
Todd P Lukanc
Chris Haidinyak
Luigi Capodieci
Carl P Babcock
Hung-Eil Kim
Christopher A Spence
Original Assignee
Advanced Micro Devices Inc
Cyrus E Tabery
Todd P Lukanc
Chris Haidinyak
Luigi Capodieci
Carl P Babcock
Hung-Eil Kim
Christopher A Spence
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc, Cyrus E Tabery, Todd P Lukanc, Chris Haidinyak, Luigi Capodieci, Carl P Babcock, Hung-Eil Kim, Christopher A Spence filed Critical Advanced Micro Devices Inc
Publication of WO2005104189A2 publication Critical patent/WO2005104189A2/en
Publication of WO2005104189A3 publication Critical patent/WO2005104189A3/en

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Abstract

A method of selecting a plurality of lithography process parameters for patterning a layout (300) on a wafer includes simulating (310) how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified (320) based on manufacturability. RETs that provide optimal manufacturability can be selected (330). In this manner, the simulation tool (210) can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
PCT/US2005/007301 2004-04-02 2005-03-07 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques WO2005104189A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/816,764 US7269804B2 (en) 2004-04-02 2004-04-02 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
US10/816,764 2004-04-02

Publications (2)

Publication Number Publication Date
WO2005104189A2 WO2005104189A2 (en) 2005-11-03
WO2005104189A3 true WO2005104189A3 (en) 2006-04-27

Family

ID=34963129

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/007301 WO2005104189A2 (en) 2004-04-02 2005-03-07 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

Country Status (3)

Country Link
US (2) US7269804B2 (en)
TW (1) TW200539272A (en)
WO (1) WO2005104189A2 (en)

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US7765518B2 (en) * 2008-03-20 2010-07-27 International Business Machines Corporation System and method for implementing optical rule checking to identify and quantify corner rounding errors
US8321818B2 (en) * 2009-06-26 2012-11-27 International Business Machines Corporation Model-based retargeting of layout patterns for sub-wavelength photolithography
US8146026B2 (en) 2009-11-17 2012-03-27 International Business Machines Corporation Simultaneous photolithographic mask and target optimization
US8230372B2 (en) * 2009-12-03 2012-07-24 International Business Machines Corporation Retargeting for electrical yield enhancement
US8331646B2 (en) 2009-12-23 2012-12-11 International Business Machines Corporation Optical proximity correction for transistors using harmonic mean of gate length
US8397183B2 (en) * 2010-02-03 2013-03-12 International Business Machines Corporation Generation of asymmetric circuit devices
US8381141B2 (en) 2010-10-28 2013-02-19 International Business Machines Corporation Method and system for comparing lithographic processing conditions and or data preparation processes
US8438505B2 (en) * 2011-01-21 2013-05-07 Taiwan Semicondcutor Manufacturing Company, Ltd. Method for improving accuracy of parasitics extraction considering sub-wavelength lithography effects
US8745553B2 (en) * 2012-08-23 2014-06-03 Globalfoundries Inc. Method and apparatus for applying post graphic data system stream enhancements
US9811619B2 (en) * 2013-10-22 2017-11-07 Texas Instruments Incorporated Low drop-out voltage regulator modeling systems and methods
US10656517B2 (en) * 2016-01-20 2020-05-19 Mentor Graphics Corporation Pattern correction in multiple patterning steps
JP6559601B2 (en) * 2016-03-23 2019-08-14 信越半導体株式会社 Detection apparatus and detection method
CN110826248B (en) * 2019-11-18 2023-10-20 杭州涂鸦信息技术有限公司 Method and system for simulating infrared camera dark angle based on light source database

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Also Published As

Publication number Publication date
US7657864B2 (en) 2010-02-02
US20070209030A1 (en) 2007-09-06
TW200539272A (en) 2005-12-01
US7269804B2 (en) 2007-09-11
WO2005104189A2 (en) 2005-11-03
US20050229125A1 (en) 2005-10-13

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