WO2005119440A3 - Methods and systems for mixed-mode physical synthesis in electronic design automation - Google Patents

Methods and systems for mixed-mode physical synthesis in electronic design automation Download PDF

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Publication number
WO2005119440A3
WO2005119440A3 PCT/US2005/019187 US2005019187W WO2005119440A3 WO 2005119440 A3 WO2005119440 A3 WO 2005119440A3 US 2005019187 W US2005019187 W US 2005019187W WO 2005119440 A3 WO2005119440 A3 WO 2005119440A3
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WO
WIPO (PCT)
Prior art keywords
clusters
objects
clustering
systems
methods
Prior art date
Application number
PCT/US2005/019187
Other languages
French (fr)
Other versions
WO2005119440A2 (en
Inventor
Zhong-Qing Shang
Original Assignee
Tera Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tera Systems Inc filed Critical Tera Systems Inc
Publication of WO2005119440A2 publication Critical patent/WO2005119440A2/en
Publication of WO2005119440A3 publication Critical patent/WO2005119440A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Abstract

Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to reduce or minimize interconnections between clusters. Clustering optionally includes multi-level clustering. The clusters, and any unclustered objects, are floorplanned. Floorplanning positions the clusters so as to reduce or minimize the length of interconnections between the clusters. Objects within the clusters are then placed within the area assigned to the corresponding clusters. Placement optionally utilizes placement-based wire load models to accurately predict timing issues. A bottoms-up procedure is optionally performed during clustering and/or floorplanning, whereby area and/or size constraints of clustered objects are taken into account.
PCT/US2005/019187 2004-06-01 2005-06-01 Methods and systems for mixed-mode physical synthesis in electronic design automation WO2005119440A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57542004P 2004-06-01 2004-06-01
US60/575,420 2004-06-01

Publications (2)

Publication Number Publication Date
WO2005119440A2 WO2005119440A2 (en) 2005-12-15
WO2005119440A3 true WO2005119440A3 (en) 2007-11-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/019187 WO2005119440A2 (en) 2004-06-01 2005-06-01 Methods and systems for mixed-mode physical synthesis in electronic design automation

Country Status (2)

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US (1) US7409658B2 (en)
WO (1) WO2005119440A2 (en)

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Publication number Priority date Publication date Assignee Title
US7296252B2 (en) * 2004-07-22 2007-11-13 International Business Machines Corporation Clustering techniques for faster and better placement of VLSI circuits
US7305640B1 (en) * 2004-11-12 2007-12-04 Altera Corporation Programmable soft macro memory using gate array base cells
US7441208B1 (en) * 2005-09-13 2008-10-21 Altera Corporation Methods for designing integrated circuits
US7996797B1 (en) 2006-08-16 2011-08-09 Altera Corporation Method and apparatus for performing multiple stage physical synthesis
US8359558B2 (en) * 2010-03-16 2013-01-22 Synopsys, Inc. Modeling of cell delay change for electronic design automation
US8516412B2 (en) 2011-08-31 2013-08-20 International Business Machines Corporation Soft hierarchy-based physical synthesis for large-scale, high-performance circuits
US8539400B2 (en) * 2011-09-29 2013-09-17 International Business Machines Corporation Routability using multiplexer structures
US8484589B2 (en) * 2011-10-28 2013-07-09 Apple Inc. Logical repartitioning in design compiler
US10409945B1 (en) 2015-06-29 2019-09-10 Cadence Design Systems, Inc. Methods, systems, and computer program product for connectivity verification of electronic designs
US9734278B1 (en) * 2015-06-29 2017-08-15 Cadence Design System, Inc. Methods, systems, and articles of manufacture for automatic extraction of connectivity information for implementation of electronic designs
TWI718486B (en) * 2019-02-27 2021-02-11 瑞昱半導體股份有限公司 Ic layout design method
US10831955B1 (en) 2019-11-19 2020-11-10 International Business Machines Corporation Prediction of closure feasibility in microprocessor design

Citations (2)

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US20020087940A1 (en) * 2000-09-06 2002-07-04 Greidinger Yaacov I. Method for designing large standard-cell based integrated circuits
US6651235B2 (en) * 2001-10-30 2003-11-18 Cadence Design Systems, Inc. Scalable, partitioning integrated circuit layout system

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US5566078A (en) * 1993-05-26 1996-10-15 Lsi Logic Corporation Integrated circuit cell placement using optimization-driven clustering
US6145117A (en) * 1998-01-30 2000-11-07 Tera Systems Incorporated Creating optimized physical implementations from high-level descriptions of electronic design using placement based information
BR9914200A (en) * 1998-09-30 2002-01-22 Cadence Design Systems Inc Methods for designing a circuit system, for expanding an existing methodology for assessing the feasibility of a circuit design, for performing a feasibility assessment for a circuit design, for refining a first decision rule for a circuit design, to form a second decision rule for a circuit design, for organizing a designer's experience data for a plurality of pre-designed circuit blocks, for increasing glue logic distribution efficiency and for distributing a plurality of logic elements of glue between design blocks and distribute glue logic for execution in an integrated circuit device design scheme, to convert a circuit block-specific interface, to select a circuit collector, to design a device that incorporates the enable a device test to verify the correct operation of a and to develop a behavioral test bench, collar interface and interface system
US6415426B1 (en) * 2000-06-02 2002-07-02 Incentia Design Systems, Inc. Dynamic weighting and/or target zone analysis in timing driven placement of cells of an integrated circuit design
US6588003B1 (en) * 2001-06-26 2003-07-01 Lsi Logic Corporation Method of control cell placement for datapath macros in integrated circuit designs
US6754877B1 (en) * 2001-12-14 2004-06-22 Sequence Design, Inc. Method for optimal driver selection
US7149991B2 (en) * 2002-05-30 2006-12-12 Nec Electronics America, Inc. Calibrating a wire load model for an integrated circuit
US6785875B2 (en) * 2002-08-15 2004-08-31 Fulcrum Microsystems, Inc. Methods and apparatus for facilitating physical synthesis of an integrated circuit design
US7036102B2 (en) * 2003-10-27 2006-04-25 Lsi Logic Corporation Process and apparatus for placement of cells in an IC during floorplan creation
US7100140B2 (en) * 2003-12-23 2006-08-29 International Business Machines Corporation Generation of graphical congestion data during placement driven synthesis optimization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020087940A1 (en) * 2000-09-06 2002-07-04 Greidinger Yaacov I. Method for designing large standard-cell based integrated circuits
US6651235B2 (en) * 2001-10-30 2003-11-18 Cadence Design Systems, Inc. Scalable, partitioning integrated circuit layout system

Also Published As

Publication number Publication date
US7409658B2 (en) 2008-08-05
WO2005119440A2 (en) 2005-12-15
US20050268267A1 (en) 2005-12-01

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