WO2005119686A3 - Method of increasing ddr memory bandwidth in ddr sdram modules - Google Patents

Method of increasing ddr memory bandwidth in ddr sdram modules Download PDF

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Publication number
WO2005119686A3
WO2005119686A3 PCT/US2005/018679 US2005018679W WO2005119686A3 WO 2005119686 A3 WO2005119686 A3 WO 2005119686A3 US 2005018679 W US2005018679 W US 2005018679W WO 2005119686 A3 WO2005119686 A3 WO 2005119686A3
Authority
WO
WIPO (PCT)
Prior art keywords
bandwidth
ddr
read command
increasing
ddr memory
Prior art date
Application number
PCT/US2005/018679
Other languages
French (fr)
Other versions
WO2005119686A2 (en
Inventor
Ryan M Petersen
Franz Michael Shuette
Original Assignee
Ocz Technology
Ryan M Petersen
Franz Michael Shuette
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ocz Technology, Ryan M Petersen, Franz Michael Shuette filed Critical Ocz Technology
Priority to EP05760508.1A priority Critical patent/EP1776641B1/en
Priority to AU2005251173A priority patent/AU2005251173B2/en
Publication of WO2005119686A2 publication Critical patent/WO2005119686A2/en
Publication of WO2005119686A3 publication Critical patent/WO2005119686A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules (400). DDR memory (420) has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the termination of an ongoing data burst (510) By using the Variable Early Read command the effect of the CAS latency is minimized in terms of the effect on bandwidth. The enhanced bandwidth technology achieved with this invention optimizes the remaining two access latencies (tRP and tRCD) for optimal bandwidth. These optimizations in the SPD (500) allow for much better bandwidth in real world applications.
PCT/US2005/018679 2004-05-26 2005-05-26 Method of increasing ddr memory bandwidth in ddr sdram modules WO2005119686A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05760508.1A EP1776641B1 (en) 2004-05-26 2005-05-26 Method of increasing ddr memory bandwidth in ddr sdram modules
AU2005251173A AU2005251173B2 (en) 2004-05-26 2005-05-26 Method of increasing DDR memory bandwidth in DDR SDRAM modules

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52157004P 2004-05-26 2004-05-26
US60/521,570 2004-05-26

Publications (2)

Publication Number Publication Date
WO2005119686A2 WO2005119686A2 (en) 2005-12-15
WO2005119686A3 true WO2005119686A3 (en) 2007-01-11

Family

ID=35463605

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/018679 WO2005119686A2 (en) 2004-05-26 2005-05-26 Method of increasing ddr memory bandwidth in ddr sdram modules

Country Status (5)

Country Link
US (1) US8151030B2 (en)
EP (1) EP1776641B1 (en)
AU (1) AU2005251173B2 (en)
TW (1) TWI380314B (en)
WO (1) WO2005119686A2 (en)

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US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
GB2444663B (en) 2005-09-02 2011-12-07 Metaram Inc Methods and apparatus of stacking drams
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
JP2007249837A (en) * 2006-03-17 2007-09-27 Nec Electronics Corp Memory controller, memory control method, and portable device
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8171181B2 (en) * 2008-05-05 2012-05-01 Micron Technology, Inc. Memory module with configurable input/output ports
EP2441007A1 (en) 2009-06-09 2012-04-18 Google, Inc. Programming of dimm termination resistance values

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US5835956A (en) * 1899-10-02 1998-11-10 Samsung Electronics Co., Ltd. Synchronous dram having a plurality of latency modes
US6200144B1 (en) * 1997-03-04 2001-03-13 Micron Technology, Inc. Interposer/converter to allow single-sided contact to circuit modules
US6151236A (en) * 2000-02-29 2000-11-21 Enhanced Memory Systems, Inc. Enhanced bus turnaround integrated circuit dynamic random access memory device
US20040004822A1 (en) * 2002-06-28 2004-01-08 Hermann Ruckerbauer Method, adapter card and configuration for an installation of memory modules

Also Published As

Publication number Publication date
AU2005251173A1 (en) 2005-12-15
EP1776641A2 (en) 2007-04-25
WO2005119686A2 (en) 2005-12-15
EP1776641A4 (en) 2007-12-05
EP1776641B1 (en) 2013-05-01
AU2005251173B2 (en) 2009-09-03
US8151030B2 (en) 2012-04-03
TWI380314B (en) 2012-12-21
TW200614256A (en) 2006-05-01
US20050278474A1 (en) 2005-12-15

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