WO2005121969A3 - Distributed virtual multiprocessor - Google Patents

Distributed virtual multiprocessor Download PDF

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Publication number
WO2005121969A3
WO2005121969A3 PCT/US2005/018478 US2005018478W WO2005121969A3 WO 2005121969 A3 WO2005121969 A3 WO 2005121969A3 US 2005018478 W US2005018478 W US 2005018478W WO 2005121969 A3 WO2005121969 A3 WO 2005121969A3
Authority
WO
WIPO (PCT)
Prior art keywords
node
address
copy
page
memory page
Prior art date
Application number
PCT/US2005/018478
Other languages
French (fr)
Other versions
WO2005121969A2 (en
Inventor
Thomas L Lyon
Peter Newman
Joseph R Eykholt
Original Assignee
Netillion Inc
Thomas L Lyon
Peter Newman
Joseph R Eykholt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Netillion Inc, Thomas L Lyon, Peter Newman, Joseph R Eykholt filed Critical Netillion Inc
Publication of WO2005121969A2 publication Critical patent/WO2005121969A2/en
Publication of WO2005121969A3 publication Critical patent/WO2005121969A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45537—Provision of facilities of other operating environments, e.g. WINE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1056—Simplification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/151—Emulated environment, e.g. virtual machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/154—Networked environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/651—Multi-level translation tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/656—Address space sharing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management

Abstract

A distributed virtual multiprocessor (202) having a plurality of nodes coupled to one another by a network (203). A first node (2Oh) page faults in response to an instruction. The first node (2011) indexes a first address translation data structure (2051) maintained therein to obtain an intermediate address that corresponds to a virtual address, then transmits the intermediate address to a second node to request a copy of a memory page that corresponds to the intermediate address (201N). The first node receives a copy of the memory page from the second node, stores the copy of the memory page at a physical address (2091), then loads a second address translation data structure with translation information (2051). Thereafter, the first node resumes execution of the instruction that yielded the page fault.
PCT/US2005/018478 2004-06-02 2005-05-25 Distributed virtual multiprocessor WO2005121969A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US57688504P 2004-06-02 2004-06-02
US57655804P 2004-06-02 2004-06-02
US60/576,558 2004-06-02
US60/576,885 2004-06-02
US10/948,064 2004-09-23
US10/948,064 US20050273571A1 (en) 2004-06-02 2004-09-23 Distributed virtual multiprocessor

Publications (2)

Publication Number Publication Date
WO2005121969A2 WO2005121969A2 (en) 2005-12-22
WO2005121969A3 true WO2005121969A3 (en) 2007-04-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/018478 WO2005121969A2 (en) 2004-06-02 2005-05-25 Distributed virtual multiprocessor

Country Status (2)

Country Link
US (1) US20050273571A1 (en)
WO (1) WO2005121969A2 (en)

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Publication number Publication date
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