WO2006004921A2 - Micro-castellated interposer - Google Patents

Micro-castellated interposer Download PDF

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Publication number
WO2006004921A2
WO2006004921A2 PCT/US2005/023270 US2005023270W WO2006004921A2 WO 2006004921 A2 WO2006004921 A2 WO 2006004921A2 US 2005023270 W US2005023270 W US 2005023270W WO 2006004921 A2 WO2006004921 A2 WO 2006004921A2
Authority
WO
WIPO (PCT)
Prior art keywords
printed wiring
wiring board
castellations
micro
parent
Prior art date
Application number
PCT/US2005/023270
Other languages
French (fr)
Other versions
WO2006004921A3 (en
Inventor
Aaron Levine
Jay D. Stanke
Original Assignee
Honeywell International Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc. filed Critical Honeywell International Inc.
Priority to EP05769151A priority Critical patent/EP1774582A2/en
Priority to JP2007519429A priority patent/JP2008505498A/en
Priority to KR1020077002237A priority patent/KR101318669B1/en
Publication of WO2006004921A2 publication Critical patent/WO2006004921A2/en
Publication of WO2006004921A3 publication Critical patent/WO2006004921A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09181—Notches in edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09645—Patterning on via walls; Plural lands around one hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/225—Correcting or repairing of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers

Definitions

  • the present invention relates to packaging of highly reliable, high ⁇ speed complex electronics, and more particularly to a method and apparatus for reworking circuits using a micro-castellated interconnect board with its related electrical parts and affixing it to the circuitry.
  • An existing prior art device or method uses a custom hybrid part, which internally incorporates the electrical wiring changes with mount die(s) containing the affected parts and provides environmental protection for the electronics.
  • a custom part is very expensive, requires extensive lead- time and is not compliant to the volume allocated to the existing electronics. This method is not adequate for an individual revision as it is cost prohibitive. It can only be utilized for multiple or similar revisions to a large quantity of printed wiring boards (PWB's).
  • Scrapping product and re-layout of circuitry is costly and often causes delays in build schedules. Manual rework is not exact, is prone to human error and adds additional expense due to the use of highly skilled labor. Additionally, some product still gets scrapped due to damage during repair and the rework is not precise and may introduce variability in electrical integrity.
  • a re-layout of the base circuit board can accomplish the same function, that of rewiring, accommodating part changes and providing high reliability, however this approach would be extremely expensive. Additionally, this method may introduce additional errors in re-layout of complex very high-density circuitry by rerouting of critical signals. Other devices, such as individual parts can accomplish one of the desired outcomes but not all three, wiring changes, part changes, and high reliability.
  • US Patent No. 6,377,464 B1 is a device which may have castellations for termination, but does not address durability of the interconnect. In fact, the method described for constellating a part lacks features, which could provide the necessary durability, namely bottom pads.
  • US Patent No. 5,247,423 has 1/2 vias which form periphery castellations allowing leads, wires or solder filled springs, to be attached and provide the interconnect to the parent printed wiring board.
  • the present invention is a durable leadless interconnect.
  • US Patent No. 5,069,626 is a molded plastic device, which is molded to allow plating of castellations, which have additional geometry attachment to the parent printed wiring board. While it mentions that the individual
  • solder joint geometry is critical to sustaining the thermally induced strains to meet the necessary durability.
  • the present invention forms a robust methodology for accommodating part and/or circuitry changes to an existing printed wiring board while allowing for automated assembly. It provides these capabilities without incorporation of additional hardware, namely leads or flexible circuitry. It also allows a method for accommodating parts, materials and geometries that are disparate with the parent's materials and geometries.
  • a primary object of the present invention is to provide a micro castellated interposer, which has the ability to accommodate different wiring paths, part changes and/or new parts and maintain the original high level of reliability of the circuit board assembly.
  • a primary advantage of the present invention is that it provides a means for circuitry and part changes at the lowest cost with the highest reliability without compromising performance.
  • Fig. 1 shows the preferred embodiment of the micro-castellated printed wiring board.
  • Fig. 2 shows the embodiment of Fig. 1 populated with components.
  • Fig. 3 shows the embodiment of Fig. 2 mounted on a parent board.
  • Fig. 4 shows an alternative embodiment of the present invention using partially occluded micro-castellations. DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • the present invention comprises a small but common printed circuit board, which can be manufactured with conventional high precision techniques.
  • the layout of this printed circuit board which can be done in- house to accommodate interface data from the parent circuit card assembly, uses standard trace routing and interconnect (through-holes) found in printed circuit applications. Exact shape, layering and interconnect are determined at the time of laying out the circuitry. Replacement parts and additional parts are incorporated into the circuitry.
  • the micro-castellations which will subsequently interconnect the micro-castellated interconnect board to its parent are placed to optimize circuitry issues while ensuring a robust solder joint which provides the interconnect. Manufacturing methods for the micro-castellated features may vary depending upon the design intent.
  • This design once completed is panelized to provide fabrication efficiency for the circuit board house and enable a multiple up build of micro- castellated circuits on the manufacturing floor.
  • the panelized micro-castellated circuits are built up with parts using standard high precision surface mount assembly methods and machines to form micro-castellated assemblies. These individual assemblies are then separated and are available for stocking or use on the parent assembly.
  • the design of these castellated "leadless" solder joints comprises two distinct stress areas. One area is the pad to pad region commonly called the foot of the solder joint, which is relatively thin and is stressed predominately by sheering forces. The other area known as the toe is the solder that forms a fillet between the castellated solder joint and the remaining pad area.
  • Printed wiring board 101 includes micro- castellated through-hole vias 111 that form the micro-castellated solder joints
  • micro-castellated vias 111 are designed to align with surface features on the parent printed wring board 125 (Fig.3).
  • the micro-castellated printed wiring board 101 is populated with changed circuitry devices, such as a microcircuits 113, resistors 115, and/or capacitors 117. These devices are soldered to the micro-castellated printed wiring board 101 making the micro-castellated circuit card assembly
  • This micro-castellated circuit assembly 119 embodies the replacement circuitry for parent printed wiring board 125.
  • the micro-castellated circuit card assembly 119 is mounted on the parent printed wiring board 125.
  • the micro-castellations 111 are soldered directly to the surface pads 121 forming robust leadless surface mount solder joints 123.
  • the robustness of the solder joints results from choosing the correct material properties for the micro-castellated interposer, designing the castellations/pad geometry in relation to the current parent pad geometry to form adequate solder joints/fillets and designing pad geometry to accommodate part geometries.
  • the materials include the selection of printed wiring board materials whose properties account for a coefficient of expansion differences between the mounted parts and the parent printed wiring board.
  • Solder durability analysis of the geometries and materials is performed in the design stage to ensure that the micro- castellated interposer provides robust solder joints for the parts as well as the interconnect to the parent printed wiring board.
  • These include a pad to castellation geometry ratio, which ensures that the resultant solder geometry is capable of accommodating thermal induced stresses between parts, the micro-castellated printed wiring board and the parent printed wiring board.
  • the manufacturing method includes supplying the correct solder volume to produce the correct geometry solder joint.
  • the parent printed wiring board is made of commercial woven E-glass/epoxy with a coefficient of expansion (CTE) of 15 (parts per million / degree Celsius) and the new parts to be added to the circuitry are ceramic parts with CTE of 7 (ppm/°C), then the Micro-castellated Interposer board would preferably be designed out of woven aramid/multi-functional epoxy with a CTE in between the parts and the parent printed wiring board.
  • CTE coefficient of expansion
  • Optional design and construction methods 127 shown in Fig. 4 allow use of partially occluded micro-castellations 133. This design methodology permits use of additional area for routing circuitry 131 and use of additional devices 129.
  • the partially occluded castellations 133 are soldered to the parent printed wiring board 125 surface pads 121, forming robust leadless surface mount solder joints 123.
  • fully occluded micro-castellations 137 may be utilized as in Fig 5.
  • the fully occluded micro-castellated printed wring board 135 offers maximum board area for a slight reduction in solder joint reliability.
  • micro-castellations are located anywhere on the micro-castellated printed wiring board, including underneath device bodies and permitting their integration into the device land patterns.

Abstract

A miniature PWB (101) with features that incorporate the required circuitry changes and component footprints (105), which has been enhanced with micro-castellations (111) such as those found on ceramic surface mount packages. The miniature PWB (101) is mounted on the circuit board (125) using techniques well known in the art. This combination of technologies provides an adaptable, durable interconnect methodology, which allows for circuit (109) and part changes (113, 115, 117) without changing the layout of the base printed wiring board (125).

Description

MICRO-CASTELLATED INTERPOSER
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based on U.S. Provisional Application Serial No. 60/584025 entitled "Micro Castellated Interposer", filed on June 30, 2004, the teachings of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
Field of the Invention (Technical Field):
The present invention relates to packaging of highly reliable, high¬ speed complex electronics, and more particularly to a method and apparatus for reworking circuits using a micro-castellated interconnect board with its related electrical parts and affixing it to the circuitry.
Background Art:
As electronic devices get smaller and smaller the prior art methods of part substitution and repair of circuitry create errors on existing hardware and become very problematic, if not entirely troublesome. Repair of circuitry and rewiring of devices on high-speed circuitry needs to be manufacturable and to a great extent electrically identical and meet environmental requirements of the product's end use. The present invention addresses a method for incorporating these changes to surface mounted electronics.
An existing prior art device or method uses a custom hybrid part, which internally incorporates the electrical wiring changes with mount die(s) containing the affected parts and provides environmental protection for the electronics. Such a custom part is very expensive, requires extensive lead- time and is not compliant to the volume allocated to the existing electronics. This method is not adequate for an individual revision as it is cost prohibitive. It can only be utilized for multiple or similar revisions to a large quantity of printed wiring boards (PWB's).
Another prior art method is to scrap existing product circuit cards, re- layout the electronics, and procure new printed wiring boards and components. Other methods include reworking the circuit card assembly, usually called "dead bugging" of components and "cut and jumpering" of circuitry relying on highly skilled operators and requiring the visual aid of a microscope to complete. Presently, the accepted practice for military electronics is defined by standards for "cut and jumpering" of traces.
Scrapping product and re-layout of circuitry is costly and often causes delays in build schedules. Manual rework is not exact, is prone to human error and adds additional expense due to the use of highly skilled labor. Additionally, some product still gets scrapped due to damage during repair and the rework is not precise and may introduce variability in electrical integrity.
State of the art approaches have been relatively successful until the current generation of smaller geometry, high-speed electronic parts. Smaller parts require higher skill and use of magnification aids. As parts get smaller, the manual repair and replacement of parts becomes harder and at some point impossible due to human limitations. Higher speeds require more exact electrical wiring lengths and electrical trace separation. Depending upon the extent of the change, current approaches utilize additional adhesive to adhere part and wires to the circuit card assembly.
A re-layout of the base circuit board can accomplish the same function, that of rewiring, accommodating part changes and providing high reliability, however this approach would be extremely expensive. Additionally, this method may introduce additional errors in re-layout of complex very high-density circuitry by rerouting of critical signals. Other devices, such as individual parts can accomplish one of the desired outcomes but not all three, wiring changes, part changes, and high reliability.
There are several prior art documents that disclose castellations and/or outer land grid pads however, they do not address any context of providing a durable interconnect containing the combination of substrate design/materials, pad geometries, and castellation matched to the parent printed wiring board. Additionally, the intent of utilizing existing parent printed wiring board circuitry and providing changed electrical functionality that is both manufacturable and low cost is not addressed in any of the prior art.
These prior art documents include US Patent No. 6,609,915 B2 which discloses a piece that only forms the interconnect between a multichip module and the parent printed wring board. The present invention performs that function as well as providing new circuitry and mounting of parts and addresses the durability of the interconnect.
US Patent No. 6,377,464 B1 is a device which may have castellations for termination, but does not address durability of the interconnect. In fact, the method described for constellating a part lacks features, which could provide the necessary durability, namely bottom pads.
US Patent No. 5,247,423 has 1/2 vias which form periphery castellations allowing leads, wires or solder filled springs, to be attached and provide the interconnect to the parent printed wiring board. The present invention is a durable leadless interconnect.
US Patent No. 5,069,626 is a molded plastic device, which is molded to allow plating of castellations, which have additional geometry attachment to the parent printed wiring board. While it mentions that the individual
"castellations area able to flex (on a microscopic level)" and it allows that the molded material may be matched to the "second component" it does not address how the castellations really flex and if this would be of any benefit to the level of stresses induced due to thermal coefficient of expansion mismatch, not to mention differential heating and cooling. Unless there is major accommodation in the mounting structure, aka flexibility, the solder joint geometry is critical to sustaining the thermally induced strains to meet the necessary durability.
None of the prior art documents teach or disclose the combination of substrate design/materials, pad and castellation geometries, which allow the formation of a robust solder joint. Additionally, the prior art fails to disclose the utilization of existing parent printed wiring board circuitry and providing changed electrical functionality that is both manufacturable and low cost.
SUMMARY OF THE INVENTION (DISCLOSURE OF THE INVENTION)
The present invention forms a robust methodology for accommodating part and/or circuitry changes to an existing printed wiring board while allowing for automated assembly. It provides these capabilities without incorporation of additional hardware, namely leads or flexible circuitry. It also allows a method for accommodating parts, materials and geometries that are disparate with the parent's materials and geometries.
A primary object of the present invention is to provide a micro castellated interposer, which has the ability to accommodate different wiring paths, part changes and/or new parts and maintain the original high level of reliability of the circuit board assembly. A primary advantage of the present invention is that it provides a means for circuitry and part changes at the lowest cost with the highest reliability without compromising performance.
Other objects, advantages and novel features, and further scope of applicability of the present invention will be set forth in part in the detailed description to follow, taken in conjunction with the accompanying drawings, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated into and form a part of the specification, illustrate several embodiments of the present invention and, together with the description, serve to explain the principles of the invention. The drawings are only for the purpose of illustrating a preferred embodiment of the invention and are not to be construed as limiting the invention. In the drawings:
Fig. 1 shows the preferred embodiment of the micro-castellated printed wiring board.
Fig. 2 shows the embodiment of Fig. 1 populated with components. Fig. 3 shows the embodiment of Fig. 2 mounted on a parent board.
Fig. 4 shows an alternative embodiment of the present invention using partially occluded micro-castellations. DESCRIPTION OF THE PREFERRED EMBODIMENTS
(BEST MODES FOR CARRYING OUT THE INVENTION)
The present invention comprises a small but common printed circuit board, which can be manufactured with conventional high precision techniques. The layout of this printed circuit board, which can be done in- house to accommodate interface data from the parent circuit card assembly, uses standard trace routing and interconnect (through-holes) found in printed circuit applications. Exact shape, layering and interconnect are determined at the time of laying out the circuitry. Replacement parts and additional parts are incorporated into the circuitry. The micro-castellations which will subsequently interconnect the micro-castellated interconnect board to its parent are placed to optimize circuitry issues while ensuring a robust solder joint which provides the interconnect. Manufacturing methods for the micro-castellated features may vary depending upon the design intent. This design once completed is panelized to provide fabrication efficiency for the circuit board house and enable a multiple up build of micro- castellated circuits on the manufacturing floor. Once fabricated the panelized micro-castellated circuits are built up with parts using standard high precision surface mount assembly methods and machines to form micro-castellated assemblies. These individual assemblies are then separated and are available for stocking or use on the parent assembly. The design of these castellated "leadless" solder joints comprises two distinct stress areas. One area is the pad to pad region commonly called the foot of the solder joint, which is relatively thin and is stressed predominately by sheering forces. The other area known as the toe is the solder that forms a fillet between the castellated solder joint and the remaining pad area. This region serves as a pseudo column and significantly adds to the life of the solder joint. The second assembly operation with the parent assembly is also an automated process again using standard high precision surface mount assembly methods and machines. The novel micro-castellated printed wiring board is shown in Fig. 1 , where printed wiring board 101 is designed and fabricated by common but high precision printed wiring board tools and methods producing fine features 103. These fine features 103 can include pads for mounting components 105, traces for top and bottom interconnect 109, and through- hole vias 107 for interconnecting layers. Artwork may include intermediate layers for shielding and interconnect depending upon the complexity of the electrical circuitry (not shown). Printed wiring board 101 includes micro- castellated through-hole vias 111 that form the micro-castellated solder joints
123 (Fig. 3) and interconnect to bottom surface pads 121 (Fig. 3). These micro-castellated vias 111 are designed to align with surface features on the parent printed wring board 125 (Fig.3).
In Fig. 2, the micro-castellated printed wiring board 101 is populated with changed circuitry devices, such as a microcircuits 113, resistors 115, and/or capacitors 117. These devices are soldered to the micro-castellated printed wiring board 101 making the micro-castellated circuit card assembly
119. This micro-castellated circuit assembly 119 embodies the replacement circuitry for parent printed wiring board 125.
In Fig. 3 the micro-castellated circuit card assembly 119 is mounted on the parent printed wiring board 125. The micro-castellations 111 are soldered directly to the surface pads 121 forming robust leadless surface mount solder joints 123. The robustness of the solder joints results from choosing the correct material properties for the micro-castellated interposer, designing the castellations/pad geometry in relation to the current parent pad geometry to form adequate solder joints/fillets and designing pad geometry to accommodate part geometries. The materials include the selection of printed wiring board materials whose properties account for a coefficient of expansion differences between the mounted parts and the parent printed wiring board. Solder durability analysis of the geometries and materials is performed in the design stage to ensure that the micro- castellated interposer provides robust solder joints for the parts as well as the interconnect to the parent printed wiring board. These include a pad to castellation geometry ratio, which ensures that the resultant solder geometry is capable of accommodating thermal induced stresses between parts, the micro-castellated printed wiring board and the parent printed wiring board.
In addition, the manufacturing method includes supplying the correct solder volume to produce the correct geometry solder joint.
For example if the parent printed wiring board is made of commercial woven E-glass/epoxy with a coefficient of expansion (CTE) of 15 (parts per million / degree Celsius) and the new parts to be added to the circuitry are ceramic parts with CTE of 7 (ppm/°C), then the Micro-castellated Interposer board would preferably be designed out of woven aramid/multi-functional epoxy with a CTE in between the parts and the parent printed wiring board.
In this way the necessary interconnect strength could be accommodated from the as designed pad/castellation geometry and the resultant solder joint morphology.
Optional design and construction methods 127 shown in Fig. 4 allow use of partially occluded micro-castellations 133. This design methodology permits use of additional area for routing circuitry 131 and use of additional devices 129. The partially occluded castellations 133 are soldered to the parent printed wiring board 125 surface pads 121, forming robust leadless surface mount solder joints 123.
To utilize maximum surface area on the daughter printed wiring board fully occluded micro-castellations 137 may be utilized as in Fig 5. The fully occluded micro-castellated printed wring board 135 offers maximum board area for a slight reduction in solder joint reliability.
Any of these designs and construction methods can be utilized where the micro-castellations are located anywhere on the micro-castellated printed wiring board, including underneath device bodies and permitting their integration into the device land patterns.
Although the invention has been described in detail with particular reference to these preferred embodiments, other embodiments can achieve the same results. Variations and modifications of the present invention will be obvious to those skilled in the art and it is intended to cover in the appended claims all such modifications and equivalents. The entire disclosures of all references, applications, patents, and publications cited above, are hereby incorporated by reference.

Claims

CLAIMSWhat is claimed is:
1. An apparatus for accommodating circuitry device (113, 115, 117) and interconnect changes externally to a parent printed wiring assembly (125), the apparatus comprising: a micro-castellated printed wiring board (101), said micro- castellated printed wiring board (101 ) comprising fine features (103); a first interconnection between said fine features (103) and the changed circuitry devices (113, 115,117), said first interconnect comprising automated assembly and reflow; and a second interconnection between landed castellations (111) of said micro-castellated printed wiring board (101) and the parent printed wiring assembly (125).
2. The apparatus of claim 1 wherein said landed castellations (111) interface directly to parent printed wiring assembly (125).
3. The apparatus of claim 1 wherein said second interconnection comprises a leadless robust solder joint (123).
4. The apparatus of claim 3 wherein said robust leadless solder joint (123) comprises two distinct soldered zones, a first formed between land patterns (121) comprising a thin structure and a second being formed in the landed castellations (111) which functions as a solder column.
5. The apparatus of claim 3 wherein said micro-castellated printing wiring board (101) comprises: a printed wiring board material whose properties account for coefficient of expansion differences between the changed circuitry devices (113, 115, 117) and a parent printed wiring board (125) from the printed wiring assembly (101); and a solder joint (123) with a specific geometry based on a pad to a part lead geometry and thermal induced stresses.
6. The apparatus of claim 1 wherein said first interconnection comprises a robust solder joint.
7. The apparatus of claim 6 wherein said first interconnection comprises: a unique pad geometry (105) for said changed circuitry devices (113, 115, 117) which defines a footprint; a printed wiring board (101) material whose properties account for a coefficient of expansion differences between the changed circuitry devices (113, 115, 117) and a parent printed wiring board (125) from the printed wiring assembly (101); and a solder joint (123) with a specific geometry based on a pad to lead geometry and thermal induced stresses.
8. The apparatus of claim 1 wherein said landed castellations
(111) are formed on an edge of the micro-castellated printed wiring board (101).
9. The apparatus of claim 1 wherein said landed castellations
(111) are formed internal to the micro-castellated printed wiring board (101) comprising partially occluded castellations (133).
10. The apparatus of claim 1 wherein said landed castellations
(111) are formed internal to the micro-castellated printed wiring board (135) comprising fully occluded castellations (137).
11. The apparatus of claim 1 wherein said second interconnection comprises a means for automated assembly and reflow.
12. A method for revising a portion of a parent board (125), the method comprising the steps of: a) removing the portion of the parent board (125) to be replaced;
b) providing a miniature printed wiring board (101 ) comprising micro-castellations (111) for mounting on the parent board (125) wherein said micro-castellations (111) are electrically connected to component mounting pads (105) and which align with surface features (121) on the parent board (125); c) mounting at least one component (113, 115, 117) to the component mounting pads (105); and d) affixing the miniature printed wiring board (101) to the parent board (125).
13. The method of claim 12 further comprising the step of underlaying the miniature printed wiring board (101) comprising providing cutouts in the miniature printed wiring board (101) and placing the at least one component (113, 115, 117) to accommodate the cutouts.
14. The method of claim 12 wherein the step of providing a miniature wiring board (101) comprises interfacing the micro-castellations
(111 ) directly to the surface features (121 ) of the parent printed wiring board (125).
15. The method of claim 12 wherein the step of affixing comprises affixing with a robust leader less solder joint (123).
16. The method of claim 12 wherein the step of providing a miniature printed wiring board (101) comprises: selecting a printed wiring board (101) material whose properties account for coefficient of expansion differences between the at least one component (113, 115, 117) and the parent board (125); and selecting a solder joint (123) with a specific geometry based on a pad (121) to castellation (111) geometry ratio and thermal induced stresses.
17. The method of claim 12 wherein the step of providing a miniature printed wiring board (101) comprises forming the micro castellations (111 ) on an edge of the miniature printed wiring board (101).
18. The method of claim 12 wherein the step of providing a miniature printed wiring board (101) comprises forming the castellations (123) internal to the miniature printed wiring board (101), forming partially occluded castellations (133).
19. The method of claim 12 wherein the step of providing a miniature printed wiring board (101) comprises forming the castellations
(111) internal to the miniature printed wiring board (101), forming fully occluded castellations (137).
20. The method of claim 12 wherein the step of affixing the miniature printed wiring board (101) to the parent board (125) comprises automated assembly and reflow.
PCT/US2005/023270 2004-06-30 2005-06-29 Micro-castellated interposer WO2006004921A2 (en)

Priority Applications (3)

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EP05769151A EP1774582A2 (en) 2004-06-30 2005-06-29 Micro-castellated interposer
JP2007519429A JP2008505498A (en) 2004-06-30 2005-06-29 Interposer with micro-castellation
KR1020077002237A KR101318669B1 (en) 2004-06-30 2005-06-29 Micro-castellated interposer

Applications Claiming Priority (4)

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US58402504P 2004-06-30 2004-06-30
US60/584,025 2004-06-30
US11/136,120 2005-05-24
US11/136,120 US7507914B2 (en) 2004-06-30 2005-05-24 Micro-castellated interposer

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WO2006004921A3 WO2006004921A3 (en) 2006-09-21

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EP1774582A2 (en) 2007-04-18
US7507914B2 (en) 2009-03-24
US20060000638A1 (en) 2006-01-05
WO2006004921A3 (en) 2006-09-21
KR20070039570A (en) 2007-04-12
JP2008505498A (en) 2008-02-21

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