WO2006012127A3 - Microelectronic packages and methods therefor - Google Patents

Microelectronic packages and methods therefor Download PDF

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Publication number
WO2006012127A3
WO2006012127A3 PCT/US2005/021968 US2005021968W WO2006012127A3 WO 2006012127 A3 WO2006012127 A3 WO 2006012127A3 US 2005021968 W US2005021968 W US 2005021968W WO 2006012127 A3 WO2006012127 A3 WO 2006012127A3
Authority
WO
WIPO (PCT)
Prior art keywords
flexible substrate
microelectronic element
microelectronic
outer region
disposed
Prior art date
Application number
PCT/US2005/021968
Other languages
French (fr)
Other versions
WO2006012127A2 (en
Inventor
Belgacem Haba
Masud Beroz
Teck-Gyu Kang
Yoichi Kubota
Sridhar Krishnan
John B Riley Iii
Ilyas Mohammed
Original Assignee
Tessera Inc
Belgacem Haba
Masud Beroz
Teck-Gyu Kang
Yoichi Kubota
Sridhar Krishnan
John B Riley Iii
Ilyas Mohammed
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera Inc, Belgacem Haba, Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John B Riley Iii, Ilyas Mohammed filed Critical Tessera Inc
Priority to CN2005800284765A priority Critical patent/CN101268548B/en
Priority to JP2007518213A priority patent/JP5572288B2/en
Publication of WO2006012127A2 publication Critical patent/WO2006012127A2/en
Publication of WO2006012127A3 publication Critical patent/WO2006012127A3/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
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Abstract

A microelectronic package (90) includes a microelectronic element (62) having faces, contacts and an outer perimeter, and a flexible substrate (42) overlying and spaced from a first face of the Microelectronic element (62), an outer region (86) of the flexible substrate (42) extending beyond the outer perimeter of the Microelectronic element (62). The package (90) includes a plurality of conductive posts (40a-40f) exposed at a surface of the flexible substrate (42) and being electrically interconnected with the microelectronic element (62), whereby at least one of the conductive posts (40a-40f) is disposed in the outer region (86) of the flexible substrate (42), and a compliant layer (74) disposed between the first face of the microelectronic element (62) and the flexible substrate (42), wherein the compliant layer (74) overlies the at least one of the conductive posts that is disposed in the outer region (86) of the flexible substrate (42). The package includes a support element (84) in contact with the microelectronic element (62) and the compliant layer (74), whereby the support element 84 overlies the outer region (86) of the flexible substrate (42).
PCT/US2005/021968 2004-06-25 2005-06-21 Microelectronic packages and methods therefor WO2006012127A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2005800284765A CN101268548B (en) 2004-06-25 2005-06-21 Microelectronic packages and methods therefor
JP2007518213A JP5572288B2 (en) 2004-06-25 2005-06-21 Ultra-small electronic component package and method therefor

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US58306604P 2004-06-25 2004-06-25
US60/583,066 2004-06-25
US62186504P 2004-10-25 2004-10-25
US60/621,865 2004-10-25
US11/140/312 2005-05-27
US11/140,312 US7453157B2 (en) 2004-06-25 2005-05-27 Microelectronic packages and methods therefor

Publications (2)

Publication Number Publication Date
WO2006012127A2 WO2006012127A2 (en) 2006-02-02
WO2006012127A3 true WO2006012127A3 (en) 2007-05-18

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US (4) US7453157B2 (en)
JP (2) JP5572288B2 (en)
CN (1) CN101268548B (en)
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US7745943B2 (en) 2010-06-29
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