WO2006017042A2 - Column amplifier with automatic gain selection for cmos image sensors - Google Patents

Column amplifier with automatic gain selection for cmos image sensors Download PDF

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Publication number
WO2006017042A2
WO2006017042A2 PCT/US2005/023461 US2005023461W WO2006017042A2 WO 2006017042 A2 WO2006017042 A2 WO 2006017042A2 US 2005023461 W US2005023461 W US 2005023461W WO 2006017042 A2 WO2006017042 A2 WO 2006017042A2
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WO
WIPO (PCT)
Prior art keywords
amplifier
gain
output
column
column buffer
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PCT/US2005/023461
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French (fr)
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WO2006017042A3 (en
Inventor
Markus Loose
Original Assignee
Altasens, Inc.
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Publication date
Application filed by Altasens, Inc. filed Critical Altasens, Inc.
Priority to JP2007520395A priority Critical patent/JP5456971B2/en
Priority to EP05768275A priority patent/EP1769534A4/en
Publication of WO2006017042A2 publication Critical patent/WO2006017042A2/en
Publication of WO2006017042A3 publication Critical patent/WO2006017042A3/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70—Circuitry for compensating brightness variation in the scene
    • H04N23/76—Circuitry for compensating brightness variation in the scene by influencing the image signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
    • H04N25/672—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction between adjacent sensors or output registers for reading a single image
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array

Definitions

  • the present invention relates generally to automatic gain selection circuits, and more particularly to a column amplifier having automatic gain selection for CMOS image sensors.
  • a comparator compares the pixel signal directly with a reference signal, in order to determine whether or not to amplify the signal. If the signal is below a certain threshold, the signal is amplified, otherwise it is not.
  • a certain threshold there are many non-uniformities from pixel to pixel in an image sensor, making it difficult to select an appropriate threshold for the amplification decision, or requiring a unique threshold for each pixel.
  • the present invention is a column amplifier architecture having automatic gain selection for CMOS image sensors.
  • a comparator compares an amplified column buffer output signal to a reference voltage. The output of the comparator controls the gain of the amplifier based on the result of the comparison. Initially, a high column buffer gain is selected. For small signals, the output of the column buffer stays below the reference voltage and the output signal stays within the system's dynamic range. For larger signals, the column buffer output will exceed the reference voltage (and also the system's dynamic range) and therefore the comparator output switches states, which selects the low-gain setting.
  • the switching of the comparator output reduces the gain of the column buffer such that the amplified signal returns back to be within the allowed operating range. If desired, the process can be repeated through several gain steps (i.e. high, medium, low). Also, several comparators and reference voltages could be utilized at the same time in order to determine an optimum gain setting. As a result of the architecture of the present invention, the signal will always be amplified with the maximum gain possible, thereby reducing the effect of noise from other system components.
  • the comparator outputs a range output signal, used to identify to downstream processing blocks, which gain setting was used for the corresponding pixel output signal.
  • a digital correction stage attenuate the amplified signals as directed by the range output signal from the comparator.
  • Fig. 1 is a schematic of a prior art circuit
  • Fig. 2 is a graph illustrating the limiting effect of gain on the dynamic range of a system
  • Fig. 3 is a graph illustrating how the present invention can be utilized to digitally attenuate an amplified signal later in processing to overcome to avoid limiting the dynamic range of an image sensor;
  • Fig. 4 is a block diagram of the system architecture of the present invention
  • Fig. 5 is a simplified schematic of an automatic gain selection circuit according to the present invention
  • Fig. 6 is a more detailed schematic of one embodiment of an automatic selection circuit according to the present invention.
  • Fig. 7 is a schematic showing one embodiment of the present invention having a sample-and-hold stage.
  • Fig. 8 is a block diagram of a digital video camera, in which the present invention can advantageously be applied.
  • a CMOS image sensor comprises a plurality of pixels arranged in rows and columns.
  • a sensor may comprise 1920 columns and 1080 rows. Signals from the pixels are typically read-out of the sensor on a column by column basis.
  • Each column may include a column buffer to amplify the small analog signals from each pixel.
  • the present invention provides a multi-gain amplification with automatic gain selection directly in the column buffers. Since the column buffer is the first analog stage after the pixel, the benefit of amplification is maximized. The noise contribution of all the following circuits is thus reduced.
  • the present invention is described herein with respect to reading the pixel signals out on a column basis, the present invention could also be advantageously applied to systems that read out the pixel signals on a row basis, or even systems which multiplex several columns into a single column buffer amplifier circuit.
  • a pixel signal 30 is read-out to a column buffer 32 and amplified by a gain factor "A."
  • a gain factor "A” if the amplified signal is below a certain threshold, then it is passed to a line driver 34. However, if the amplified signal is above a certain threshold, then the unamplified signal is passed to the line driver 34.
  • a lower gain amplification may be applied to the signal, if the high-gain would place the signal above the threshold value.
  • several different gain "levels" could be implemented, each having a different threshold value as desired.
  • a programmable gain amplifier (PGA) 36 further amplifies the signal as determined by the over-all light conditions and system parameters.
  • An analog-to- digital converter (ADC) 38 then converts the analog signal to a digital signal.
  • I/A the noise contributions of the line driver 34, PGA 36, and ADC 38 are reduced by I/A for the signals amplified at the column buffer stage.
  • a digital correction stage 40 reduces the amplified signals by a gain factor of I/A.
  • the present invention effectively reduces the noise contribution of the analog processing blocks for small signals, without adversely affecting the dynamic range of the system.
  • the total noise of the system comprises:
  • V 2 V 2 plxe l + V 2 C 0 IbUf + V 2 LD + V 2 PGA + V 2 A DC + V 2 cross talk (Eqn. 1)
  • v 2 [A 2 * (v 2 p lxe i + V 2 C 0 IbUf) + V 2 LD + v 2 PGA + V 2 ADC + v 2 crO sstaik] / A 2 (Eqn. 2)
  • a high-level schematic of an automatic gain selection circuit 50 utilized in each column buffer is shown Fig. 5.
  • a comparator 54 compares the amplified column buffer 52 output to a reference voltage V rcf .
  • the output of the comparator 54 controls the gain of the amplifier 52 based on the result of the comparison.
  • the basic operation of the circuit 50 is as follows. Initially, a high column buffer gain is selected. For small signals, the output of the column buffer 52 stays below the reference voltage V ref and the output signal stays within the system's dynamic range. For larger signals, the column buffer output will exceed the reference voltage V ref (and also the system's dynamic range) and therefore the comparator 54 output switches states.
  • the amplifier is a dual-gain amplifier. Small signals are amplified with a high-gain, whereas signals above V ref are amplified with a unity or low-gain.
  • the switching of the comparator 54 output reduces the gain of the column buffer 52 such that the amplified signal returns back to be within the allowed operating range. If desired, the process can be repeated through several gain steps (i.e. high, medium, low). Also, several comparators and reference voltages could be utilized at the same time in order to determine an optimum gain setting. As a result of the architecture of the present invention, the signal will always be amplified with the maximum gain possible, thereby reducing the effect of noise from other system components. Note that in contrast to the Kawahito et al. solution discussed above with reference to Fig. 1, the comparator 54 is not comparing the pixel signal V P i xe i directly, but is instead comparing the amplified signal of the column buffer 52 with a reference signal V ref . The present architecture provides two significant advantages over the circuit of Fig. 1
  • the comparator decision is based on the actual integrated signal charge on each pixel, but not on the pixel-to-pixel variations. 2. Since the comparison is performed after a high-gain amplification, the sensitivity versus inaccuracies of the reference voltage or the comparator offsets is greatly reduced. Although the comparator offset is negligible to the first order, a low offset helps to reduce second order effects later in the data reconstruction process, and also avoids column non-uniformities at the transition point from one gain domain to the next.
  • FIG. 6 A more detailed schematic of one possible switched capacitor implementation of the automatic gain selection circuitry is shown in Fig. 6.
  • the preferred component values are shown for a dual-gain circuit 60, having gain settings of 2 and 8.
  • small signals are amplified by a factor of 8
  • larger signals above V re a are amplified by a factor of 2.
  • the high-gain is set by [1 + C3/C4]
  • the low-gain is set by [1 + C1/C2].
  • this circuit performs double sampling on CO (V reSet - V p j xe i).
  • the nominal power supply voltage for this circuit 60 is 3.3 volts.
  • the amplifier 62 and the comparator 64 may be implemented as operational amplifiers, using a folded cascode architecture.
  • a "Range Out” flag is generated by the comparator 64. In a system with only two gain settings, this flag can be a single bit.
  • the digital correction stage 40 checks the Range Out flag to determine with the signal needs to be attenuated or not. For implementations with more than two gain settings, the flag may constitute multiple bits, as appropriate, hi such embodiments, the digital correction stage 40 could perform different levels of signal attenuation, corresponding to the multiple levels of gains.
  • the circuit of Fig. 6, may be further enhanced as shown in Fig. 7.
  • the outputs of the amplifier 62 and the comparator 64 may be stored in a capacitor C stOre and a latch D, respectively. This allows the next pixel signal to be read out, while the current signals are waiting to be transmitted on the respective bus lines 72, 74, via the tri-state buffers 76, 78.
  • Fig. 8 is a high-level block diagram of a type of digital video camera in which the present invention can advantageously be applied. The various blocks are briefly described below:
  • CMOS imaging SoC Functionality Blocks including Imaging Array, CDS AGC A/D, Sensor Drive, Timing Generator, HD Encoder, NTSC Encoder, Video Drive and part of DSP that are often integrated into CMOS imaging System-on-Chip sensors.
  • Imaging Sensor Solid-state cameras use imaging sensors that are fingernail-sized silicon chips containing millions of pixels with photosensitive diodes.
  • CDS AGC A/D Used with analog imaging arrays, such as CCDs and some CMOS sensors, to process the analog video from the imaging sensor to reduce random noise using correlated double sampling (CDS), automatically control gain (AGC) to scale the signal seen by the A/D converter, and finally digitize the analog video (A/D) to produce a digital representation.
  • CDS correlated double sampling
  • AGC automatically control gain
  • DSP/DMP The digital signal processor or digital media processor performs various signal processing functions on the digitized video including color reconstruction, digital compression, noise reduction, etc.
  • Power/Management Provides and manages camera power from line supply or battery.
  • CMOS imaging sensors generally have this block integrated in the sensor including, in some cases, all that is needed to operate the sensor.
  • Timing Generator Provides all the timing and clock signals to operate the various camera blocks.
  • HD Encoder Encodes the video from the DSP to the standard SMPTE format required to display the video on high definition televisions.
  • NTSC Encoder Encodes the video from the DSP to the NTSC format required to display the video on standard televisions.
  • Video Drive Amplifies the video signals to the level needed for television display.
  • DVI Encoder Serializes the video to the standard DVI format used in the latest digital televisions and personal computers.
  • EEPROM Camera memory to non-destructively store camera setup and miscellaneous information.
  • Audio Codec Digitizes, compresses and decompresses various audio signals including raw audio from microphone
  • Audio Amp Amplifies the audio signal to drive speaker.
  • MCU The master control unit controls the camera and lens based on input from the user and scene information. Provides operating status to LCD monitor.
  • Zoom Lens Control Controls zoom ratio of lens based on user input.
  • Buttons Controls camera setup based on user input.
  • IR Remote IR receiver provides user setup information to MCU to appropriately adjust camera operation from remote control unit.

Abstract

A column amplifier architecture having automatic gain selection (50) for CMOS image sensors, which reduces the effect of analog noise, while maintaining a system's dynamic range. A comparator (54) compares an amplified column buffer output signal to a reference voltage (Vref). The output of the comparator (54) controls the gain of the amplifier (52) based on the result the comparison. Initially, a high column buffer gain is selected. For small signals, the output of the column buffer stays below the reference voltage and the output signal stays within the system's dynamic range. For larger signals, the column buffer output will exceed the reference voltage and also the system's dynamic range and therefore the comparator output switches states, which selects the low-gain setting. Multiple gain levels may be implemented, if desired.

Description

COLUMN AMPLIFIER WITH AUTOMATIC GAIN SELECTION FOR
CMOS IMAGE SENSORS
BACKGROUND OF THE INVENTION 1. Technical Field
The present invention relates generally to automatic gain selection circuits, and more particularly to a column amplifier having automatic gain selection for CMOS image sensors.
2. Description of the Related Art In order to design improved CMOS image sensors for low light sensitivity, excellent low noise performance is desired. Besides the noise generated directly in each pixel, the noise contribution of all subsequent analog processing stages must be considered as well. To minimize the impact of these system noise sources, it is beneficial to amplify each pixel sensor signal as early as possible in the image sensor. Early amplification leads to an improved signal-to-noise ratio, since the signal is amplified, but the noise of the system components after the amplification stage is not. The problem with signal amplification, however, is that large signals, when amplified, can end up being outside of the dynamic range of the sensor In other words, signal amplification reduces the over-all dynamic range of the system. One prior attempt to solve this problem is disclosed by S. Kawahito et al., A
Column-Based Pixel-Gain-Adaptive CMOS Image Sensor for Low-Light Level Imaging, Proc. of IEEE International Solid-State Circuits Conference (ISSCC), 2003, San Francisco, Volume 46, Page 224. As shown in Fig. 1 , a comparator compares the pixel signal directly with a reference signal, in order to determine whether or not to amplify the signal. If the signal is below a certain threshold, the signal is amplified, otherwise it is not. However, there are many non-uniformities from pixel to pixel in an image sensor, making it difficult to select an appropriate threshold for the amplification decision, or requiring a unique threshold for each pixel.
Therefore, it would be desirable if a selective amplification could be applied to the pixel signals in an image sensor, wherein the amplification decision is less dependent on the non-uniformities of the pixels.
SUMMARY OF THE INVENTION
In general, the present invention is a column amplifier architecture having automatic gain selection for CMOS image sensors. In one embodiment, a comparator compares an amplified column buffer output signal to a reference voltage. The output of the comparator controls the gain of the amplifier based on the result of the comparison. Initially, a high column buffer gain is selected. For small signals, the output of the column buffer stays below the reference voltage and the output signal stays within the system's dynamic range. For larger signals, the column buffer output will exceed the reference voltage (and also the system's dynamic range) and therefore the comparator output switches states, which selects the low-gain setting.
The switching of the comparator output reduces the gain of the column buffer such that the amplified signal returns back to be within the allowed operating range. If desired, the process can be repeated through several gain steps (i.e. high, medium, low). Also, several comparators and reference voltages could be utilized at the same time in order to determine an optimum gain setting. As a result of the architecture of the present invention, the signal will always be amplified with the maximum gain possible, thereby reducing the effect of noise from other system components.
Additionally, the comparator outputs a range output signal, used to identify to downstream processing blocks, which gain setting was used for the corresponding pixel output signal. After additional processing by other analog stages, such as a line driver, a programmable gain amplifier and an analog-to-digital converter, a digital correction stage attenuate the amplified signals as directed by the range output signal from the comparator.
BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which: Fig. 1 is a schematic of a prior art circuit;
Fig. 2 is a graph illustrating the limiting effect of gain on the dynamic range of a system;
Fig. 3 is a graph illustrating how the present invention can be utilized to digitally attenuate an amplified signal later in processing to overcome to avoid limiting the dynamic range of an image sensor;
Fig. 4 is a block diagram of the system architecture of the present invention; Fig. 5 is a simplified schematic of an automatic gain selection circuit according to the present invention;
Fig. 6 is a more detailed schematic of one embodiment of an automatic selection circuit according to the present invention;
Fig. 7 is a schematic showing one embodiment of the present invention having a sample-and-hold stage; and
Fig. 8 is a block diagram of a digital video camera, in which the present invention can advantageously be applied. DETAILED DESCRIPTION OF THE INVENTION
The following description is provided to enable any person skilled in the art to make and use the invention and sets forth the best modes contemplated by the inventor for carrying out the invention. Various modifications, however, will remain readily apparent to those skilled in the art. Any and all such modifications, equivalents and alternatives are intended to fall within the spirit and scope of the present invention.
In general, a CMOS image sensor comprises a plurality of pixels arranged in rows and columns. For example, in a typical HDTV video application, a sensor may comprise 1920 columns and 1080 rows. Signals from the pixels are typically read-out of the sensor on a column by column basis. Each column may include a column buffer to amplify the small analog signals from each pixel. The present invention provides a multi-gain amplification with automatic gain selection directly in the column buffers. Since the column buffer is the first analog stage after the pixel, the benefit of amplification is maximized. The noise contribution of all the following circuits is thus reduced. While the present invention is described herein with respect to reading the pixel signals out on a column basis, the present invention could also be advantageously applied to systems that read out the pixel signals on a row basis, or even systems which multiplex several columns into a single column buffer amplifier circuit.
As illustrated in Fig. 2, if a single high-gain amplifier were used to amplify each signal from the pixels, the dynamic range of the system would be greatly reduced, since the output signals would quickly reach the saturation limit of the system. Therefore, it would be desirable to amplify the small signals below point S on the graph with a high-gain, but only amplify the signals above point S with a low or no-gain amplifier. After the signals are processed by the other analog system components, the analog signal may be digitized and a digital attenuation stage can "map" the amplified small signals back into the original domain, as shown in the graph of Fig. 3. Fig. 4 illustrates the signal processing blocks according to one embodiment of the present invention, which may be used in a digital video application, such as for an HDTV video camera. A pixel signal 30 is read-out to a column buffer 32 and amplified by a gain factor "A." According to the present invention, if the amplified signal is below a certain threshold, then it is passed to a line driver 34. However, if the amplified signal is above a certain threshold, then the unamplified signal is passed to the line driver 34. Alternatively, a lower gain amplification may be applied to the signal, if the high-gain would place the signal above the threshold value. In fact, several different gain "levels" could be implemented, each having a different threshold value as desired. Next a programmable gain amplifier (PGA) 36 further amplifies the signal as determined by the over-all light conditions and system parameters. An analog-to- digital converter (ADC) 38 then converts the analog signal to a digital signal. Note that the noise contributions of the line driver 34, PGA 36, and ADC 38 are reduced by I/A for the signals amplified at the column buffer stage. Finally, a digital correction stage 40 reduces the amplified signals by a gain factor of I/A. Thus, the present invention effectively reduces the noise contribution of the analog processing blocks for small signals, without adversely affecting the dynamic range of the system. In this example, the total noise of the system comprises:
V2 = V2 plxel + V2C0IbUf + V2LD + V2PGA+ V2 ADC + V2 crosstalk (Eqn. 1) Applying a gain factor of A in the column buffer, lead to: v2 = [A2 * (v2plxei + V2C0IbUf) + V2LD + v2 PGA+ V2ADC + v2 crOsstaik] / A2 (Eqn. 2)
= v2 pixei + v2 coibuf + (V2LD + V2PGA+ v2 ADc + v2 CTosstaik) / A2 (Eqn. 3)
V0Ut = (Vp1Xd * A) / A = Vplxei (Eqn. 4)
Thus, the noise contributions of the line driver, PGA, ADC and crosstalk are reduced by I/A, and the SNR (V011, / Vv2) is improved.
A high-level schematic of an automatic gain selection circuit 50 utilized in each column buffer is shown Fig. 5. A comparator 54 compares the amplified column buffer 52 output to a reference voltage Vrcf. The output of the comparator 54 controls the gain of the amplifier 52 based on the result of the comparison. The basic operation of the circuit 50 is as follows. Initially, a high column buffer gain is selected. For small signals, the output of the column buffer 52 stays below the reference voltage Vref and the output signal stays within the system's dynamic range. For larger signals, the column buffer output will exceed the reference voltage Vref (and also the system's dynamic range) and therefore the comparator 54 output switches states. In this embodiment, the amplifier is a dual-gain amplifier. Small signals are amplified with a high-gain, whereas signals above Vref are amplified with a unity or low-gain.
The switching of the comparator 54 output reduces the gain of the column buffer 52 such that the amplified signal returns back to be within the allowed operating range. If desired, the process can be repeated through several gain steps (i.e. high, medium, low). Also, several comparators and reference voltages could be utilized at the same time in order to determine an optimum gain setting. As a result of the architecture of the present invention, the signal will always be amplified with the maximum gain possible, thereby reducing the effect of noise from other system components. Note that in contrast to the Kawahito et al. solution discussed above with reference to Fig. 1, the comparator 54 is not comparing the pixel signal VPixei directly, but is instead comparing the amplified signal of the column buffer 52 with a reference signal Vref. The present architecture provides two significant advantages over the circuit of Fig. 1
1. Since the signal has already been "double-sampled" the non-uniformities of the pixels have been virtually eliminated. Therefore, the comparator decision is based on the actual integrated signal charge on each pixel, but not on the pixel-to-pixel variations. 2. Since the comparison is performed after a high-gain amplification, the sensitivity versus inaccuracies of the reference voltage or the comparator offsets is greatly reduced. Although the comparator offset is negligible to the first order, a low offset helps to reduce second order effects later in the data reconstruction process, and also avoids column non-uniformities at the transition point from one gain domain to the next.
A more detailed schematic of one possible switched capacitor implementation of the automatic gain selection circuitry is shown in Fig. 6. The preferred component values are shown for a dual-gain circuit 60, having gain settings of 2 and 8. In other words, small signals are amplified by a factor of 8, whereas larger signals above Vrea are amplified by a factor of 2. The high-gain is set by [1 + C3/C4] and the low-gain is set by [1 + C1/C2]. Also, this circuit performs double sampling on CO (VreSet - Vpjxei). The nominal power supply voltage for this circuit 60 is 3.3 volts.
The amplifier 62 and the comparator 64 may be implemented as operational amplifiers, using a folded cascode architecture. In order for the digital correction stage 40 (Fig. 4) to know which signals need to be attenuated, a "Range Out" flag is generated by the comparator 64. In a system with only two gain settings, this flag can be a single bit. For each pixel signal processed, the digital correction stage 40 checks the Range Out flag to determine with the signal needs to be attenuated or not. For implementations with more than two gain settings, the flag may constitute multiple bits, as appropriate, hi such embodiments, the digital correction stage 40 could perform different levels of signal attenuation, corresponding to the multiple levels of gains.
The circuit of Fig. 6, may be further enhanced as shown in Fig. 7. The outputs of the amplifier 62 and the comparator 64 may be stored in a capacitor CstOre and a latch D, respectively. This allows the next pixel signal to be read out, while the current signals are waiting to be transmitted on the respective bus lines 72, 74, via the tri-state buffers 76, 78.
Fig. 8 is a high-level block diagram of a type of digital video camera in which the present invention can advantageously be applied. The various blocks are briefly described below:
CMOS imaging SoC Functionality: Blocks including Imaging Array, CDS AGC A/D, Sensor Drive, Timing Generator, HD Encoder, NTSC Encoder, Video Drive and part of DSP that are often integrated into CMOS imaging System-on-Chip sensors. Imaging Sensor: Solid-state cameras use imaging sensors that are fingernail-sized silicon chips containing millions of pixels with photosensitive diodes.
CDS AGC A/D: Used with analog imaging arrays, such as CCDs and some CMOS sensors, to process the analog video from the imaging sensor to reduce random noise using correlated double sampling (CDS), automatically control gain (AGC) to scale the signal seen by the A/D converter, and finally digitize the analog video (A/D) to produce a digital representation. DSP/DMP: The digital signal processor or digital media processor performs various signal processing functions on the digitized video including color reconstruction, digital compression, noise reduction, etc.
Power/Management: Provides and manages camera power from line supply or battery.
Sensor Drive: This block provides all the voltages and clock waveforms needed to operate CCD-based imaging sensors. CMOS imaging sensors generally have this block integrated in the sensor including, in some cases, all that is needed to operate the sensor. Timing Generator: Provides all the timing and clock signals to operate the various camera blocks.
HD Encoder: Encodes the video from the DSP to the standard SMPTE format required to display the video on high definition televisions.
NTSC Encoder: Encodes the video from the DSP to the NTSC format required to display the video on standard televisions.
Video Drive: Amplifies the video signals to the level needed for television display.
DVI Encoder: Serializes the video to the standard DVI format used in the latest digital televisions and personal computers.
EEPROM: Camera memory to non-destructively store camera setup and miscellaneous information.
Audio Codec: Digitizes, compresses and decompresses various audio signals including raw audio from microphone
Audio Amp: Amplifies the audio signal to drive speaker.
MCU: The master control unit controls the camera and lens based on input from the user and scene information. Provides operating status to LCD monitor. Zoom Lens Control: Controls zoom ratio of lens based on user input.
Buttons: Controls camera setup based on user input.
Motor Drivers: Control focus and zoom based on information provided by MCU
Motors: Lens motors appropriately adjust lens focus and zoom ratio. Rx IR Remote: IR receiver provides user setup information to MCU to appropriately adjust camera operation from remote control unit.
Those skilled in the art will appreciate that various adaptations and modifications of the just-described preferred embodiments can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.

Claims

What is claimed is: 1. In a CMOS image sensor having a plurality of pixels, a column buffer having automatic gain control, the column buffer comprising: an amplifier connected to at least one pixel; a reference voltage; and a comparator connected to the reference voltage and an output of the amplifier; wherein the amplifier is first set to a first gain level, and if the output of the amplifier is below the reference voltage then a signal is output at the first gain level, otherwise if the output of the amplifier is above the reference voltage, then the amplifier gain is reset to a second level and the amplifier outputs a signal at the second gain level. 2. The column buffer of Claim 1 , wherein the first gain level is a high-gain level, and the second gain level is a low-gain level. 3. The column buffer of Claim 2, wherein the low-gain level is a unity gain level. 4. The column buffer of Claim 2, wherein the amplifier is an operational amplifier having a folded cascode architecture. 5. The column buffer of Claim 4, wherein the comparator is an operational amplifier having a folded cascode architecture. 6. The column buffer of Claim 2, further comprising a pixel charge storage capacitor connected to an input of the amplifier. 7. The column buffer of Claim 6, further comprising a switched capacitor network connected to an input of the amplifier to set the gain level of the amplifier. 8. The column buffer of Claim 7, wherein the comparator outputs a gain range output signal corresponding to the gain level set by the comparator. 9. The column buffer of Claim 8, further comprising an output storage capacitor for storing an output of the amplifier. 10. The column buffer of Claim 9, further comprising a latch to store the gain range output signal. 11. The column buffer of Claim 1 , wherein the amplifier has a plurality of gain levels that are set according to a comparison of an output signal with multiple reference voltages. 12. A CMOS image sensor having a plurality of pixels arranged in rows and columns, the image sensor comprising: a column buffer associated with each column of pixels and connected to the pixels via a column bus, the column buffer comprising: an amplifier connected to the column bus; a reference voltage; and a comparator connected to the reference voltage and an output of the amplifier, the comparator outputting a gain range output signal; wherein the amplifier is first set to a first gain level, and if the output of the amplifier is below the reference voltage then a signal is output at the first gain level, otherwise if the output of the amplifier is above the reference voltage, then the amplifier gain is reset to a second level and the amplifier outputs a signal at the second gain level. 13. The CMOS image sensor of Claim 12, wherein the amplifier has a plurality of gain levels that are set based on a comparison of an amplified output signal with a plurality of reference voltages. 14. The CMOS image sensor of Claim 12, further comprising a line driver, a programmable gain amplifier and an analog-to-digital converter connected to the column buffer output. 15. The CMOS image sensor of Claim 14, further comprising a digital correction stage connected to the analog-to-digital converter to attenuate the amplified signal. 16. A digital video camera comprising: a CMOS image sensor having a plurality of pixel sensors arranged in rows and columns, the CMOS image sensor comprising: a column buffer associated with each column of pixels and connected to the pixels via a column bus, the column buffer comprising: an amplifier connected to the column bus; a reference voltage; and a comparator connected to the reference voltage and an output of the amplifier, the comparator outputting a gain range output signal; wherein the amplifier is first set to a first gain level, and if the output of the amplifier is below the reference voltage then a signal is output at the first gain level, otherwise if the output of the amplifier is above the reference voltage, then the amplifier gain is reset to a second level and the amplifier outputs a signal at the second gain level; an analog- to-digital converter connected to an output of the amplifier; and a digital correction stage connected to an output of the analog-to-digital converter to attenuate the amplified signal. 17. The digital video camera of Claim 16, further comprising a line driver connected between the column buffer and the analog-to-digital converter. 18. The digital video camera of Claim 17, further comprising a programmable gain amplifier connected between the line driver and the analog-to-digital converter. 19. The digital video camera of Claim 18, wherein the amplifier connected to the column bus has a plurality of gain levels. 20. The digital video camera of Claim 19, wherein the column buffer is connected to a plurality of columns, such that an output from each column is multiplexed onto the column the buffer.
PCT/US2005/023461 2004-07-07 2005-07-01 Column amplifier with automatic gain selection for cmos image sensors WO2006017042A2 (en)

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US20080136952A1 (en) 2008-06-12
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TWI372515B (en) 2012-09-11
US7443435B2 (en) 2008-10-28
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WO2006017042A3 (en) 2007-02-22

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