WO2006017376A2 - Semiconductor power device having a top-side drain using a sinker trench - Google Patents

Semiconductor power device having a top-side drain using a sinker trench Download PDF

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Publication number
WO2006017376A2
WO2006017376A2 PCT/US2005/026928 US2005026928W WO2006017376A2 WO 2006017376 A2 WO2006017376 A2 WO 2006017376A2 US 2005026928 W US2005026928 W US 2005026928W WO 2006017376 A2 WO2006017376 A2 WO 2006017376A2
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WIPO (PCT)
Prior art keywords
trench
sinker
gate
substrate
sinker trench
Prior art date
Application number
PCT/US2005/026928
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French (fr)
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WO2006017376A3 (en
Inventor
Thomas E. Grebs
Gary M. Dolny
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Fairchild Semiconductor Corporation
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Publication date
Application filed by Fairchild Semiconductor Corporation filed Critical Fairchild Semiconductor Corporation
Priority to JP2007524859A priority Critical patent/JP2008509557A/en
Priority to AT0930405A priority patent/AT502860A2/en
Priority to DE112005001675.7T priority patent/DE112005001675B4/en
Publication of WO2006017376A2 publication Critical patent/WO2006017376A2/en
Publication of WO2006017376A3 publication Critical patent/WO2006017376A3/en
Priority to HK08106846.5A priority patent/HK1112112A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates in general to semiconductor power devices and more particularly to power devices with top-side drain contact using a sinker trench.
  • ICs integrated circuits
  • many power semiconductor devices have a vertical structure with the back of the die being an active electrical connection.
  • the source and gate connections are at the top surface of the die and the drain connection is on the back side of the die.
  • sinker trench structures are used for this purpose.
  • diffusion sinkers extending from the top-side of the die down to the substrate (which forms the drain contact region of the device) are used to make the drain contact available at the top surface of the die.
  • a drawback of this technique is that the lateral diffusion during the formation of the diffusion sinkers results in consumption of a significant amount of the silicon area.
  • a semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate.
  • a first trench extends into and terminates within the epitaxial layer.
  • a sinker trench extends from the top surface of the epitaxial layer through the epitaxial layer and terminates within the substrate.
  • the sinker trench is laterally spaced from the first trench, and is wider and extends deeper than the first trench.
  • the sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.
  • a semiconductor power device is formed as follows.
  • An epitaxial layer is formed over and in contact with a substrate.
  • the epitaxial layer and the substrate are of a first conductivity type.
  • a first opening for forming a first trench and a second opening for forming a sinker trench are defined such that the second opening is wider than the first opening.
  • a silicon etch is performed to simultaneously etch through the first and second openings to form the first trench and the sinker trench such that the first trench terminates within the epitaxial layer and the sinker trench terminates within the substrate.
  • the sinker trench sidewalls and bottom are lined with an insulator.
  • the sinker trench is filled with a conductive material such that the conductive material makes electrical contact with the substrate along the bottom of the sinker trench.
  • An interconnect layer is formed over the epitaxial layer such that the interconnect layer makes electrical contact with the conductive material along the top surface of the sinker trench.
  • a semiconductor power device includes a plurality of groups of stripe-shaped trenches extending in a silicon region over a substrate.
  • a contiguous sinker trench completely surrounds each group of the plurality of stripe-shaped trenches so as to isolate the plurality of groups of stripe-shaped trenches from one another.
  • the contiguous sinker trench extends from a top surface of the silicon region through the silicon region and terminates within the substrate.
  • the contiguous sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench.
  • a semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate.
  • Each of a plurality of stripe-shaped sinker trenches extends between two adjacent groups of the plurality of groups of stripe-shaped gate trenches.
  • the plurality of stripe-shaped sinker trenches extend from a top surface of the silicon region through the silicon region and terminate within the substrate.
  • the plurality of stripe-shaped sinker trenches are lined with an insulator only along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.
  • a semiconductor package device houses a die which includes a power device.
  • the die includes a silicon region over a substrate.
  • Each of a first plurality of trenches extends in the silicon region.
  • a contiguous sinker trench extends along the perimeter of the die so as to completely surround the first plurality of trenches.
  • the contiguous sinker trench extends from a top surface of the die through the silicon region and terminates within the substrate.
  • the contiguous sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench.
  • a plurality of interconnect balls arranged in a grid array includes an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the contiguous sinker trench.
  • FIG. 1 shows a simplified cross sectional view of an exemplary vertical power device in accordance with an embodiment of the invention
  • Figs. 2-4 show various top layout views of a vertical power device with one or more sinker trenches in accordance with exemplary embodiments of the invention
  • Fig. 5 is a top view illustrating the locations of interconnect balls in a ball-grid array package relative to a sinker trench extending along the perimeter of a die housed in the ball- grid array package, in accordance with an exemplary embodiment of the invention.
  • a sinker trench terminating within the silicon substrate is filled with a highly conductive material such as doped polysilicon or metallic material.
  • the sinker trench is laterally spaced a predetermined distance from the active region wherein gate trenches are formed.
  • the sinker trench is wider and extends deeper than the gate trenches, and is lined with an insulator only along its sidewalls.
  • Fig. 1 shows a simplified cross sectional view of a vertical trenched-gate power MOSFET structure 100 in accordance with an exemplary embodiment of the invention.
  • An n-type epitaxial layer 104 extends over an n-type substrate 102 which forms the back side drain.
  • a sinker trench 106 extends from the top surface of epitaxial layer 104 through epitaxial layer 104 terminating within substrate 102.
  • a dielectric layer 110 lines the sinker trench sidewalls.
  • Dielectric layer 110 may be from any one of oxide, silicon nitride, silicon oxynitride, multilayer of oxide and nitride, any known low k insulating material, and any known high k insulating material.
  • Oxide as used in this disclosure means a chemical vapor deposited oxide (Si x Oy) or a thermally grown silicon dioxide (SiO 2 ).
  • Sinker trench 106 is filled with a conductive material 108 such as doped polysilicon, selective epitaxial silicon (SEG), metal, or metallic compounds.
  • Conductive material 108 is in electrical contact with substrate 102 along the bottom of sinker trench 106.
  • Conductive material 108 thus makes the back-side drain available along the top side for interconnection. With the drain contact moved to the top surface, a back-side metal for contacting substrate 102 is no longer needed, but could be used in conjunction with the top side contact.
  • the back side metal layer may be included for other purposes such as preventing the die from cracking and improving the heat transfer properties of the device.
  • Well regions 114 of p-type conductivity extend along an upper portion of epitaxial layer 104.
  • Gate trenches 112 are laterally spaced from sinker trench 106 by a predetermined distance Sl, and vertically extend from the top surface through p-type well regions 114 terminating at a predetermined depth within epitaxial layer 104.
  • Sinker trench 106 is wider and deeper than gate trenches 112.
  • Gate trenches 112 are lined with a dielectric layer 116. The dielectric along the bottom of gate trenches 112 may optionally be made thicker than the dielectric along the gate trench sidewalls.
  • Each gate trench 112 includes a gate electrode 118 and a dielectric layer 120 atop gate electrode 118 to reduce the gate to drain capacitance.
  • Source regions 122 of n-type conductivity extend along an upper portion of well regions 114. Source regions 122 overlap gate electrodes 118 along the vertical dimension.
  • well region 114 terminates a distance away from sinker trench 106. In one embodiment, this distance is dictated by the device blocking voltage rating. In another embodiment, well region 114 terminates at and thus abuts sinker trench 106. In this embodiment, for higher blocking voltage ratings, the thickness of the dielectric layer along sinker trench sidewalls needs to be made larger since the sinker dielectric is required to withstand a higher voltage. This may require a wider sinker trench if the conductive material 108 is required to have a minimum width for current handling purposes.
  • a conduction channel from source regions 122 to epitaxial layer 104 is formed in well regions 114 along gate trench sidewalls.
  • a current thus flows from drain terminal 124 vertically through conductive material 108 of sinker trench 106, then laterally through substrate 102, and finally vertically through epitaxial layer 104, the conduction channel in well regions 114, and source regions 122, to source terminal 126.
  • the width of the gate trenches is generally kept as small as the manufacturing technology allows to maximize the packing density, a wider sinker trench is generally more desirable.
  • a wider sinker trench is easier to fill, has lower resistance, and can more easily be extended deeper if needed.
  • sinker trench 106 and gate trenches 114 are formed at the same time. This is advantageous in that the sinker trench is self-aligned to the active region.
  • the widths of the sinker trench and the gate trenches and spacing Sl between sinker trench 106 and the active region need to be carefully selected taking into account a number of factors.
  • a ratio of width Ws of sinker trench 106 to width Wg of gate trenches 112 needs to be selected so that upon completion of the trench etch step sinker trench 106 and gate trenches 112 terminate at tiie desired depths.
  • the width ratio as well as spacing Sl needs to be carefully selected to minimize micro-loading effect which occurs when trenches with different features are simultaneously etched. Micro- loading effect, if not addressed properly, may cause trenches with a wide opening have a wider bottom than top. This can lead to such problems as formation of pin-holes in the conductive material in the sinker trench. The micro-loading effect can also be minimized by selecting proper etch material.
  • the ratio of the width of the sinker trench to that of the gate trenches is also dependent on the type of conductive material used in the sinker trench. In general, a ratio of the sinker trench width to the gate trench width of less than 10: 1 is desirable. In one embodiment wherein doped polysilicon is used as the conductive material, a ratio of sinker trench width to gate trench width of less than 5:1 is desirable. For example, for a gate trench width of 0.5 ⁇ m, a sinker trench width in the range of about 0.7 ⁇ m to 2.5 ⁇ m would be selected. If a metal or other highly conductive material is used in the sinker trench, a higher ratio (e.g., 3 : 1) is more desirable. Other than the relative width of the trenches, spacing S 1 between the sinker trench and the active region also impacts the micro-loading effect. A smaller spacing generally results in reduced micro-loading effect.
  • the depth of the gate trenches in the epitaxial layer is selected to be close to the interface between substrate 102 and epitaxial layer 104 so that a slightly wider sinker trench would reach through to contact substrate 102.
  • both the gate trenches and the sinker trench terminate within substrate 102.
  • the sinker trench and the gate trenches are formed at different times. Thought the sinker trench would not be self-aligned to the active region, spacing Sl is not a critical dimension. Advantages of forming the two trenches at different times include elimination of the micro-loading effect, and the ability to optimize each trench separately.
  • a method of forming the power transistor shown in Fig. 1 wherein the sinker trench and gate trenches are formed simultaneously is as follows. Epitaxial layer 104 is formed over substrate 102. Next, a masking layer is used to pattern the gate trench and sinker trench openings.
  • a nitride layer is formed over the oxide layer in all trenches.
  • the oxide and nitride layers are then removed from the bottom of the sinker trench using conventional photolithography and anisotropic etch techniques thus leaving an oxide-nitride bi-layer along the sinker trench sidewalls.
  • anisotropic and isotropic etching or isotropic etching alone can be used.
  • the combination of anisotropic and isotropic etching can advantageously be used to respectively remove the nitride and oxide layers from lower sidewall portions of the trench sinker (e.g., those lower sidewall portions extending in the substrate or even in the epitaxial layer - this would advantageously reduce the on-resistance).
  • the resulting thicker bi-layer of dielectric along sinker trench sidewalls is advantageously capable of withstanding higher drain voltages.
  • the sinker trench and gate trenches are then filled with in-situ doped polysilicon.
  • the doped polysilicon is then etched back to planarize the top of the polysilicon in the trenches with the top surface of epitaxial layer 104.
  • the polysilicon and oxide-nitride bi-layer are removed from the gate trenches.
  • the gate trenches are then lined with a gate oxide layer and filled with gate polysilicon material.
  • the excess gate polysilicon over the sinker trench is removed using a conventional photolithography and etch process to pattern the gate electrode.
  • the remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods.
  • a thick oxide layer (as mentioned above, to reduce the spacing of the sinker trench to the well region) is formed along the sidewalls and bottom of the gate and sinker trenches.
  • the thick oxide layer is then removed from the bottom of the sinker trenches using conventional photolithography and anisotropic etch techniques thus leaving the sidewalls of the sinker trench lined with the thick oxide while the gate trenches are protected.
  • anisotropic and isotropic etching can be used to also remove the thick oxide from lower portions of the trench sinker sidewalls.
  • the oxide layer may act as a sacrificial insulating layer for the gate trenches to improve the gate oxide integrity.
  • the sinker trench and gate trenches are then filled with in-situ doped polysilicon.
  • the doped polysilicon is then etched back to planarize the top of the polysilicon in the trenches with the top surface of epitaxial layer 104.
  • the polysilicon and insulating layer are removed from the gate trenches.
  • the gate trenches are then lined with a gate insulating layer and filled with gate polysilicon material.
  • the excess gate polysilicon over the sinker trenches is removed using a conventional photolithography and etch process to pattern the gate electrode.
  • the remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods.
  • an insulating layer e.g., gate oxide
  • the gate oxide layer is then removed from the bottom of the sinker trenches using conventional photolithography and anisotropic etch techniques thus leaving an oxide layer lining the sidewalls of the sinker trench while the gate trenches are protected.
  • anisotropic and isotropic etching or isotropic etching alone can be used.
  • the combination of anisotropic and isotropic etching can advantageously be used to remove the gate oxide layer from lower sidewall portions of the trench sinker (e.g., those lower sidewall portions extending in the substrate or even in the epitaxial layer - this would advantageously reduce the on-resistance).
  • the sinker trench and gate trenches are then filled with in-situ doped polysilicon.
  • the doped polysilicon is then patterned using conventional photolithography techniques and etched to form both the sinker (drain) and gate electrodes.
  • the remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods.
  • the sinker trench and gate trenches are formed independently by using separate masking steps. For example, using a first set of masks and processing steps the gate trenches are defined and etched, lined with gate oxide, and filled with polysilicon. Using a second set of masks and processing steps the sinker trench is defined and etched, lined with dielectric layer along its sidewalls, and filled with a conductive material. The order in which the sinker trench and gate trenches are formed may be reversed.
  • Fig. 2 shows a simplified top layout view of the power device with sinker trench in accordance with an exemplary embodiment of the invention.
  • the Fig. 2 layout view depicts a stripe-shaped cell configuration.
  • Stripe-shaped gate trenches 212a extend vertically and terminate in horizontally-extending gate trenches 212b.
  • the three groups of striped gate trenches are surrounded by a contiguous sinker trench 206.
  • sinker trenches 306 are disposed between groups of gate trenches (only two of which are shown) and are repeated at such frequency and spacing as dictated by the desired Ron.
  • the spacing between adjacent sinker trenches needs to be two times the thickness of the wafer. For example, for a 4 mils thick wafer, the sinker trenches may be spaced from one another by approximately 8 mils. For even a lower Ron, the sinker trenches may be placed closer together.
  • striped gate trenches 412 extend horizontally, and vertically extending sinker trenches 406 separate the different groups of gate trenches. Sinker trenches 406 are interconnected by a metal interconnect 432. Metal interconnect is shown as being enlarged along the right side of the figure forming a drain pad for bond- wire connection. Also a gate pad 430 is shown in a cut-out corner of one of the groups of gate trenches.
  • Fig. 5 shows a top view of a die housing the power device with sinker trenches in accordance with an embodiment of the invention.
  • the small circles depict the balls of a ball grid array package.
  • the outer perimeter region 506 includes the sinker trench, and the balls in outer periphery region 506 thus provide the drain connection.
  • Central region 507 represents the active region and the balls inside this region provide the source connection.
  • the small square region 530 at the bottom left corner of central region 508 represents the gate pad and the ball inside region 530 provides the gate connection.
  • the sinker trench structure 106 in Fig. 1 may be used to bring the backside connection of any power device to the top surface and as such is not limited to use with vertical trenched-gate power MOSFETs.
  • Same or similar sinker trench structures may be similarly integrated with such other vertically conducting power devices as planar gate MOSFETs (i.e., MOSFETs with the gate and its underlying channel region extending over and parallel to the silicon surface), and power diodes to make the anode or cathode contact regions available along the top for interconnection.
  • planar gate MOSFETs i.e., MOSFETs with the gate and its underlying channel region extending over and parallel to the silicon surface
  • power diodes to make the anode or cathode contact regions available along the top for interconnection.
  • Figs. 2-5 show layout implementations based on the open cell configuration, the invention is not limited as such.
  • the structure shown in Fig. 1 can also be implemented in any one of a number of well known closed cell configurations.
  • the dimensions in the cross section view in Fig. 1 and the top layout views in Figs. 2-5 are not to scale and are merely illustrative.

Abstract

A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epitaxial layer through the epitaxial layer and terminates within the substrate. The sinker trench is laterally spaced from the first trench, and is wider and extends deeper than the first trench. The sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.

Description

SEMICONDUCTOR POWER DEVICE HAVING A TOP-SIDE DRAIN
USING A SINKER TRENCH
CROSS-REFERENCES TO RELATED APPLICATIONS [0001] This application claims the benefit of US Provisional Application No. 60/598,678, filed August 3, 2004, incorporated herein by reference. Also, this application relates to Application No. 11/026,276 titled "Power Semiconductor Devices and Methods of Manufacture" filed December 29, 2004 incorporated herein by reference.
BACKGROUND OF THE INVENTION [0002] This invention relates in general to semiconductor power devices and more particularly to power devices with top-side drain contact using a sinker trench.
[0003] Unlike integrated circuits (ICs) which have a lateral structure with all interconnects available on the upper die surface, many power semiconductor devices have a vertical structure with the back of the die being an active electrical connection. For example, in vertical power MOSFET structures, the source and gate connections are at the top surface of the die and the drain connection is on the back side of the die. For some applications, it is desirable to make the drain connection accessible at the top side. Sinker trench structures are used for this purpose.
[0004] In a first technique, diffusion sinkers extending from the top-side of the die down to the substrate (which forms the drain contact region of the device) are used to make the drain contact available at the top surface of the die. A drawback of this technique is that the lateral diffusion during the formation of the diffusion sinkers results in consumption of a significant amount of the silicon area.
[0005] In a second technique, metal-filled vias extending from the top-side of the die clear through to the backside of the die are used to bring the back-side contact to the top-side of the die. Although, this technique does not suffer from the loss of active area as in the diffusion sinker technique, it however requires formation of very deep vias which adds to the complexity of the manufacturing process. Further, during conduction, the current is required to travel through long stretches of the substrate before reaching the drain contact, thus resulting in higher device on resistance Ron. [0006] Thus, an improved trench structure for making a back-side contact available at the top-side is desirable.
BRIEF SUMMARY OF THE INVENTION
[0007] In accordance with an embodiment of the invention, a semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epitaxial layer through the epitaxial layer and terminates within the substrate. The sinker trench is laterally spaced from the first trench, and is wider and extends deeper than the first trench. The sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.
[0008] In accordance with another embodiment of the invention, a semiconductor power device is formed as follows. An epitaxial layer is formed over and in contact with a substrate. The epitaxial layer and the substrate are of a first conductivity type. A first opening for forming a first trench and a second opening for forming a sinker trench are defined such that the second opening is wider than the first opening. A silicon etch is performed to simultaneously etch through the first and second openings to form the first trench and the sinker trench such that the first trench terminates within the epitaxial layer and the sinker trench terminates within the substrate. The sinker trench sidewalls and bottom are lined with an insulator. The sinker trench is filled with a conductive material such that the conductive material makes electrical contact with the substrate along the bottom of the sinker trench. An interconnect layer is formed over the epitaxial layer such that the interconnect layer makes electrical contact with the conductive material along the top surface of the sinker trench.
[0009] hi accordance with yet another embodiment of the invention, a semiconductor power device includes a plurality of groups of stripe-shaped trenches extending in a silicon region over a substrate. A contiguous sinker trench completely surrounds each group of the plurality of stripe-shaped trenches so as to isolate the plurality of groups of stripe-shaped trenches from one another. The contiguous sinker trench extends from a top surface of the silicon region through the silicon region and terminates within the substrate. The contiguous sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench.
[0010] In accordance with yet another embodiment of the invention, a semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate. Each of a plurality of stripe-shaped sinker trenches extends between two adjacent groups of the plurality of groups of stripe-shaped gate trenches. The plurality of stripe-shaped sinker trenches extend from a top surface of the silicon region through the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator only along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.
[0011] In accordance with another embodiment of the invention, a semiconductor package device houses a die which includes a power device. The die includes a silicon region over a substrate. Each of a first plurality of trenches extends in the silicon region. A contiguous sinker trench extends along the perimeter of the die so as to completely surround the first plurality of trenches. The contiguous sinker trench extends from a top surface of the die through the silicon region and terminates within the substrate. The contiguous sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench. A plurality of interconnect balls arranged in a grid array includes an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the contiguous sinker trench.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Fig. 1 shows a simplified cross sectional view of an exemplary vertical power device in accordance with an embodiment of the invention;
[0013] Figs. 2-4 show various top layout views of a vertical power device with one or more sinker trenches in accordance with exemplary embodiments of the invention; and [0014] Fig. 5 is a top view illustrating the locations of interconnect balls in a ball-grid array package relative to a sinker trench extending along the perimeter of a die housed in the ball- grid array package, in accordance with an exemplary embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION [0015] In accordance with an embodiment of the present invention, a sinker trench terminating within the silicon substrate is filled with a highly conductive material such as doped polysilicon or metallic material. The sinker trench is laterally spaced a predetermined distance from the active region wherein gate trenches are formed. The sinker trench is wider and extends deeper than the gate trenches, and is lined with an insulator only along its sidewalls. This technique eliminates the area loss due to side diffusion of the diffusion sinker approach, and results in improved on-resistance since a more conductive material is used than diffusion. Also, this technique requires a far shallower trench than that needed in the technique where a metal-filled trench extends from the top to the bottom of the die. The on- resistance is improved since the current need not travel through the entire depth of the substrate to reach the drain contact.
[0016] Fig. 1 shows a simplified cross sectional view of a vertical trenched-gate power MOSFET structure 100 in accordance with an exemplary embodiment of the invention. An n-type epitaxial layer 104 extends over an n-type substrate 102 which forms the back side drain. A sinker trench 106 extends from the top surface of epitaxial layer 104 through epitaxial layer 104 terminating within substrate 102. A dielectric layer 110 lines the sinker trench sidewalls. Dielectric layer 110 may be from any one of oxide, silicon nitride, silicon oxynitride, multilayer of oxide and nitride, any known low k insulating material, and any known high k insulating material. "Oxide" as used in this disclosure means a chemical vapor deposited oxide (SixOy) or a thermally grown silicon dioxide (SiO2). Sinker trench 106 is filled with a conductive material 108 such as doped polysilicon, selective epitaxial silicon (SEG), metal, or metallic compounds. Conductive material 108 is in electrical contact with substrate 102 along the bottom of sinker trench 106. Conductive material 108 thus makes the back-side drain available along the top side for interconnection. With the drain contact moved to the top surface, a back-side metal for contacting substrate 102 is no longer needed, but could be used in conjunction with the top side contact. The back side metal layer may be included for other purposes such as preventing the die from cracking and improving the heat transfer properties of the device. [0017] Well regions 114 of p-type conductivity extend along an upper portion of epitaxial layer 104. Gate trenches 112 are laterally spaced from sinker trench 106 by a predetermined distance Sl, and vertically extend from the top surface through p-type well regions 114 terminating at a predetermined depth within epitaxial layer 104. Sinker trench 106 is wider and deeper than gate trenches 112. Gate trenches 112 are lined with a dielectric layer 116. The dielectric along the bottom of gate trenches 112 may optionally be made thicker than the dielectric along the gate trench sidewalls. Each gate trench 112 includes a gate electrode 118 and a dielectric layer 120 atop gate electrode 118 to reduce the gate to drain capacitance. Source regions 122 of n-type conductivity extend along an upper portion of well regions 114. Source regions 122 overlap gate electrodes 118 along the vertical dimension. As can be seen well region 114 terminates a distance away from sinker trench 106. In one embodiment, this distance is dictated by the device blocking voltage rating. In another embodiment, well region 114 terminates at and thus abuts sinker trench 106. In this embodiment, for higher blocking voltage ratings, the thickness of the dielectric layer along sinker trench sidewalls needs to be made larger since the sinker dielectric is required to withstand a higher voltage. This may require a wider sinker trench if the conductive material 108 is required to have a minimum width for current handling purposes.
[0018] In the on state, a conduction channel from source regions 122 to epitaxial layer 104 is formed in well regions 114 along gate trench sidewalls. A current thus flows from drain terminal 124 vertically through conductive material 108 of sinker trench 106, then laterally through substrate 102, and finally vertically through epitaxial layer 104, the conduction channel in well regions 114, and source regions 122, to source terminal 126.
[0019] While the width of the gate trenches is generally kept as small as the manufacturing technology allows to maximize the packing density, a wider sinker trench is generally more desirable. A wider sinker trench is easier to fill, has lower resistance, and can more easily be extended deeper if needed. In one embodiment, sinker trench 106 and gate trenches 114 are formed at the same time. This is advantageous in that the sinker trench is self-aligned to the active region. In this embodiment, the widths of the sinker trench and the gate trenches and spacing Sl between sinker trench 106 and the active region need to be carefully selected taking into account a number of factors. First, a ratio of width Ws of sinker trench 106 to width Wg of gate trenches 112 needs to be selected so that upon completion of the trench etch step sinker trench 106 and gate trenches 112 terminate at tiie desired depths. Second, the width ratio as well as spacing Sl needs to be carefully selected to minimize micro-loading effect which occurs when trenches with different features are simultaneously etched. Micro- loading effect, if not addressed properly, may cause trenches with a wide opening have a wider bottom than top. This can lead to such problems as formation of pin-holes in the conductive material in the sinker trench. The micro-loading effect can also be minimized by selecting proper etch material. Third, the widths of the trenches and spacing Sl impact the device on-resistance Ron. In the article by A. Andreini, et al., titled "A New Integrated Silicon Gate Technology Combining Bipolar Linear, CMOS Logic, and DMOS Power Parts," IEEE Transaction on Electron Devices, Vol. ED-33, No. 12, December, 1986, pp 2025-2030, a formula is set forth in section IV-B at page 2028 which can be used to determine the optimum trench widths and spacing Sl for the desired Ron. Although the power device described in this article uses a diffusion sinker, the same principles relating to optimizing Ron can be applied in the present invention. This article is incorporated herein by reference.
[0020] The ratio of the width of the sinker trench to that of the gate trenches is also dependent on the type of conductive material used in the sinker trench. In general, a ratio of the sinker trench width to the gate trench width of less than 10: 1 is desirable. In one embodiment wherein doped polysilicon is used as the conductive material, a ratio of sinker trench width to gate trench width of less than 5:1 is desirable. For example, for a gate trench width of 0.5μm, a sinker trench width in the range of about 0.7μm to 2.5μm would be selected. If a metal or other highly conductive material is used in the sinker trench, a higher ratio (e.g., 3 : 1) is more desirable. Other than the relative width of the trenches, spacing S 1 between the sinker trench and the active region also impacts the micro-loading effect. A smaller spacing generally results in reduced micro-loading effect.
[0021] In one embodiment, the depth of the gate trenches in the epitaxial layer is selected to be close to the interface between substrate 102 and epitaxial layer 104 so that a slightly wider sinker trench would reach through to contact substrate 102. In an alternate embodiment, both the gate trenches and the sinker trench terminate within substrate 102.
[0022] In another embodiment, the sinker trench and the gate trenches are formed at different times. Thought the sinker trench would not be self-aligned to the active region, spacing Sl is not a critical dimension. Advantages of forming the two trenches at different times include elimination of the micro-loading effect, and the ability to optimize each trench separately. [0023] In accordance with an embodiment of the present invention, a method of forming the power transistor shown in Fig. 1 wherein the sinker trench and gate trenches are formed simultaneously, is as follows. Epitaxial layer 104 is formed over substrate 102. Next, a masking layer is used to pattern the gate trench and sinker trench openings. Conventional plasma etch techniques are used to etch the silicon to form the sinker trench and gate trenches. An insulating layer, e.g., oxide, is then formed along sidewalls and bottom of both the gate trenches and the sinker trench. Increasing the insulating thickness or increase in the dielectric constant of the insulating material is advantageous in minimizing the area between the depletion region and sinker trench, distance Sl, as some of the voltage from the depletion layer will be supported by the insulating layer thus reducing consumed silicon area by use of a sinker trench.
[0024] A nitride layer is formed over the oxide layer in all trenches. The oxide and nitride layers are then removed from the bottom of the sinker trench using conventional photolithography and anisotropic etch techniques thus leaving an oxide-nitride bi-layer along the sinker trench sidewalls. Alternatively, a combination of anisotropic and isotropic etching or isotropic etching alone can be used. The combination of anisotropic and isotropic etching can advantageously be used to respectively remove the nitride and oxide layers from lower sidewall portions of the trench sinker (e.g., those lower sidewall portions extending in the substrate or even in the epitaxial layer - this would advantageously reduce the on-resistance). The resulting thicker bi-layer of dielectric along sinker trench sidewalls is advantageously capable of withstanding higher drain voltages. The sinker trench and gate trenches are then filled with in-situ doped polysilicon. The doped polysilicon is then etched back to planarize the top of the polysilicon in the trenches with the top surface of epitaxial layer 104. Next, using a masking layer to cover the sinker trench, the polysilicon and oxide-nitride bi-layer are removed from the gate trenches. The gate trenches are then lined with a gate oxide layer and filled with gate polysilicon material. The excess gate polysilicon over the sinker trench is removed using a conventional photolithography and etch process to pattern the gate electrode. The remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods.
[0025] In an alternate method, after trenches are formed, a thick oxide layer (as mentioned above, to reduce the spacing of the sinker trench to the well region) is formed along the sidewalls and bottom of the gate and sinker trenches. The thick oxide layer is then removed from the bottom of the sinker trenches using conventional photolithography and anisotropic etch techniques thus leaving the sidewalls of the sinker trench lined with the thick oxide while the gate trenches are protected. Alternatively, a combination of anisotropic and isotropic etching can be used to also remove the thick oxide from lower portions of the trench sinker sidewalls. The oxide layer may act as a sacrificial insulating layer for the gate trenches to improve the gate oxide integrity. The sinker trench and gate trenches are then filled with in-situ doped polysilicon. The doped polysilicon is then etched back to planarize the top of the polysilicon in the trenches with the top surface of epitaxial layer 104. Next, using a masking layer to cover the sinker trench, the polysilicon and insulating layer are removed from the gate trenches. The gate trenches are then lined with a gate insulating layer and filled with gate polysilicon material. The excess gate polysilicon over the sinker trenches is removed using a conventional photolithography and etch process to pattern the gate electrode. The remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods.
[0026] In another method, once trenches are formed, an insulating layer, e.g., gate oxide, is formed (grown or deposited) along the sidewalls and bottom of the gate and sinker trenches. The gate oxide layer is then removed from the bottom of the sinker trenches using conventional photolithography and anisotropic etch techniques thus leaving an oxide layer lining the sidewalls of the sinker trench while the gate trenches are protected. Alternatively, a combination of anisotropic and isotropic etching or isotropic etching alone can be used. The combination of anisotropic and isotropic etching can advantageously be used to remove the gate oxide layer from lower sidewall portions of the trench sinker (e.g., those lower sidewall portions extending in the substrate or even in the epitaxial layer - this would advantageously reduce the on-resistance). The sinker trench and gate trenches are then filled with in-situ doped polysilicon. The doped polysilicon is then patterned using conventional photolithography techniques and etched to form both the sinker (drain) and gate electrodes. The remaining process steps for forming the insulating layer over the gate electrodes, the well regions, the source regions, the source and drain metal contact layers, as well as other steps to complete the device are carried out in accordance with conventional methods. [0027] In yet another method, the sinker trench and gate trenches are formed independently by using separate masking steps. For example, using a first set of masks and processing steps the gate trenches are defined and etched, lined with gate oxide, and filled with polysilicon. Using a second set of masks and processing steps the sinker trench is defined and etched, lined with dielectric layer along its sidewalls, and filled with a conductive material. The order in which the sinker trench and gate trenches are formed may be reversed.
[0028] Fig. 2 shows a simplified top layout view of the power device with sinker trench in accordance with an exemplary embodiment of the invention. The Fig. 2 layout view depicts a stripe-shaped cell configuration. Stripe-shaped gate trenches 212a extend vertically and terminate in horizontally-extending gate trenches 212b. As shown, the three groups of striped gate trenches are surrounded by a contiguous sinker trench 206. In an alternate embodiment shown in Fig. 3, sinker trenches 306 are disposed between groups of gate trenches (only two of which are shown) and are repeated at such frequency and spacing as dictated by the desired Ron. In one variation of this embodiment, to achieve the same Ron as the back-side drain contact approach, the spacing between adjacent sinker trenches needs to be two times the thickness of the wafer. For example, for a 4 mils thick wafer, the sinker trenches may be spaced from one another by approximately 8 mils. For even a lower Ron, the sinker trenches may be placed closer together. In yet another embodiment shown in Fig. 4, striped gate trenches 412 extend horizontally, and vertically extending sinker trenches 406 separate the different groups of gate trenches. Sinker trenches 406 are interconnected by a metal interconnect 432. Metal interconnect is shown as being enlarged along the right side of the figure forming a drain pad for bond- wire connection. Also a gate pad 430 is shown in a cut-out corner of one of the groups of gate trenches.
[0029] Fig. 5 shows a top view of a die housing the power device with sinker trenches in accordance with an embodiment of the invention. The small circles depict the balls of a ball grid array package. The outer perimeter region 506 includes the sinker trench, and the balls in outer periphery region 506 thus provide the drain connection. Central region 507 represents the active region and the balls inside this region provide the source connection. The small square region 530 at the bottom left corner of central region 508 represents the gate pad and the ball inside region 530 provides the gate connection.
[0030] As is readily apparent, the sinker trench structure 106 in Fig. 1 may be used to bring the backside connection of any power device to the top surface and as such is not limited to use with vertical trenched-gate power MOSFETs. Same or similar sinker trench structures may be similarly integrated with such other vertically conducting power devices as planar gate MOSFETs (i.e., MOSFETs with the gate and its underlying channel region extending over and parallel to the silicon surface), and power diodes to make the anode or cathode contact regions available along the top for interconnection. Many other variations and alternatives are possible, including use of shielded gate and dual gate structures in different combinations with various charge balancing techniques many of which are described in detail in the above-referenced commonly assigned patent application number 11/026,276 titled "Power Semiconductor Devices and Methods of Manufacture" filed December 29, 2004, which is incorporated herein by reference in its entirety. Also, although Figs. 2-5 show layout implementations based on the open cell configuration, the invention is not limited as such. The structure shown in Fig. 1 can also be implemented in any one of a number of well known closed cell configurations. Lastly, the dimensions in the cross section view in Fig. 1 and the top layout views in Figs. 2-5 are not to scale and are merely illustrative.

Claims

WHAT IS CLAIMED IS:
1. A semiconductor power device comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over and in contact with the substrate; a first trench extending into and terminating within the epitaxial layer; a sinker trench extending from the top surface of the epitaxial layer through the epitaxial layer and terminating within the substrate, the sinker trench being laterally spaced from the first trench, the sinker trench being wider and extending deeper than the first trench, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.
2. The semiconductor power device of claim 1 further comprising: a well region of a second conductivity type in the epitaxial layer; source regions of the first conductivity type in the well region, the source regions flanking the first trench; a gate dielectric layer lining at least the sidewalls of the first trench; and a gate electrode at least partially filling the first trench, wherein a gate electrode contact layer electrically contacting the gate electrode, a source contact layer electrically contacting the source regions, and a drain contact layer electrically contacting the substrate are all along one surface of the semiconductor power device.
3. The semiconductor power device of claim 1 wherein the conductive material includes one or more of doped polysilicon, selective epitaxial silicon (SEG), metal, and metallic compound.
4. The semiconductor power device of claim 1 wherein the insulator comprises one of oxide, silicon nitride, silicon oxynitride, multilayer of oxide and nitride, a low k insulating material, and a high k insulating material.
5. A semiconductor power device comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over and in contact with the substrate; a well region of a second conductivity type in the epitaxial layer; a gate trench extending through the epitaxial layer and the well region and terminating within the substrate, the gate trench including a gate dielectric layer lining at least the sidewalls of the gate trench, and a gate electrode at least partially filling the gate trench; source regions of the first conductivity type in the well region, the source regions flanking the gate trench; and a sinker trench extending from the top surface of the epitaxial layer through the epitaxial layer and terminating within the substrate, the sinker trench being laterally spaced from the first trench, the sinker trench being wider than the first trench, the sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.
6. The semiconductor power device of claim 5 wherein the conductive material includes one or more of doped polysilicon, selective epitaxial silicon (SEG), metal, and metallic compound.
7. The semiconductor power device of claim 5 wherein the insulator includes one of oxide, silicon nitride, multilayer of oxide and nitride, silicon oxynitride, a low k insulating material, and a high k insulating material.
8. A method of forming a semiconductor power device, comprising: forming an epitaxial layer over and in contact with a substrate, the epitaxial layer and the substrate being of a first conductivity type; defining a first opening for forming a first trench and a second opening for forming a sinker trench, the second opening being wider than the first opening; performing silicon etch to simultaneously etch through the first and second openings to form the first trench and the sinker trench such that the first trench terminates within the epitaxial layer and the sinker trench terminates within the substrate; lining the sinker trench sidewalls with an insulator; filling the sinker trench with a conductive material such that the conductive material makes electrical contact with the substrate along the bottom of the sinker trench; and forming an interconnect layer over the epitaxial layer, the interconnect layer making electrical contact with the conductive material along the top surface of the sinker trench.
9. The method of claim 8 wherein a ratio of a width of the first trench to a width of the sinker trench is pre-selected based on the target depths of the first trench and the sinker trench.
10. The method of claim 8 wherein a ratio of a width of the first trench to a width of the sinker trench and a spacing between the first trench and the sinker trench are pre- selected to minimize micro-loading effects.
11. The method of claim 9 wherein the ratio is less than four to one.
12. The method of claim 8 wherein the conductive material comprises polysilicon, and the ratio is about two to one.
13. The method of claim 8 wherein the insulator in the lining step is a bi- layer of oxide-nitride.
14. The method of claim 8 wherein the insulator includes one of oxide, silicon nitride, multilayer of oxide and nitride, silicon oxynitride, a low k insulating material, and a high k insulating material.
15. The method of claim 8 further comprising: forming a well region of a second conductivity type in the epitaxial layer; forming source regions of the first conductivity type in the well region such that the source regions flank the first trench; forming a gate dielectric layer lining at least the sidewalls of the first trench; and forming a gate electrode at least partially filling the first trench, wherein a gate electrode contact layer electrically contacting the gate electrode, a source contact layer electrically contacting the source regions, and a drain contact layer electrically contacting the substrate are all along one surface of the semiconductor power device.
16. The method of claim 8 wherein plasma etch is used in performing the silicon etch.
17. The method of claim 8 wherein in the lining step the sidewalls of the first trench are also lined with the insulator, the method further comprising: removing the insulator only from the bottom of the trench sinker so that the substrate along the sinker trench bottom becomes exposed.
18. The method of claim 8 further comprising: prior to the filling step, removing the insulator from a lower portion of the trench sinker using anisotropic etch.
19. The method of claim 8 wherein: the lining step comprises simultaneously lining the sidewalls and bottom of both the sinker trench and the first trench with the insulator, and the filling step comprises simultaneously filling both the sinker trench and the first trench with in-situ doped polysilicon; the method further comprising: prior to the filling step, removing the insulator from the bottom of the sinker trench only; removing the polysilicon and the insulator from at least inside the first trench; forming a gate dielectric lining the sidewalls and bottom of the first trench; and forming a gate electrode in the first trench.
20. The method of claim 8 wherein: the lining step comprises simultaneously lining the sidewalls and bottom of both the sinker trench and the first trench with a gate dielectric; and the filling step comprises simultaneously filling both the sinker trench and the first trench with in-situ doped polysilicon, the method further comprising: prior to the filling step, removing the gate dielectric from the bottom of the sinker trench only.
21. A method of forming a field effect transistor, comprising: forming an epitaxial layer over and in contact with a substrate, the epitaxial layer and the substrate being of a first conductivity type; defining a first opening for forming a gate trench and a second opening for forming a sinker trench, the second opening being wider than the first opening; performing silicon etch to simultaneously etch through the first and second openings to form the gate trench and the sinker trench such that the gate trench terminates within the epitaxial layer and the sinker trench terminates within the substrate; lining the sidewalls and bottom of both the sinker trench and the gate trench with an insulator; and removing the insulator from a lower portion of the sinker trench; filling the sinker trench and the gate trench with doped polysilicon such that the conductive material makes electrical contact with the substrate along the lower portion of the sinker trench.
22. The method of claim 21 further comprising: forming a well region of a second conductivity type in the epitaxial layer; forming source regions of the first conductivity type in the well region such that the source regions flank the gate trench; wherein a gate electrode contact layer electrically contacting the gate electrode, a source contact layer electrically contacting the source and well regions, and a drain contact layer electrically contacting the substrate through the sinker trench are all along one surface of the semiconductor power device.
23. The method of claim 21 wherein a ratio of a width of the gate trench to a width of the sinker trench is pre-selected based on the target depths of the first trench and the sinker trench.
24. The method of claim 21 wherein a ratio of a width of the gate trench to a width of the sinker trench and a spacing between the gate trench and the sinker trench are pre-selected to minimize micro-loading effects.
25. The method of claim 21 wherein the ratio is less than four to one.
26. The method of claim 21 wherein the insulator in the lining step is a bi- layer of oxide-nitride.
27. The method of claim 21 wherein the lower portion of the sinker trench includes the trench bottom and lower sidewall portions of the sinker trench extending in the substrate.
28. A semiconductor power device comprising: a plurality of groups of stripe-shaped trenches extending in a silicon region over a substrate; a contiguous sinker trench completely surrounding each group of the plurality of stripe-shaped trenches so as to isolate the plurality of groups of stripe-shaped trenches from one another, the contiguous sinker trench extending from a top surface of the silicon region through the silicon region and terminating within the substrate, the contiguous sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench.
29. The semiconductor power device of claim 28 wherein the silicon region is an epitaxial layer and the plurality of stripe-shape trenches are gate trenches, the semiconductor device further comprising: a well region of a second conductivity type in the epitaxial layer; source regions of the first conductivity type in the well region, the source regions flanking the gate trenches; a gate dielectric layer lining at least the sidewalls of each gate trench; and a gate electrode at least partially filling each gate trench, wherein a gate electrode contact layer electrically contacting the gate electrodes, a source contact layer electrically contacting the source regions, and a drain contact layer electrically contacting the substrate are all along one surface of the semiconductor power device.
30. The semiconductor power device of claim 28 wherein the conductive material includes one or more of doped polysilicon, selective epitaxial silicon (SEG), metal, and metallic compound.
31. The semiconductor power device of claim 28 wherein the contiguous sinker trench is wider and extends deeper than the plurality of stripe-shape trenches.
32. A semiconductor power device comprising: a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate; a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of stripe-shaped gate trenches, the plurality of stripe-shaped sinker trenches extending from a top surface of the silicon region through the silicon region and terminating within the substrate, the plurality of stripe-shaped sinker trenches being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.
33. The semiconductor power device of claim 32 wherein the silicon region is an epitaxial layer, the semiconductor device further comprising: a well region of a second conductivity type in the epitaxial layer; source regions of the first conductivity type in the well region, the source regions flanking the plurality of groups of stripe-shaped gate trenches; a gate dielectric layer lining at least the sidewalls of each gate trench; and a gate electrode at least partially filling each gate trench, wherein a gate electrode contact layer electrically contacting the gate electrodes, a source contact layer electrically contacting the source regions, and a drain contact layer electrically contacting the substrate are all along one surface of the semiconductor power device.
34. The semiconductor power device of claim 32 wherein the conductive material includes one or more of doped polysilicon, selective epitaxial silicon (SEG), metal, and metallic compound.
35. The semiconductor power device of claim 32 wherein the plurality of sinker trenches are wider and extend deeper than the plurality of groups of stripe-shape gate trenches.
36. The semiconductor power device of claim 32 wherein a drain interconnect layer electrically connects the plurality of stripe-shaped sinker trenches to a drain pad configured to receive a drain bond-wire.
37. A semiconductor package device housing a die which comprises a power device, the die comprising a silicon region over a substrate, the semiconductor package device comprising: a first plurality of trenches extending in the silicon region; a contiguous sinker trench extending along the perimeter of the die so as to completely surround the first plurality of trenches, the contiguous sinker trench extending from a top surface of the die through the silicon region and terminating within the substrate, the contiguous sinker trench being lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench; and a plurality of interconnect balls arranged in a grid array, an outer group of the plurality of interconnect balls electrically connecting to the conductive material in the contiguous sinker trench.
38. The semiconductor power device of claim 37 wherein the silicon region is an epitaxial layer and the first plurality of trenches are gate trenches, the semiconductor package device further comprising: a well region of a second conductivity type in the epitaxial layer; source regions of the first conductivity type in the well region, the source regions flanking the gate trenches; a gate dielectric layer lining at least the sidewalls of each gate trench; and a gate electrode at least partially filling each gate trench, wherein a gate electrode contact layer electrically contacting the gate electrodes, a source contact layer electrically contacting the source regions, and a drain contact layer electrically contacting the substrate are all along one surface of the semiconductor power device.
39. The semiconductor power device of claim 37 wherein an inner group of plurality of the interconnect balls surrounded by the outer group of the plurality of the interconnect balls electrically contact the source contact layer.
40. The semiconductor power device of claim 37 wherein the contiguous sinker trench is wider and extends deeper than the first plurality of trenches.
PCT/US2005/026928 2004-08-03 2005-07-29 Semiconductor power device having a top-side drain using a sinker trench WO2006017376A2 (en)

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JP2007524859A JP2008509557A (en) 2004-08-03 2005-07-29 Semiconductor power device with surface side drain using recessed trench
AT0930405A AT502860A2 (en) 2004-08-03 2005-07-29 POWER SEMICONDUCTOR ELEMENT WITH A TOP DRAIN USING A SINKER TRENCH
DE112005001675.7T DE112005001675B4 (en) 2004-08-03 2005-07-29 Power semiconductor device having a top drain using a sinker trench and method of manufacture
HK08106846.5A HK1112112A1 (en) 2004-08-03 2008-06-19 Semiconductor power device having a top-side drain using a sinker trench

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